JPH03217947A - Trouble position point-out method - Google Patents

Abstract

PURPOSE:To improve the point-out accuracy of a trouble position by extracting previously the data on the circuit state via a trouble analyzing subject computer, performing the logical simulation based on the extracted data on the circuit state, ad comparing the obtained circuit state of a normal mode with the circuit state of a trouble mode. CONSTITUTION:A trouble detecting computer system contains the trouble analyzing subject computers 1 - 3 connected to a single trouble analyzing computer 4. The circuit states of computers 1 - 3 are extracted and stored for each prescribed time, and the due processing is started at occurrence of troubles of computers 1 - 3. Then a logical simulator 15 performs the logical simulation of the circuit states of the computers 1 - 3 based on the stored circuit states set before occurrence of the trouble. A comparison processing part 14 compares successively the simulated circuit states with those of the stored ones. Based on these comparison results, the trouble positions of the computers 1 - 3 are pointed out.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a fault location pointing method, and is particularly suitable for testing electronic computers or when a fault occurs while a computer system is in operation. The present invention relates to a fault location pointing method that can point out the fault location.

[Conventional technology]

Conventionally, each device constituting a computer system is equipped with various hardware error detection circuits, and when these error detection circuits detect an error, an error indication flip-flop ( An error latch) is provided corresponding to each error detection circuit. When an error occurs, an error log containing data indicating the set/reset states of these error indicating flip-flops is collected by the service processors in the five systems, for example, and recorded in a disk device.

The error log collected when an error occurs is edited and output to the console display as necessary.
Or it can be printed out. The operator analyzes the error log data and diagnoses the location of the failure.

However, when an error occurs in one device of a computer system, the error is propagated one after another, and as a result, it is also detected as an error in the error check circuit at the propagation destination. It becomes difficult to point out accurately.

To deal with this, as a method for pointing out the location of a failure in an information processing device, as in the error processing method described in Japanese Patent Application Laid-Open No. 60-69752, when multiple error latches are lit, the relationship between the error latches is A method has been proposed for pointing out the location of a fault using a combination table showing the following. Furthermore, as in the diagnostic processing method described in Japanese Patent Application Laid-Open No. 61-95457, a method has been proposed in which, when multiple error latches are lit, the fault position is pointed out from the upper and lower positional relationships of each error latch. .

[Problem to be solved by the invention]

By the way, when an error indicating flip-flop (error-latch) is used as in the prior art described above, the accuracy of pointing out the fault location is determined by the breadth of the circuit coverage of the error latch.

However, error latches that are generally provided in correspondence with error detection circuits installed in computer system equipment are physically difficult to provide, even if the equipment becomes larger and more complex. Because there is a limit, 1
The circuit range of the two error latches must become wider. For example, one error latch may cover a plurality of printed circuit boards and LSIs that constitute a processing device. This makes it difficult to accurately pinpoint the location of the failure.

Furthermore, as the logic of a computer system becomes more complex, it becomes difficult to create a combination table that shows the relationship between error latches, and it becomes difficult to construct logic while giving error latches a higher-lower positional relationship. becomes difficult.

The present invention has been made to solve the above problems.

An object of the present invention is to provide a fault location pointing method that improves the accuracy of fault location pointing.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

In order to achieve the above object, the fault location pointing method of the present invention is a fault location pointing method that extracts the circuit state of a computer to be analyzed and points out the fault location from the extracted circuit state. The circuit state of the computer is extracted and stored at predetermined time intervals, processing is started when a failure occurs in the computer to be analyzed, and logical simulation of the circuit status of the computer to be analyzed is performed from the stored circuit state before the failure occurs. The circuit state of the logic simulation result is sequentially compared with the stored circuit state, and the fault location of the computer to be analyzed is pointed out based on the comparison results.

[Effect]

The fault location pointing method here is a fault location pointing method that extracts the circuit state of the computer to be analyzed and points out the fault location from the extracted circuit state.

In order to identify the location of a fault in a computer to be analyzed, the circuit state of the computer to be analyzed is extracted and stored at predetermined time intervals, and processing is started when a failure occurs in the computer to be analyzed.
A logic simulation of the circuit state of the failure analysis target computer is performed from the stored circuit state before the occurrence of a failure, and the circuit state as a result of the logic simulation is sequentially compared with the stored circuit state. Based on this comparison result, the location of the failure in the computer subject to failure analysis is pointed out.

Here, we give the circuit state of the computer subject to failure analysis to the logic simulator before the failure occurrence, execute a logic simulation from the circuit state of the computer subject to failure analysis before the failure occurrence, determine the circuit state in normal condition, and perform failure analysis. Compare the circuit state of the target computer when a failure occurs and the normal circuit state obtained from the logic simulator. In order to improve the accuracy of pointing out the fault location, the circuit state of the logic simulation results and the stored circuit state are compared multiple times sequentially from before the fault occurs to when the fault occurs, and the error propagation state is compared. To make it easier to judge the problem and accurately pinpoint the location of the failure.

In logic simulation, changes in the circuit state inside a computer can be determined in detail using the logic design data of the computer as time changes in signal values of latches, gates, signal lines, etc. that make up the computer.

Therefore, by providing the circuit state of the failure analysis target computer before the occurrence of a failure to a logic simulator and executing a logic simulation from the circuit state before the occurrence of the failure, it is possible to obtain the detailed circuit state of the computer during normal operation. Therefore, by comparing the circuit state of the computer subject to failure analysis at the time of failure with the normal circuit state obtained from logic simulation, detailed signal value comparisons can be made at the latch, gate, and signal line levels. This makes it possible to pinpoint fault locations with high accuracy.

In addition, during normal data processing operations, computers operate at high processing speeds, so abnormal signals from the fault location may propagate after a fault occurs until the fault is recognized outside the computer. , when comparing circuit states, there is a possibility that signal values will not match over a wide range of devices. Therefore, by sequentially comparing the circuit states a plurality of times before a failure occurs, it is possible to determine the propagation status of the abnormal signal, and it is possible to narrow down the range in which the failure location can be pointed out. This makes it possible to pinpoint the fault location with high accuracy.

〔Example〕

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

FIG. 1 is a block diagram showing the configuration of main parts of a failure detection computer system according to an embodiment of the present invention. In FIG. 1, numerals 1, 2, and 3 are failure analysis target computers, and 4 is a failure analysis computer whose normal operation has been confirmed. A plurality of failure analysis target computers 1, 2.3 are connected to one failure analysis computer 4 to constitute a failure detection computer system. The failure analysis target computer 1 is provided with a processing device 5 including a main memory, a circuit state extraction circuit 6, a communication control circuit 7, a service processor 8, etc., and is provided with a circuit state storage storage device 9 as an external storage device. It is being The failure analysis computer 4 is equipped with a processing unit 10 including a main memory, a communication control circuit 11, and a storage device 12 for storing the circuit state of the failure analysis target computer as an external storage device, and a circuit state storage device for logic simulation results. and a storage device 17 for storing a logical design file of a computer to be analyzed.

Further, the processing device 10 of the failure analysis computer 4 is provided with a comparison processing section 14 for a comparison processing function, a logic simulator 15 for a logic simulation processing function, and an operating system 16 for controlling each processing function. . Note that the processing functions required by this failure analysis computer 4 are a comparison processing function and a logic simulation processing function, and a processing device in which the processing functions of Niku et al. are separately implemented as firmware may be used. In this failure detection computer system, the other computers 2 and 3 connected to the failure analysis computer 4 have the same internal configuration as the failure analysis computer 1, although not shown. ing.

The failure analysis target computer 1 includes a processing device 5 including a main memory, an operating system 5a that performs system control operations, and a user program 5 executed under the operating system 5a.
b is read and operated. The operating status of the hardware is constantly monitored and managed by the service processor 8. In addition, even during data processing, the processing device 5 receives an interrupt instruction issued from the service processor 8, and uses the circuit state extraction circuit 6 to extract the internal state of the failure analysis target computer 1, the currently executing command, and the like. Previous and subsequent commands,
The state of the internal registers and other circuit state data at that time are extracted and stored in the circuit state storage storage device 9 via the circuit state extraction circuit 6. The circuit state storage storage device 9 stores a plurality of extracted data of the circuit state of the failure analysis target computer 1 extracted by the service processor 8 periodically issuing interrupt instructions, together with the extracted time data. Ru. The extracted data stored here is
This serves as initial setting data for executing a logic simulation in the logic simulator 15 on the failure analysis computer 4, and comparison data for failure analysis. Note that the circuit state extraction circuit 6 operates independently of the processing device 5, and extracts the circuit state of the failure analysis target computer 1 even when a failure occurs (
(evacuation) and storing it in the circuit state storage storage device 9. Further, the communication control circuit 7 operates under the control of the service processor 8, and transmits the circuit states of a plurality of times stored in the circuit state storage storage device 9 to the communication control circuit on the failure analysis computer 4 side through the communication line. Send it to 11.

The failure analysis computer 4 is provided with a processing device 10 including a main memory and a communication control device 1111. Communication control circuit 11
receives circuit state data at a plurality of time points sent from the communication control circuit 7 on the side of the failure analysis target computer 1, and stores it in the circuit state storage storage device 12. The circuit state storage storage device 12 supplies stored circuit state data when the logic simulator 15 performs logic simulation processing. The processing device 10 includes an operating system 16 that performs system control operations therein;
A logic simulator 15 that is executed under this environment and a comparison processing section 14 are provided. logic simulator 15
By reading the logical design data of the failure analysis target computer from the logical design file 17, it is possible to logically reproduce the internal circuit of the failure analysis target computer 1, 2.3. By storing logical design data in the logical design file 17 in correspondence with the type of failure analysis target computer, logic simulation processing of the internal circuit state of failure analysis target computers 1 with different internal circuit configurations can be performed on a single computer. logic simulator 1
5 can be executed.

The logic simulator 15 has a function that, by inputting the circuit state at an arbitrary time, can reproduce the circuit state of the failure analysis target computer 1 at any time after that time. The data on the circuit state obtained is stored in the output result storage storage device 13 and can be retrieved when necessary. In this way, the circuit state data (memory device 12 for storing circuit state) sent from the failure analysis target computer 1 and the circuit state data generated by the logic simulator 15 (memory device 1 for storing power result) are combined.
3) are compared by the comparison processing unit 14, and the location of the failure is pointed out.

FIG. 2 is a diagram illustrating an operation for extracting circuit state data in a failure analysis target computer. The explanatory diagram in FIG. 2 shows the extracted circuit between the processing device 5 executing the user program, the circuit state extraction circuit 6, the communication control circuit 7, the service processor 8, and the circuit state storage storage device 9. It shows the flow of status data.

In the computer subject to failure analysis, the processing unit 5 executes the user program under the operating system environment, so when the system operation starts, the internal state of the circuit is sequentially changed in chronological order by the machine clock to perform processing. Is going.

The circuit state data at each time is obtained by temporarily stopping the operation in the processing device 5 by the service processor 8 issuing an interruption command 21 to the processing device 5.
Each data of the circuit state in the processing operation of the processing device 5 is fixed, the service processor 8 instructs the circuit state saving 22, and activates the circuit state extraction circuit 6 to extract it. The circuit state data extracted by the circuit state extracting circuit 6 at each time is sequentially stored in the circuit state storage memory circuit 9 at each time. Such processing is repeated in chronological order until the failure occurrence 23 is detected, and at each time tl, t2, t3, t
4,... ti,..., tn are sequentially stored. This process is carried out under the control of the service processor 8, but when a failure occurrence 23 is detected, the service processor 8 again instructs the circuit state saving 24, starts the circuit state extraction circuit 6, and extracts the circuit state data. do. At this time, the processing device 5 has temporarily stopped its operation due to a failure, and does not issue any particular interruption command. Then, the service processor 8 issues a transfer command 25 to the communication control device 7. Thereby, the communication control circuit 7 reads the circuit state data stored in the circuit state storage memory circuit 9 and sends it to the failure analysis computer side.

When the service processor 8 finishes sending the circuit state data including the time of failure, it performs a stop process 26.

In this way, the service processor 8 always uses the processing device 5 (
The state of the failure analysis target computer 1) is monitored, and in order to retain and store the circuit state at a certain time, an interrupt command is issued, and the circuit state extraction circuit 6 extracts the extracted data of the circuit state from the memory device for storing the circuit state. Store in 9. As a storage method, for example, data is read and written using the first-in-last-out method, and when the extracted data of the circuit state exceeds the specified number of times that can be stored, the oldest extracted data of the circuit state is discarded, and the extracted data of the circuit state is always stored. Stores temporally new extracted data within a specified number of times. Even when a failure occurs, the circuit state of the processing device 5 is extracted and stored by the circuit state extraction circuit 6, and then the service processor 8 issues a transfer command to the communication control circuit 7. The communication control circuit 7 that has received the information reads out the stored circuit state data from the circuit state storage storage device 9, and sends it to a fault analysis computer that has a logic simulation function and has been confirmed to be operating properly via the communication line. Forward. When this is completed, processing is performed to stop the system.

FIG. 3 is a flowchart showing the operation flow on the side of the failure analysis target computer. A series of operations on the computer subject to failure analysis will be explained with reference to the flowchart in FIG.

First, in step 31, the failure analysis target computer starts system operation. Next, in step 32,
It is detected whether the service processor 8 has issued an interrupt instruction to save the circuit state at the relevant time, and when the interrupt instruction is detected, the process proceeds to step 33, where the circuit state is saved. This circuit state saving process is performed by extracting and saving circuit state data of the failure analysis target computer 1 by the circuit state extraction circuit 6. The extracted circuit state data is stored in the circuit state storage storage device 9. The data extracted and stored at this time is, for example,
Data such as the status of all error latches (check latches), the values of major registers, the currently executing instruction and the instructions before and after it, the contents of main memory, and the time when the interrupt instruction was issued and extracted and saved. be. These data are required when the logic simulator 15 performs logic simulation processing, and are required for the failure analysis target computer 1.
This is data that can reproduce the circuit state at that time. This kind of circuit state data is extracted and stored by issuing periodic interrupt commands, and data on the circuit state at the time of multiple interrupt commands and issuances can be stored retroactively from the time the failure occurred. It is read out using an in-then-out method, and the latest information is always stored for multiple times starting from the time of failure. Also, if the storage device is of a first-in, first-out type with a predetermined capacity,
By simply storing the data sequentially in the storage device, multiple batches are always stored starting from the latest one. On the other hand, if no interruption instruction is detected in step 32, normal processing is performed in step 34. Next, in step 35, a system stop request is made by a stop command, and it is determined whether the system is stopped. If the system is not stopped, it is determined in the next step 36 whether or not a failure has occurred. If no failure has occurred, the process returns to step 32 and the process starting from the determination of the interruption command is performed again.

If the system is stopped in step 35, the process proceeds to step 39, where system stop processing is performed and the process is ended. In this way, depending on whether an interrupt command is detected or not, circuit state saving processing or normal processing is performed, and processing for determining whether the system is stopped or a failure has occurred is repeatedly continued.

During such processing, for example, an error latch lights up,
If it is determined in step 36 that a failure has occurred, the process then proceeds to step 37, where a process for saving the circuit state at the time of failure is performed. This process is similar to the process at step 33. Next, in step 38, the communication control circuit is activated to perform circuit state transfer processing, and the next step 39
Perform system stop processing and end the process.

The processing in these steps 36 to 39 is as follows:
When a failure occurs (step 36), the service processor 8
When a circuit state saving processing command is received, the circuit state extraction circuit 6 is used to store the extracted data of the circuit state in the circuit state storage storage device 9 (step 37). When the completion of this storage operation is confirmed, the communication control circuit 7 is activated by the service processor 8, and according to a certain transmission procedure, the extracted data of the circuit state arranged in chronological order stored in the circuit state storage storage device 9 and the failure occurrence The saved data of the circuit state at the time is transferred to the failure analysis computer 4 (step 38
). Thereafter, system shutdown processing is performed (step 39).

FIG. 4 is a flowchart showing a series of operations on the failure analysis computer side. Referring to FIG. 4, a process in which the failure analysis computer 4 performs a logical simulation of a circuit state and points out a failure location will be described.

When a failure occurs in the failure resolution target computer 1 and the circuit state data is transferred to the failure analysis computer 4 via the communication line, the failure analysis computer 4 first processes the transferred data in step 41. Store data in storage. That is, all the data transferred from the communication control circuit 11 is stored in the circuit state storage storage device 12. Next, in step 42, the logic simulator 15 is activated. When the logic simulator 15 is activated, next in step 43, logic design data corresponding to the failure analysis target computer is read from the logic design file 17. The read logic design data is given to the logic simulator.

Next, in step 44, the logic simulator is initialized with the transferred circuit state. This initial setting is performed by reading circuit state data of the oldest time (circuit state data close to the operation start time) into the logic simulator 15 from the circuit state storage storage device 12. Next, in step 45, a logic simulation is executed, and in the next step 46, the circuit state obtained from the logic simulation is stored in the memory device (the memory device 13 for storing logic results). Next, in step 47, it is determined whether or not the logic simulation process has been executed up to the failure occurrence time. If the logic simulation process has not been executed up to the failure occurrence time, the process returns to step 45. Repeat the process from Further, if it is determined in step 47 that the logic simulation process has been performed up to the failure occurrence time, then in step 48, the logic simulation is ended. That is, the logic simulator 15 is activated, logic simulation is repeatedly performed, the internal state of the failure analysis target computer 1 up to the time of failure occurrence is reproduced, and the results are sequentially stored in the storage device 13 for storing output results. Finish 15.

Next, in step 49, the comparison processing unit 14 is activated, and in the next step 50, comparison processing for comparing check latches and internal registers is performed.

This reads the circuit state data at each time when the interrupt instruction was issued in the failure analysis target computer 1 from the circuit state storage storage device 12, and also reads out the circuit state data at the corresponding time calculated by the logic simulation by the logic simulator 15. Read the status data from the output result storage storage device 13,
This is done by comparing the circuit state data of both. As the comparison data to be compared at this time, for example, data on the state of a check latch or the state of an internal register is used.

Then, in the next step 51, a determination result indicating the location of the failure is determined based on the comparison result, and the process ends.

As described above, according to this embodiment, in a failure analysis computer having a logic simulation function, a logic simulation is executed using circuit state data abstracted from a failure analysis target computer before a failure occurs. By sequentially comparing the obtained circuit state data during normal operation with the circuit state data extracted from the failure analysis target computer up to the occurrence of the failure, detailed information at the signal line level in each circuit state can be obtained. Parts can be compared and fault locations can be pinpointed with high accuracy. In addition, by extracting circuit state data multiple times before a failure occurs and extracting a large amount of circuit state data, the internal state changes rapidly within the processing device, and errors that occur can be propagated over a wide area. Even in the case of a failure, it is possible to trace the error propagation status back to the original circuit state where the failure occurred. Therefore, the location of the failure can be narrowed down.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

As explained above, according to the present invention, circuit state data is periodically extracted from a failure analysis target computer before a failure occurs, and logic simulation is performed using the extracted circuit state data. the normal circuit state that was
By comparing the circuit state at the time of failure, detailed comparisons can be made at the signal line level, and the fault location can be pinpointed with high accuracy.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the main parts of a fault detection computer system according to an embodiment of the present invention, and FIG. 2 is a diagram illustrating the extraction operation of circuit state data in a fault analysis target computer. FIG. 3 is a flowchart showing a sequence of operations on the failure analysis computer side, and FIG. 4 is a flowchart showing a series of operations on the failure analysis computer side. In the figure, 1, 2, 3... failure analysis target computer, 4 failure analysis computer, 5... processing device, 5a... operating system, 5b... user program, 6... circuit state extraction circuit, 7... Communication control circuit, 8... Service processor, 9... Memory device for storing circuit status, 1
0... Processing device, 11... Communication control circuit, 12...
13. Storage device for storing output results, 14. Comparison processing unit, 15. Logic simulation, 16. Operating system, 17. Logic design file.

Claims (1)

[Scope of Claims] 1. A fault location pointing method that extracts the circuit state of a computer to be analyzed and points out the fault location from the extracted circuit state, wherein the circuit state of the computer to be analyzed is extracted at every predetermined time. Processing is started when a failure occurs in the computer subject to failure analysis, and a logic simulation of the circuit state of the computer subject to failure analysis is performed from the stored circuit state before the occurrence of the failure, and the circuit state as a result of the logic simulation is and a stored circuit state, and the fault position of a computer to be analyzed is pointed out based on the comparison result. 2. A fault detection computer system for pointing out a fault location by the fault location pointing method according to claim 1, comprising: means for periodically sampling a circuit state of a computer to be analyzed; A memory means for storing the circuit state together with the time signal, and when the circuit state is sampled and stored more than a specified number of times, the circuit state at the oldest time previously stored in the memory means is erased and the newly sampled circuit state is stored. A memory control means, a means for determining a normal circuit state from a circuit state of a computer to be analyzed by using a computer having a logic simulation function, and a means for comparing two circuit states at an abnormal time and a normal state. A failure detection computer system characterized by the following. 3. A fault detection computer system that points out a fault location using the fault location pointing method according to claim 1, comprising a circuit state extraction circuit that collects the circuit state of a computer to be analyzed;
a service processor that performs control to periodically collect the circuit state of the failure analysis target computer using a circuit state extraction circuit;
A first-in, first-out storage device with a predetermined capacity that separately stores the collected circuit states together with time information, and a communication control circuit that sends out the data stored in the first-in, first-out storage device are provided on the side of the computer to be analyzed. A communication control circuit that receives circuit state data for failure analysis from the side, a logic simulator that performs logic simulation of the correct circuit state using logic design data of the computer to be analyzed, and two circuit states: abnormal and normal. A failure detection computer system characterized in that a comparison processing unit for comparison is provided on the side of a failure analysis computer. 4. Logical simulation of the circuit state of the computer subject to failure analysis is performed from the oldest stored circuit state before the occurrence of the failure, and the circuit state of the logical simulation result and the stored circuit state are compared to the oldest point. 2. The fault location pointing method according to claim 1, wherein the fault location pointing out method is characterized in that the fault location of the computer to be analyzed is pointed out based on the comparison result. 5. In the failure detection computer system according to claim 3, a plurality of failure analysis target computers are connected to one failure detection computer, and the communication control circuit on the side of the failure analysis target computer is configured to: A failure detection computer system, characterized in that a line is connected to a communication control circuit on the side of a failure analysis computer, and data stored in a first-in, first-out storage device is sent to the side of the failure analysis computer.