JPS6029133B2 - Fault diagnosis method - Google Patents

Description

[Detailed description of the invention] The present invention relates to a failure diagnosis method for an information processing device.

In general, methods for diagnosing faults in information processing equipment can be broadly divided into: ■ Test data for fault diagnosis and response data (
A method in which test data (expected values) are prepared in advance and this test data is used to diagnose the failure when a failure occurs.

■ A method for diagnosing failures by analyzing the failure state when a failure occurs.

There are two.

Method (2) requires test data and response data to be created in advance, which requires a large amount of development man-hours.

In addition, the hardware for inputting test data to the information processing equipment (
(scan-in function) is required. Method (2) does not require test data or response data, but the conventional method estimates the failure location from the failure state at the time of failure.
When the logic circuit to be diagnosed becomes complex, it becomes extremely difficult and time-consuming to analyze the failure state.

An object of the present invention is to provide a fault diagnosis method that solves the above-mentioned problems.

The purpose of this is to provide a retry control circuit that retries the diagnosed device a predetermined number of times when an error is detected, a diagnostic control circuit that reads out the operating state of the diagnosed device for each clock at the final retry, and If an error is detected as a result of the final retry, the diagnosis target device is diagnosed based on the operating state stored in the storage means. Next, details of the present invention will be explained with reference to the drawings.

The figure shows a block diagram of an embodiment of the present invention.

In the figure, 1 is a device to be diagnosed, 2 is a diagnostic control circuit, 3 is a retry control circuit, 4 is a retry counter, 5 is an error detection circuit, 6 is a simulator, 7 is a display device, 8 is a storage circuit,
9 and 10 are AND gates, 11 is a flip-flop, 1
2 is Or Gate, 13 and 14 are Batsufu Aregis Yu, 15
, 17 are scan-out data lines, 16 are scan-out signal lines, and 18 are clock signal lines. Next, the operation will be explained.

When the device to be diagnosed 1 generates an error during business operation, the error detection circuit 5 detects the error and starts the retry control circuit 3.

The retry control circuit 3 instructs the device to be diagnosed 1 to retry.
If no error is detected after retrying, business operation is continued. The diagnostic control circuit 2 collects the operating state at the time of retrial, and the number of trials is counted by the retry counter 4 and reaches a predetermined number of trials. When the final trial is started, the AND gate 10 is turned on and the flip-flop 11 is set. . Therefore, the clock signal that was being sent to the device to be diagnosed 1 through the band gate 9 is stopped, and at the same time, subsequent clocks are controlled by the diagnostic control circuit 2 and are applied to the device to be diagnosed 1 one clock at a time.

Next, the diagnostic control circuit 2 sends out a scan-out signal via the scan-out signal line 16 in order to read the operating state inside the device 1 to be diagnosed for each clock. Diagnosed device 1
The operating status within is read out to the diagnostic control circuit 2 via the scanout data output line 17,
5 and stored in the circuit state storage circuit 8. If no error is detected as a result of the final retry, the retry control circuit 3 instructs the continuation of business operation. If an error is detected, a hard machine check interrupt is generated and the diagnostic control circuit 2 starts up the simulator 6 at the same time as informing that recovery is impossible by retrying. The scan-out data stored in the storage circuit 8 is sent to the simulator 6 via the buffer memory 13. The simulator 6 performs a simulation based on the received operating state data, and as a result, displays the likely failure location on the display device 7 via the buffer register 14, and notifies the maintenance person. In addition to using a simulator to point out the failure location as shown in this embodiment, the operation status collected from the device to be diagnosed can be determined by printing out the operation status on a printer and visually finding the failure location. Alternatively, it is also possible to analyze the failure location using a program such as a logout analyzer.

As explained above, the diagnosis method according to the present invention does not require a huge number of man-hours to prepare test data and response data in advance unlike conventional methods, and also has a scan function for inputting test data into the device to be diagnosed. does not require.

Furthermore, according to this method, the history of the operating state of the device to be diagnosed at the time of retrial is stored, making it easy to analyze failures. In addition, when a failure occurs, a retry is immediately performed, and the operating status for each clock at the time of the retry is memorized, so it is also effective in diagnosing intermittent failures that would disappear due to a time delay in executing the diagnosis. This is a great method.

[Brief explanation of the drawing]

The figure shows a block diagram of an embodiment of the invention. In the figure, 1 is a device to be diagnosed, 2 is a diagnostic control circuit, 3 is a retry control circuit, 4 is a retry counter, 5 is an error detection circuit, 6 is a simulator, 7 is a display device, 8 is a storage circuit,
9 and 10 are AND gates, 11 is a flip-flop, 1
2 is an or gate, 13 and 14 are buffer registers, 15
, 17 are scan-out data lines, 16 are scan-out signal lines, and 1'8 are clock signal lines.

Claims (1)

[Claims] 1. A retry control circuit that causes the device to be diagnosed to retry a predetermined number of times when an error is detected, a diagnostic control circuit that reads out the operating state of the device to be diagnosed for each clock at the time of the final retry, and stores each of the operating states. 1. A fault diagnosis method comprising a storage means for diagnosing a device to be diagnosed based on the operating state stored in said storage means when an error is detected as a result of a final retry.