JPS5492152A - Fault diagnosis system - Google Patents

Fault diagnosis system

Info

Publication number
JPS5492152A
JPS5492152A JP15948177A JP15948177A JPS5492152A JP S5492152 A JPS5492152 A JP S5492152A JP 15948177 A JP15948177 A JP 15948177A JP 15948177 A JP15948177 A JP 15948177A JP S5492152 A JPS5492152 A JP S5492152A
Authority
JP
Japan
Prior art keywords
circuit
retrial
control circuit
operation state
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15948177A
Other languages
Japanese (ja)
Other versions
JPS6029133B2 (en
Inventor
Masami Kushihashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP52159481A priority Critical patent/JPS6029133B2/en
Publication of JPS5492152A publication Critical patent/JPS5492152A/en
Publication of JPS6029133B2 publication Critical patent/JPS6029133B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Retry When Errors Occur (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To obtain a diagnosis system which eliminates the need of diagnostic data and simplifies fault analysis, by providing a retrial control circuit which retries the operation of a diagnosed device, disgnostic control circuit which reads out the operation state, and a method which stores the operation state.
CONSTITUTION: When diagnosed device 1 generates an error during its operation, retrial control circuit 3 is actuated via error detection circuit 5 to give the instruction of the retrial of device 1. Diagnostic control circuit 2 collects the operation states of the retrials and counter 4 counts the number of retrials; and when circuit 3 starts the final retrial after the contents of counter 4 reaches the fixed number of times, FF11 is set via gate 10. Gate 9 stops clock signals and afterwards, circuit 2 supplies the signal to unit 1 clock by clock. Circuit 2 reads out operation states and stores them in memory circuit 8. By circuit 2, data stored in circuit 8 are sent out to simulator 6, simulation is performed on the basis of the data in the operation state, and its results are displayed on display unit 7 via buffer register 14, thereby making fault analysis.
COPYRIGHT: (C)1979,JPO&Japio
JP52159481A 1977-12-29 1977-12-29 Fault diagnosis method Expired JPS6029133B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52159481A JPS6029133B2 (en) 1977-12-29 1977-12-29 Fault diagnosis method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52159481A JPS6029133B2 (en) 1977-12-29 1977-12-29 Fault diagnosis method

Publications (2)

Publication Number Publication Date
JPS5492152A true JPS5492152A (en) 1979-07-21
JPS6029133B2 JPS6029133B2 (en) 1985-07-09

Family

ID=15694704

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52159481A Expired JPS6029133B2 (en) 1977-12-29 1977-12-29 Fault diagnosis method

Country Status (1)

Country Link
JP (1) JPS6029133B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6319526U (en) * 1986-07-25 1988-02-09
JPS63126907A (en) * 1986-11-17 1988-05-30 カネボウ株式会社 Shoulder pad

Also Published As

Publication number Publication date
JPS6029133B2 (en) 1985-07-09

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