JPS6363935B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system for controlling the operation of an emergency control circuit that is activated upon the occurrence of an abnormal condition that halts the execution of a normal program and reconfigures a normal system.

Conventionally, this type of emergency operation control method has a central controller or system monitoring device monitor the execution status of a program, and if normal program execution is stopped for some reason, emergency control is issued from these devices. A method is known in which a start signal is sent to the circuit, and the emergency control circuit reloads the initial setting program of the central control unit, thereby reconfiguring the data processing device.

According to this method, the central control unit is initialized when reconfiguring the data processing equipment, so the internal state of the central control unit is not saved, which makes it difficult to find the cause of the activation of the emergency control circuit. However, there is no other way than to estimate it from the contents stored in the main memory, and there is a drawback that it is difficult to perform accurate cause analysis.

The present invention is configured such that the internal state of the central control unit is first saved in the main storage device in response to the activation request signal of the emergency control circuit, and the emergency control operation is activated after waiting for the completion of the save operation. It is an object of the present invention to provide an operation control method for an emergency control circuit that can solve the drawbacks and obtain information effective in searching for the cause of activation of the emergency control circuit.

The present invention provides a first system that is activated by an activation request signal of an emergency control circuit and saves the internal state of the central control unit in a predetermined area of a main memory.
means, a second means that is activated by the start request signal and monitors the time until the operation of the first means is completed; and a completion signal from the first means and a monitoring time from the second means. and third means for starting the operation of the emergency control circuit in response to any of the overflow signals.

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating an embodiment of the present invention.

The central control device 1 and the main storage device 2 are connected, and an overflow signal 31 of a failure detection timer 3 that monitors the execution of the program of the central control device 1 and a system abnormality signal 4 from a system monitoring device (not shown) are connected. is input to the OR circuit 5. The output of the OR circuit 5 is input to the control circuit 6 and the monitoring timer 7, and the control signal 61 from the control circuit 6 is connected to the central controller 1 in order to save the internal state of the central controller 1 to the main memory 2. Ru. Further, the completion signal 62 of the control circuit 6 and the overflow signal 71 of the monitoring timer 7 are input to the OR circuit 8, and the output of the OR circuit 8 is input to the emergency control circuit 9. Further, the completion signal 62 of the control circuit 6 is input to the monitoring timer 7 to reset it, and the fault detection timer reset signal 11 from the central control unit 1 is configured to reset the fault detection timer 3.

Next, the operation of the embodiment of the present invention will be explained.

When the central control device 1 is in a normal program execution state, it outputs the reset signal 11 before the failure detection timer 3 overflows, suppresses the generation of the overflow signal 31, and also prevents the system abnormality signal from the system monitoring device. 4 is also suppressed. When normal program execution is stopped due to some kind of failure or program error, one or both of the overflow signal 31 of the failure detection timer 3 and the abnormality signal 4 from the system monitoring device is generated, and the OR circuit 5 The control circuit 6 and the monitoring timer 7 are started through the control circuit 6 and the monitor timer 7, respectively. Under the control of a control signal 61 from the control circuit 6, the internal states of general-purpose registers, flip-flops, etc. in the central controller 1 are saved in a predetermined area of the main memory 2. The reason why the area to be saved is determined in advance is that unless it is an area that will not be destroyed even after the system is reconfigured, it cannot be used to analyze the cause of the failure.

Thereafter, when the internal state of the central control device 1 has been saved to the main storage device 2, a completion signal 62 is output, and the initial setting and program of the central control device 1 are started by activating the emergency control circuit 9 through the OR circuit 8. The data processing device is reconfigured by controlling reloading and the like. Also, the completion signal 62
By resetting the monitoring timer 7, the completion of the save operation is instructed. This is because the overflow time of the monitoring timer 7 is set to a time slightly larger than the time required for the control circuit 6 to save the internal state of the central control unit 1 to the main storage device 2.
As a result, in the event of a failure in which a save operation cannot be performed, the overflow signal 71 of the monitoring timer 7 is output, and the emergency control circuit 9 can be activated through the OR circuit 8. When the save operation is completed, the monitoring timer 7 is reset to prevent the overflow signal 71 from being generated.

FIG. 2 is a block diagram illustrating the configuration of the control circuit 6 in more detail. A counter 63 connected to the output of the OR circuit 5 and incremented at a constant cycle, and a read-only memory 64 that is addressed by the counter 63 and stores control information to the central controller 1.
and a register 65 that latches read information from the read-only memory 64 and outputs a control signal 61 and a completion signal 62.

FIG. 3 is a diagram showing details of the information latched in the register 65, including a field SR indicating the register number to be saved to the main memory 2, a field DA indicating the save destination address,
It includes a field PR that instructs the start of a save operation and a field ED that instructs the completion of this operation.

Next, the operation of the control circuit 6 will be explained with reference to FIGS. 2 and 3. When the control circuit 6 is recorded by the output of the OR circuit 5, the counter 63 becomes ++ from the initial value.
The read-only memory 64 is accessed and the control information is read into the register 65. Referring to FIG. 3, the register 65 contains the number of the register to be saved to the main memory 2, the address of the save destination, and a write instruction for the save operation, so these information can be sent to the central controller 1. By sending out the control signal 61, the central controller 1 can execute a save operation to the main storage device 2. The save operation explained above is performed using the counter 63.
The completion instruction field ED of the register 65 increments at regular intervals and latches the read information from the read-only memory 64 accessed by the value of the counter 63 when all necessary internal state save operations are completed. The operation of the control circuit 6 is completed by configuring it to be "1".

Although one embodiment of the present invention has been described above by showing a specific configuration, the present invention is not limited to this embodiment. For example, the block that controls the saving operation of the internal state of the central controller 1 shown as the control circuit 6 to the main storage device 2 does not need to be an independent block from the central controller 1, but is a central controller under microprogram control. It goes without saying that there is nothing wrong with the device even if a part of the microprogram is added with a function to control the save operation.

As explained above, the present invention first saves the internal state of the central control unit in the main storage device and waits for the completion of the save operation without immediately starting the emergency control operation in response to the activation signal of the emergency control circuit. By configuring the emergency control circuit to wait before starting the emergency control operation, it is possible to secure information in the main memory that is useful for searching for the cause of the activation of the emergency control circuit. It has the effect of allowing analysis.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a data processing device having an emergency control circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of the control circuit 6 of FIG.
FIG. 3 is a block diagram of the register 65 shown in FIG. In the figure, 1...Central control unit, 2...Main storage device, 3...Fault detection timer, 4...System abnormal signal, 5...OR circuit, 6...Control circuit, 7...
Monitoring timer, 8...OR circuit, 9...emergency control circuit, 31...reset signal, 31...overflow signal, 61...control signal, 62...completion signal,
63...Counter, 64...Read-only memory,
65...Register, 71...Overflow signal.

Claims (1)

[Claims] 1. A central control unit, a main storage device, and an emergency control circuit that is activated by a activation request signal when the central control unit detects an abnormality or by an external activation request signal to reconfigure a normal system. a first means for being activated by the activation request signal and saving the internal state of the central control unit in a predetermined area of the main storage device; and a second means for monitoring the time until the operation of the first means is completed; and the emergency control circuit according to either the completion signal from the first means or the monitoring time overflow signal from the second means. An emergency operation control system comprising a third means for starting the operation.