JPS6256544B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for handling failures detected by a channel control device that controls a plurality of channel devices in a time-sharing manner.

In recent years, channel devices that manage data transfer between central processing units and input/output devices have become smaller due to two trends: miniaturization and function substitution of central processing units.
It has begun to take on the character of an input/output processing device with multiple channels arranged in a single channel control device.
On the other hand, the external device called the channel control device cannot be recognized from the central processing unit side, and therefore a failure due to abnormality detection in the channel control device must be reported as a failure of the channel device. However, depending on the type of abnormality in the channel control device,
In some cases, it may not be possible to identify which channels it controls. For example, if an abnormality occurs in the channel control device while the channel control device is searching for a control request interrupt from the channel or a channel activation instruction from the central processing unit, the channel number cannot be specified. In such a case, according to the prior art, (1) it is reported to the central processing unit by an "external device abnormality interrupt", or (2) a predetermined channel number is used, for example, the lowest number, or channel control is carried out. This was done either by reporting the number of the last channel the device was controlling to the central processing unit using an ``input/output interrupt.''

However, method (1) has the drawback that all channels controlled by the channel control device must undergo failure recovery processing. That is, failure recovery processing after an "external device abnormal interrupt" must be performed on multiple channels, which will impair system processing speed and availability. On the other hand, in the case of method (2), since the channel determined to be abnormal is not based on actual operation, there is a risk that recovery processing will not be performed on the program. In addition, the common drawback of both is that if the same failure occurs again after failure recovery processing, an "interrupt" will occur, and unnecessary failure processing will continue.
The problem is that the processing speed of the system decreases.

SUMMARY OF THE INVENTION An object of the present invention is to correct the drawbacks of the prior art described above, to prevent a decrease in system processing speed, and to provide a channel control device with high availability.

A feature of the present invention is that a channel control device that controls a plurality of channel devices in a time-sharing manner is not coupled to any channel device, and checks whether there is an interrupt from the channel device or activation of the channel device from the central processing unit. If a failure is detected in the channel control unit while searching, the failure report to the central processing unit is temporarily suppressed, and while the failure is being suppressed, the channel control unit receives an interrupt from the channel unit or an interrupt from the central processing unit. When the activation of a channel device is received, the inhibited state is released at that point, and a fault is reported to the central processing unit along with the address of the channel device.

Hereinafter, one embodiment of the present invention will be described in detail using the drawings.

FIG. 1 is a connection configuration diagram of input/output channels, where 1 indicates a central processing unit, 2 indicates an input/output processing unit, and 3 indicates an input/output device. The input/output processing unit (IOP) 2 consists of a plurality of channels (CH) 5 to 7 and a channel control unit (CHC) 4 that controls the CHs in a time-sharing manner. They are connected via an interface 9. Each CH is connected to the input/output device 3 via the I/O interface 11.
and is also connected to the channel interface 10.
Connected to CHC4. CHC4 is the control
It has a storage (CS) 8 and controls CHs 5 to 7 by the micro program stored therein. Hereinafter, the method of the present invention will be explained using the processing of CS read failure of CHC4 as an example.

FIGS. 2 and 3 are block diagrams of the processing flow of the microprogram. The processing flow of the micro program can be classified into three routines. The first routine is an "idle" routine, which waits for a control request from the CH or a CH activation instruction from the CPU. Usually, this routine waits while repeatedly executing a microinstruction that uses its own address as an unconditional branch address, or it executes a microinstruction for self-diagnosis. The second routine is the "CH control" routine, and when a control request from CH occurs, the microprogram is forcibly branched to the start address of the routine (called BI: break-in) and starts processing. do. The third routine is a "failure handling" routine that is started due to a CS read error. A forced branch operation to a "fault handling" routine is called an STL (steal) operation to distinguish it from a BI operation.

FIG. 2 is a processing flow when the microprogram detects a CS read error while executing the "CH control" routine. Point A and C
A "CH control" request occurs at point, and the micro program returns "CH control" from the "idle" routine.
Transferring to routine. At point B, the processing of the "CH control" routine is completed and the process returns to the "idle" routine again. The operation at this time is BO for BI operation.
(Break out) action. In the example of FIG. 2, no CS read failure occurs between A and B. A "CH control" request occurs again at point C, and BI
Action occurs. If a CS read failure occurs at point D during processing of the request, the microprogram starts "failure handling" by STL operation.
The "Failure processing" routine performs fault recovery processing such as rewriting the CS, and detects that a fault has been detected in the channel device that was performing "CH control".
Report to CPU and complete "fault handling". In this way, a CHC failure detected during "CH control" is
This can be reported as a failure of a channel that was controlled by CHC. On the other hand, when a CHC failure is detected when the CHC is not controlling any CH, that is, when it is "idle," it is not possible to determine which CH is at fault.

FIG. 3 is a failure processing flow according to the present invention.
If a CS read failure is detected at point A of the "idle" routine, the microprogram
The operation attempts to start "fault handling", but
Since this is a CHC failure detected during "idle", the start of the process is suppressed. This inhibited state continues until point B, where a "CH control" request occurs, and
At this point, control of the "fault handling" routine is started as the BI operates. Therefore, in the "fault handling" routine after BI operation, CHC faults are identified and
It can be treated as a CH failure.

FIG. 4 is an embodiment of the present invention, and shows an example of the structure of a portion of the CHC that is related to the present invention.
The microinstruction read from the CS 8 is set in the CS read register (CSOR) 12, and its operation section becomes an input to the decode circuit 17 via the signal line 20. The decoded output of the decode circuit 17 is given to each part of the device, thereby executing the microinstruction. On the other hand, usually
The address part of CSOR12 is connected via signal line 19.
It is set in the CS address register 21, and this is given to CS8 as the address of the next microinstruction. In the "idle" routine, e.g.
By making the microinstruction of the CSOR 12 an unconditional branch microinstruction and setting its address part to its own address, the microinstruction will be repeatedly executed.

A control request from CH arrives through the signal line 24, and when it is accepted by the request selection circuit 14,
Control request acceptance signal line 25 is excited. By exciting the control request acceptance signal line 25, the CH control indication latch 15 is set, and the BI address signal 31 is set in the CS address register 21 through the signal line 23. That is, the microprogram forcibly branches to the start address of the "CH control" routine, and processing of the "CH control" routine begins. While running this "CH control" routine
If there is a CS read failure, it is detected by the check circuit 13 and the check output line 22 is activated. By excitation of this check output line 22, the STL
The address is set in the CS address register 21 through the signal line 23, and a forced branch is made to the "fault handling" routine.

On the other hand, when the CH control display latch 15 is in the reset state, that is, when it is displaying idle, when the check circuit 13 detects a CS read failure and the check output line 22 is excited, the latch circuit 15 The address update suppression circuit 1 uses the output 28 of
6 is activated, and its output 29 suppresses subsequent updating of the CS address and execution of microinstructions. Therefore, according to the STL address set in the CS address register 21, the first microinstruction of the "fault handling" routine is transferred to the CS read register 12.
Processing stops when the data is read out. This state continues until a CH control request is issued on line 24 and accepted by request selection circuit 14. When a CH control request is accepted and the control request acceptance signal line 25 is excited, the CH control indicator latch 15 is set, and the address update suppression circuit 16 is reset to prevent CS address update and microinstruction execution. The suppressed state is released. As a result,
The operation part of the first microinstruction of the "failure handling" routine read into the CS read register 12 becomes the input to the decoding circuit 17, the address part is set in the CS address register 21, and the "fault handling" routine is executed. be done. In addition,
The CH control display latch 15 indicates the decoding circuit 17
When the CH control signal is decoded, it is reset through the reset signal line 27.

According to such an operation, even if the fault processing is completed and the routine returns to the idle state and the fault is detected again in the routine, nothing will be done to the fault detection reporting CPU unless the next control request occurs. do not have.

As is clear from the above description, according to the present invention, when a channel control device that controls a plurality of channel devices in a time-sharing manner detects a failure in the channel control device in a state where it is not connected to any channel device, , by temporarily inhibiting reporting of the failure to the central processing unit, thereby preventing a decrease in the processing speed of the central processing unit due to unnecessary failure reporting. Furthermore, according to the present invention, during the above-mentioned suppression,
When a channel control device receives an interrupt from a channel device or an activation of a channel device from a central processing unit, it can report a failure to the central processing unit using the number (address) of the channel device.

[Brief explanation of the drawing]

FIG. 1 is a connection configuration diagram of an input/output channel targeted by the present invention, FIGS. 2 and 3 are processing flow diagrams of a micro program of a channel control device, and FIG.
The figure is a block diagram of one embodiment of the present invention. 1... Central processing unit, 2... Input/output processing unit, 3...
Input/output device, 4... Channel control unit, 5, 6, 7...
Channel, 8... Control storage, 12...
CS read register, 13...Check circuit, 14
...Request selection circuit, 15...CH control display latch,
16...Address update suppression circuit, 17...Micro instruction decoding circuit, 21...CS address register.

Claims (1)

[Claims] 1 A method for handling failures detected by a channel control device that controls multiple channel devices in a time-sharing manner, in which the channel control device does not control any specific channel device and responds to control requests from channel devices or While searching for a startup instruction for the channel device from the central processing unit,
When a failure is detected in the channel control device, the failure is temporarily inhibited from being reported to the central processing unit, and upon receiving a control request from a certain channel device or a start instruction for a certain channel device from the central processing unit. 1. A failure handling method for a channel control device, characterized in that the inhibited state is released and a failure report is made to a central processing unit using the number of the channel device that has received the control request or activation instruction.