JPH0675800A - Fault processing system - Google Patents

Abstract

PURPOSE:To enable retry even though an instruction in execution is in a retry disabling area when a fault is generated in a conversion memory section. CONSTITUTION:When the fault of a conversion memory section 2 is detected by a fault detection mechanism 12, a reading register 3 and an instruction reading register 4 are held and a selector 11 selects a conversion memory fault processing microprogram start address 13 to start the microprogram. The microprogram notifies the fault processing processor (not shown in the illustration) of the fault. The fault processing processor reads the correct value of the conversion memory section 2 by the instruction reading register 4 from the fault processing processor storage device, performs re-load to the section 2, arranging the environment capable of retrying the instruction. As the all instructions supplied before the instruction with the fault generated are completed, the retry of the instruction can be performed without fail.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure processing method for a microprogram controller, and more particularly to a failure processing method for a failure of a conversion memory unit.

[0002]

2. Description of the Related Art In a conventional failure processing method for a microprogram controller, when a failure occurs in a conversion memory unit, the failure processing is immediately executed regardless of the state of an instruction being executed.

[0003]

SUMMARY OF THE INVENTION The above-mentioned conventional fault processing method is used when a fault is detected in the conversion memory unit.
Immediately, because a failure report was made and failure processing was performed, the instruction being executed updates the system resources (main memory, registers, etc.), and if the instruction being executed is in the area where retries cannot be performed, It has the drawback of causing job abort or system stoppage due to the failure of a subsequent instruction that is not related to the instruction being executed.

[0004]

A failure processing system of the present invention comprises a control storage unit for storing a microprogram routine for each instruction and a conversion memory unit for holding start information of a microprogram corresponding to each instruction. In the failure processing method of the microprogram controller having, a register for holding a microprogram start address of a next instruction is provided between the control storage unit and the conversion memory unit,
When a failure occurs in the conversion memory unit, the failure information is held and the start address of the failure processing microprogram of the conversion memory is forcibly set in the register,
After the instruction being executed is completed, the failure processing microprogram is executed from its start address.

[0005]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the failure processing system of the present invention. As shown in FIG. 1, the conversion memory unit 2 is accessed through the signal line 101 by the instruction code in the instruction register 1, and microprogram start information such as the start address of the microprogram is read out from the signal line 102. (Below, CPDR
3) and is set.

When the fault detection mechanism 12 detects no fault in the CPDR3, the selector 11 does not operate, and the contents of the CPDR3 are transferred to the next micro program address register 6 (hereinafter NCSAR3), and when the instruction being executed is completed, the contents of NCSAR6 change to signal line 107.
To micro program address register 7 (below,
(CSAR7).

The control storage unit 8 storing the microprogram is accessed at the address of CSAR7 through the signal line 108, and the microinstruction of one step is transmitted from the signal line 110 to the microinstruction read register 9 (hereinafter,
It is read out to CSDR9) and set.

The output of each field of the CSDR9 directly controls the arithmetic circuit 10 through the signal line 111 to execute the micro instruction. Since one field of the control storage unit 8 indicates the next address, the signal line 10
The address of the microinstruction to be executed next is set in CSAR 7 via 9. In this way, micro-instructions are sequentially executed.

On the other hand, in the failure detection mechanism 12, the CPDR3
When a failure is detected in the, the failure status holding register 5 (hereinafter, referred to as FKR5) sets “1” via the signal line 104 and holds the failure status in order to hold the failure status. Hold on.

Further, the CPDR 3 and the instruction read register 4 are held via the signal line 104. In addition, a signal is sent to the selector 11 via the signal line 104 to select the conversion memory failure processing microprogram start address 13, and the conversion memory failure processing microprogram start address 13 is transmitted via the signal lines 105 and 106 to the NCS.
It is set to AR6.

If the instruction is being executed, the address of the NCSAR 6 that has been set is set in CSAR 7 after the completion of the instruction that is being executed, and the control storage unit 8 is accessed by the address of CSAR 7 to cause a failure. The process is started.

The failure processing microprogram notifies a failure processing processor (not shown) that a failure has occurred in the conversion memory unit 2. Upon receiving the notification, the failure processing processor reads CPDA4, recognizes the address of the conversion memory unit 2 in which the failure has occurred, reads the correct value of the conversion memory unit 2 at the address from the failure processing processor storage device, and converts the correct value. Reload the memory unit 2, initialize the hardware of the failed central processing unit,
Reset FKR5 to "0".

After that, an environment in which the faulty instruction can be retried is prepared, the central processing unit is notified, and the processing is terminated. Since all the instructions supplied before the faulty instruction have been completed, it is always possible to retry the instruction.

FIG. 2 is a diagram for explaining an example of the effect of this embodiment regarding whether or not a retry is possible.
The mark * in FIG. 2 indicates where a failure has occurred in the conversion memory unit 2, and the shaded portion indicates an area where retries cannot be performed.

FIG. 2A shows a flow when the instruction A and the instruction B are normally executed. In addition, FIG.
This is a flow when a failure occurs in the conversion memory unit in the retry-enabled area during the execution of the instruction A, and the retry-enabled area allows the retry from the instruction A after the failure processing is completed.

Next, FIG. 2 (c) is a flow chart of a conventional example in the case where a failure occurs in the conversion memory unit in the area where retries cannot be performed during the execution of the instruction A. The process is executed. Since the instruction A is a failure in a non-retry area, retry cannot be executed after execution of the failure processing, and the job is aborted or the system is stopped.

Further, FIG. 2 (d) is a flow of the present embodiment when a failure occurs in the conversion memory unit 2 in the area where retries cannot be performed during the execution of the instruction A. When a failure occurs,
The failure processing is executed after waiting for the end of the instruction A. After the failure processing is completed, the instruction A has already been completed, so that the instruction B can be retried.

[0018]

As described above, the fault processing system of the present invention has an effect that it is possible to relieve a fault in the conversion memory unit by 100%.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a fault processing method of the present invention.

FIG. 2 is a diagram illustrating an example of effects of the present embodiment regarding whether or not a retry is possible.

[Explanation of symbols]

1 instruction register 2 conversion memory unit 3 CPDR 4 CPDA 5 FKR 6 NCSAR 7 CSAR 8 control storage unit 9 CSDR 10 arithmetic circuit 11 selector 12 failure detection mechanism 13 conversion memory failure processing microprogram start address 101 to 112 signal line

Claims (1)

[Claims] 1. A failure processing method for a microprogram control device, comprising: a control storage section for storing a microprogram routine for each instruction; and a conversion memory section for holding microprogram start information corresponding to each instruction. A register for holding the microprogram start address of the next instruction is provided between the control storage section and the conversion memory section, and when a failure occurs in the conversion memory section, the failure information is held and the conversion is forcibly performed. A failure processing method, wherein a start address of a failure processing microprogram of a memory is set in the register, and after the instruction being executed is completed, the failure processing microprogram is executed from the start address.