JPS60254245A - False fault setting system - Google Patents

Abstract

PURPOSE:To omit a deciding circuit that starts and stops a diagnosis program according to the presence or absence of an answer given from a central processor, by actuating the diagnosis program through a service processor and asynchronously with the central processor. CONSTITUTION:A false fault setting system comprises a CPU10, a main memory 20 which stores a diagnosis program including a subprogram for execution of a series of processes to set a false fault, a service processor 30 and an interface line 40 set between the CPU10 and the processor 30. The CPU10 includes an arithmetic part 11, an instruction register 12, a decoder 13, a scan register control part 14, a stop address value applying register 15 and an address stop circuit 16. The processor 30 includes a memory part 31 which stores a diagnosis program and a diagnosis executing part 32. The diagnosis program of the processor 30 is actuated asynchronously with the CPU10.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a pseudo failure setting method for a central processing unit or the like.

(Prior Art) In the conventional pseudo failure generation method, a service processor sequentially executes a diagnostic program stored in the service processor to send a stop instruction signal to the central processing unit, and the central processing unit This signal stops the operation, and this stop is notified by sending a stop state signal to the service processor. After receiving this stop state signal, the service processor sets pseudo failure information in the central processing unit. be. Therefore, there is a drawback in that the service processor must be provided with means for interrupting the execution of the diagnostic program until it receives a stop state signal from the central processing unit during the process of executing the diagnostic program.

(Object of the Invention) An object of the present invention is to provide a pseudo failure setting method that eliminates the above-mentioned drawbacks.

(Structure of the Invention) The system of the present invention includes a storage means that stores a microprogram, and a first storage means that stores address information for the storage means.
a second holding means for holding fault information; and an execution means for stopping execution of the microprogram when the microprogram is executed up to an address corresponding to the address information held in the first holding means. a first processing device having: a first process for setting the address information in the first holding means; a second process for causing the execution means to start executing the microprogram; and a second holding means. a second processing device that executes a diagnostic program including a third process of setting pseudo failure information on the microprogram, and the execution unit starts executing the microprogram in response to the second process. The time from when the second processing device starts the second processing until the execution of the microprogram is stopped in response to the address information of the first holding means is equal to the time from when the second processing device starts the second processing to when the second Address information that will shorten the time required to start processing is set in the third holding means in the first processing.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

Referring to FIG. 1, which shows an embodiment of the system used in the method of the present invention, this embodiment uses a central processing unit (hereinafter referred to as CPU).
) 10, a main storage device 20 that stores a diagnostic program including a subprogram that performs a series of processes for setting a pseudo failure, and a service processor (hereinafter referred to as SVP).
) 30 and CPUI O,! :5VP30 and a twin interface line 40, and furthermore, C
PUl0 is a microprogram storage area (not shown)
an arithmetic unit 11 having a function of controlling the execution of a microprogram; an instruction register 12; a decoder 13 for decoding instruction codes; A microprogram stop signal line 112 and a diagnostic mode signal line 113 for instructing the arithmetic unit 11 to stop execution of the microprogram, a scan register control unit 14 for controlling the input/output of the scan register and its address, and A stop address value input register 15 that holds an address to stop execution, and an instruction to stop the execution of the micro program when the address set in the stop address value input register 15 is reached during the micro program execution process of the CPU 10. an address stop circuit 16 for inputting the stop address value sent from the scan register control unit 14, a signal line 1145- that informs the arithmetic unit 11 from the address stop circuit 16 to stop execution of the microprogram, and a stop address value input register 1 for inputting the stop address value sent from the scan register control unit 14.
5, a fault detection register 17 consisting of a plurality of flip-flops, and a fault detection register 17 from the scan register control unit 14.
a scan path 116 for setting a specific value to 7;
A signal line 117 connecting the stop address value input register 15 and the address stop circuit 16, a signal line 118 for sending instruction operand part information to the calculation unit 11,
The 8VP 30 includes a signal line 119 that connects the scan register control section 14 and the calculation section 11, and a signal line 121 that connects the main storage device 20 and the calculation section 11. , a diagnosis execution unit 32 that executes a diagnosis program, a storage unit 31 and a diagnosis execution unit 3
2 and a signal line 131 connecting the two.

Next, the operation of this embodiment will be explained. A maintenance-only instruction is stored in the instruction register 12, and when it is decoded by the decoder 13, a maintenance-only instruction detection signal is output from the decoder 13, and this signal is passed through the microprogram stop instruction signal line 112 and the diagnostic mode signal line 113. The signal is supplied to the arithmetic unit 11 via the signal. Arithmetic unit 11
stops the execution of the microprogram in response to the signal from the signal line 112, and interrupts the 5VP 30 via the interface 40 in response to the signal from the signal line 113. When the arithmetic unit 11 receives an interrupt response signal from the 5VP 30 in response to this interrupt, it reads the operand part of the maintenance-only instruction from the instruction register 12 via the signal line 118. This operand section describes a value indicating the load address in the main memory of the diagnostic program and a value of a specific address in the memory that holds the capacity value of the diagnostic program. The diagnostic program in the storage device 20 is transferred to the storage section 31 of the 8VP 30 via the interface 121 and the interface 40. Transfer ends at C
This is done by PU10 sending a transfer end signal to 5VP30 via interface 40, and upon receiving the transfer end signal, 5vP30 executes the diagnostic program in storage unit 31 step by step via signal line 131 to diagnostic execution unit. 32, and the diagnostic execution unit 32 executes each step to perform pseudo fault setting.

The contents of each step of the diagnostic program are as follows.

(1) Scan in the address value to be stopped into the stop address value input register 15 of CPU10. This is done via the interface 40, the signal a119, the scan register control section 14, and the signal line 115.

(2) Start execution of CPUIO. This is 5VP3
0 is executed by sending a microprogram start instruction to the arithmetic unit 11 via the interface 40. As a result, the CPU 10 executes until the address set in the stop address value input register 15 and stops execution at this address. The address stop circuit 16 compares the contents of the stop address value input register 15 with the microprogram address value in the currently executing instruction via the signal line 117 and signal line 114, and when they match, the microprogram is executed. This is done by sending a stop instruction to the calculation unit 11.

(The pseudo failure information is scanned into the failure detection register 17 in the 3B CPUIO. This is because the 5VP 30 sends a scan request to the calculation unit 11 via the interface 40, and the calculation unit 11 sends this request via the signal line 119. After the scan control unit 14 receives this request, the pseudo failure information sent from the 8VP 30 is sent to the 7th flip-flop of the failure detection register 17 corresponding to the flip-flop address that is subsequently sent. This is done by scanning in via the signal line 116.

+4) Start CPUIO again. As a result, C
A failure occurs in PU10 through the failure handling routine.

The present invention operates the 5VP 30 asynchronously in the sequence (1) to (4) above, regardless of the response from the CPU 10 or without any response from the CPU 10. During the execution of the diagnostic program, a response from CPUl0 is required when CPUl0 starts execution in step (2) and then stops at the address set in register 15. At this time, CPUl0 sends a stop state signal to 8VP30. Send. Conventionally, the 5VP 30 uses this stop state signal as an opportunity to scan pseudo failure information into the failure detection register 17. Therefore, until the stop state signal is detected, the 5VP 30 suspends the operation of the diagnosis execution unit 32 in order to prevent the process of step (3) from being executed.

In this embodiment, in step (2), 8VP30
The processing time CPU10 in CPU10 from starting execution of C-10-PUIO to stopping at the microprogram address set in the stop address value input register 15 is as follows: Then step (3) to get 5VP
30 inputs the microprogram stop address value to the stop address value input register 15 so that the processing time in SP(3) does not exceed 8VPT until just before 30 scans the pseudo failure information into the failure detection register 17 in the CPU10. Set to . As a result, the 5VP30 will always scan in the pseudo failure information after the CPU10 stops at the stop address.
There is no need to check the stop status signal from Q, and cp
The diagnostic program can be executed asynchronously with Ulo. Furthermore, the processing time 5VPT can be increased by inserting an appropriate number of no-operation instructions between the steps corresponding to step (2) and step (3) in the diagnostic program. This allows a later address in the microprogram to be set in the register 15 as a stop address.

(Effects of the Invention) As described above, the present invention has the ability to stop and start the diagnostic program depending on the presence or absence of a response from the central processing unit, since the service processor can operate the diagnostic program with the central processing unit in a non-active period. This has the effect of eliminating the need for a judgment circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a system used in the method of the present invention, 10... Central processing unit, 11... Arithmetic unit, 12...・Instruction register, 13...
Decoder, 112...Micro program stop signal line, 113...Diagnostic mode signal line, 1
4...Scan register control section, 15...
...Register for inputting stop address value, 16...
...Address stop circuit, 114...Signal line, 115...Scan path, 17...
Failure detection register, 116...Scan path,
117゜118.119...Signal line, 40...
...Interface, 30...Service processor, 31...Storage section, 32...
- Diagnosis execution unit, 121... interface,
131...Signal line, 20...Main storage device. 13-

Claims (1)

[Claims] A storage means storing a microprogram, a first holding means holding address information for the storage means, a second holding means holding failure information, and a microprogram executed and held in the first holding means. a first processing device having an execution means for stopping execution of the microprogram when the execution reaches an address corresponding to address information; a first process for setting the address information in the first holding means; and a first process for setting the address information in the first holding means; a second processing device for executing a diagnostic program including a second process for causing the means to start executing the microprogram and a third process for setting pseudo failure information in the second holding means; , the time from when the execution unit starts executing the microprogram in response to the second process until it stops executing the microprogram in response to the address information of the first holding means; Address information that reduces the time from when the second processing device starts the second process until it starts the third process is stored in the first holding means during the first process. A pseudo failure setting method characterized by setting.