JPH0472266B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] For example, in a vector processing device, a vector instruction is transferred from a scalar unit to a vector unit, and the vector instruction is executed by the vector unit. If an error occurs at the end of the pipeline in the scalar unit when a vector instruction is sent, the transfer of the vector instruction cannot be stopped.
Execution of this instruction will start. The present invention
In the vector unit, an identifier is added to the instruction, and based on this identifier, a means is provided to cancel an instruction in which an error has occurred or an instruction whose transfer has been interrupted, and multiple instructions can be canceled. Allows instructions to be retried (re-executed).

[Industrial application field]

The present invention, for example, as a vector processing device,
It relates to a device that transfers instructions from one instruction execution unit to another instruction execution unit, and in particular, an instruction that continuously transfers instructions to be executed by another instruction execution unit divided into multiple opcodes/data. The present invention relates to a transfer control device.

When an error related to an instruction occurs in a data processing device or the like, it is often possible to recover by retrying the instruction. It is desirable to be able to perform retries in response to such intermittent failures, regardless of the timing of error occurrence, even in vector processing devices that continuously receive instruction transfers.

[Conventional technology]

For example, a vector processing device includes a scalar unit (SU) that processes scalar instructions and a vector unit (VU) that processes vector instructions. If there is a vector instruction, the scalar unit transfers the instruction to the vector unit via the pipeline, and the vector unit executes the received vector instruction.

Conventionally, if an error in an instruction is detected in the scalar unit just before the transfer of an instruction from the scalar unit to the vector unit is complete, the vector unit will not be able to stop the transfer due to the timing. will start. Therefore, in the scalar unit,
It was not possible to retry the instruction that caused the error. That is, if such an error occurs and the instruction is retried, the vector unit will execute the same vector instruction twice depending on the timing, resulting in a logical contradiction.

[Problem that the invention seeks to solve]

While there is a trend for vector processing devices to be highly reliable, the scalar units of vector processing devices also perform advanced control over vector instructions, so the amount of microprograms tends to increase. Errors in RAM, etc. are becoming more likely to occur. That is, despite the strong demand for high reliability, the occurrence of errors tends to increase due to higher performance and functionality, and a solution to this problem is desired.

In a vector processing device or the like that continuously transfers instructions, most errors related to transferred instructions are errors in RAM or the like, and can often be corrected by retrying. Therefore, with regard to errors that occur in the scalar unit, it is desirable to be able to cancel and retry all instructions transferred to the vector unit whose execution should be suppressed, no matter what timing the error occurs.

The present invention aims to solve the above problem, and when a hardware failure occurs in the pipeline of the first instruction execution unit, the instruction canceled in the first instruction execution unit is transferred to the second instruction execution unit to which the instruction is transferred. , the purpose is to provide a means to cancel all commands and retry the command.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the present invention.

In FIG. 1, 10 is a first instruction execution unit that transfers instructions, 11 is a second instruction execution unit that executes the transferred instructions, 12 is an instruction transfer circuit that transfers instructions, and 13 is a second instruction execution unit that transfers error signals. an error signal transmission circuit for transmitting to the instruction execution unit 11;
14 is a register that receives the transferred instruction; 15
is the instruction identifier (ID) added to the received instruction
16 is an instruction ID generation counter that adds an instruction identifier to the received instruction.
17 is an instruction holding circuit that holds the received instruction;
18 is a current ID register that stores an instruction identifier of an instruction for which an error occurrence may be notified;
19 is a time monitoring circuit that monitors the time until the final timing when an error signal is sent; 20 is a transfer interruption detection circuit that detects that instruction transfer is interrupted midway; 21 is an error instruction cancel circuit that cancels an error instruction; 22 represents an interrupted instruction cancel circuit that cancels an instruction whose transfer is interrupted midway.

In the first instruction execution unit 10, the instruction transfer circuit 12 divides the instruction to be executed by the second instruction execution unit 11 into a plurality of opcodes/data and transfers them according to the instruction pipeline. The second instruction execution unit 11 receives the transferred instruction in the register 14 and sets the count value of the instruction ID generation counter 16 in the ID field 15. The count value of the instruction ID generation counter 16 is
Updated with each new command.

The instruction holding circuit 17 is constituted by several stages of buffer registers, and holds the transferred instruction together with the instruction identifier until the instruction is issued. The time monitoring circuit 19 is a counter that monitors the time of each instruction until the final timing at which an error signal may be sent from the first instruction execution unit 10.

When a hardware failure such as a machine check is detected in the first instruction execution unit 10, the error signal transmission circuit 13 transmits an error signal to the second instruction execution unit 11. Time monitoring circuit 19
When an error signal arrives during time monitoring, the error command cancel circuit 21 is activated. The error instruction cancel circuit 21 compares the contents of the current ID register 18 with the instruction identifier added to each opcode/data of the instruction held in the instruction holding circuit 17, and if they match,
A cancel signal is output to invalidate the instruction held by the instruction holding circuit 17.

The transfer interruption detection circuit 20 detects whether the transfer of instructions to be continuously sent from the first instruction execution unit 10 is
If the instruction is interrupted midway, it is detected and the interruption instruction cancel circuit 22 is operated. The interrupted instruction cancel circuit 22 compares the instruction identifier of the interrupted instruction with the instruction identifier added to each opcode/data of the instruction held in the instruction holding circuit 17, and if they match, cancels the instruction holding circuit. 17 outputs a cancel signal in response to the command held.

[Effect]

When an instruction is transferred from the first instruction execution unit 10 to the second instruction execution unit 11 by dividing it into an opcode and data, according to the conventional method, the instruction is transferred at a later timing in the pipeline of the first instruction execution unit 10. When an error or an error in a subsequent instruction occurs, the transfer of the instruction cannot be stopped due to timing. Furthermore, depending on the timing, subsequent instructions may also be transferred halfway.

According to the present invention, for the opcode/data of the instruction received by the second instruction execution unit 11,
An instruction identifier is added by the instruction ID generation counter 16 and held in the instruction holding circuit 17 until the instruction is issued. Also, a time monitoring circuit 19 guarantees the timing at which an error signal arrives for each instruction.
is provided. When an error signal is sent, the error instruction cancel circuit 21 selects the instruction corresponding to the signal based on the instruction identifier and cancels it. Furthermore, even if the transfer of one instruction is interrupted by the interrupt instruction cancel circuit 22, that instruction is canceled based on the instruction identifier.

Therefore, in the second instruction execution unit 11,
A plurality of instructions related to an error can be canceled, and after the cancellation is completed, it becomes possible to retry the instruction in the first instruction execution unit 10.

〔Example〕

FIG. 2 shows an example of a system to which the present invention is applied, FIG. 3 shows an embodiment of the present invention, and FIG. 4 shows a time chart of an embodiment of the present invention.

FIG. 2 shows an example of a vector processing device to which the present invention is applied. In FIG. 2, 30 is a main memory device, 31 is a main memory control device, 32 is a scalar unit that processes scalar instructions, 33 is a vector unit that processes vector instructions, and 34 is a vector instruction control unit that controls vector instructions. ,3
5 is a vector instruction execution unit for executing vector instructions, 36 is a load pipeline, 37 is a store pipeline, 38 is a vector register for storing vector data, 39 is an addition pipeline, 40 is a multiplication pipeline, 41 represents a division pipeline, and 42 and 43 represent internal signal lines.

The scalar unit 32 stores the following information from the main storage device 30:
Scalar instructions and vector instructions are read out via the main memory controller 31. Vector instructions flow through the pipeline of scalar unit 32 and are transferred to vector unit 33. The transferred instructions are
When the vector instruction control unit 34 in the vector unit 33 receives the instruction and the timing is ready to execute the instruction, a command is sent to the vector instruction execution unit 35 through the signal line 42 to start the instruction. The vector command signal unit 35 is
The signal line 43 connects each pipeline 36, 40,
41, a signal indicating that the instruction is being executed is sent to the vector instruction control unit 34. The vector instruction control unit 34 starts instructions when these pipelines become available, that is, when the signal of the corresponding pipeline on the signal line 43 turns OFF. The present invention primarily relates to this vector instruction control unit 34.

FIG. 3 shows a portion of the circuitry within the vector instruction control unit 34.

In FIG. 3, 50 is a fetch stage register (VFS), and the register 14 shown in FIG.
, 51 is a fetch buffer register (VFB), and 52 is a predecode stage register (VPS). The VFB51 and VPS52 correspond to the instruction holding circuit 17 shown in FIG. 53 is
VFB cancel circuit, 54 is VPS cancel circuit. 55 is an instruction interruption detection circuit in VFS, which corresponds to the transfer interruption detection circuit 20 shown in FIG. 56 is a timing counter, the first
This corresponds to the time monitoring circuit 19 shown in the figure. 60 is a data bus.

L1 and L4 to L6 are latches, L2 and L
3 represents a SET/RESET latch, R1 to R3 are registers, C1 to C4 are match detection circuits, A1 to A5 are AND circuits, and OR1 to OR4 are OR circuits.

In the scalar unit, as shown in Figure 4, a vector instruction is executed in four flows, and from the T state of the final flow, opcode IV1, opcode
It is assumed that vector commands are successively transferred to the vector unit in the order of IL2, data DV1, and data DV2.

By executing the vector instruction in the scalar unit, operation code IV1, operation code IV2, data DV1, data
DV2 and 1τ (machine cycles) are loaded, and the VALID signal indicating validity is turned ON. In the vector unit, latch L1 is activated by the VALID signal.
At the same time, an enable signal is input to the register R1, and the opcode/data of the instruction sent via the data bus 60 is received. order
The ID generation counter 16 generates an instruction identifier for each instruction, and generates an instruction identifier for each instruction.
Set in the ID field of register R1 to append to the data.

The opcode/data and instruction identifier of this VFS50 are
To VP52, if VPS52 is clogged
Sent to VFB51. Although the VFB 51 is shown in a simplified manner, it can be configured in multiple stages as necessary. The principle is the same even when there are multiple stages.

At the timing of the VALID signal for data DV2, the timing counter 56 operates and at the same time the instruction identifier held by the VFS 50 changes to the current ID.
Set in register 18. That is, the current
ID register 18 holds an instruction identifier related to the operation of timing counter 56.

Now, for example, at the ERR timing shown in Figure 4,
Assume that an error occurs in either vector instruction V1 or vector instruction V2. At this timing, all vector instructions V1 are transferred to the vector unit, and vector instructions V2 are also transferred to the vector unit only by the operation code IV1. In this case, the scalar unit tries to retry starting from the vector instruction V1, so the vector unit tries to retry the vector instructions V1 and V1.
It is necessary to cancel two instructions.
This is done as follows.

In the scalar unit, when an error occurs in the pipeline, the error latch is turned on and then a machine check detection signal is sent to the vector unit indicating that a hard error has been detected in the scalar unit.

In the vector unit, timing counter 5
When a machine check detection signal is received during the time monitoring of T1, T2, and T3 by 6, the AND circuit A
5 becomes "1", and the VFB cancel circuit 53 and VPS cancel circuit 54 operate.
Based on the instruction identifier held by the current ID register 18, the VFB cancel circuit 53 and the VPS cancel circuit 54,
By comparing the instruction identifier held by the VPS 52, an instruction to be canceled is found, and a cancel signal is output to the register holding the corresponding instruction. This cancel signal is
By resetting SET/RESET latches L2 and L3, the instruction held by the register is invalidated.

Furthermore, at the timing shown in Figure 4,
Since the next vector instruction V2 is also partially transferred to the vector unit, it is similarly canceled. Therefore, the instruction interruption detection circuit 5 in VFS
5 detects a break in the instruction transfer and inputs the detection signal to the VFB cancel circuit 53 and the VPS cancel circuit 54. The VFB cancel circuit 53 and the VPS cancel circuit 54 are each
Based on the instruction identifier held by the VFS 50, the interrupted instruction is searched for, and if there is a corresponding interrupted instruction, a cancel signal is sent to the VFB 51 and VPS 52.

The vector unit also receives a busy signal (VU Busy) when instructions remain in the vector unit.
The scalar unit is now notified. The output of the OR circuit OR4 is its busy signal, which is used by the vector instruction execution unit 3 shown in FIG.
If a signal (Execute) indicating that an instruction is being executed is received from 5, or if any of the latches L1 to L3 is ON, the flag becomes "1".

In the scalar unit, when an error occurs, the interrupt processing is started, but while the busy signal is "1", the start of the interrupt processing is made to wait.
As a result, the instruction termination order within the vector unit is correct for the instruction in which a hard error has occurred, and all instructions canceled within the scalar unit due to a hard error within the scalar unit are also canceled within the vector unit. Since the command is canceled, the command can be retried correctly.

[Effects of the Invention] As explained above, according to the present invention, before the command generation control stage of the second command execution unit,
In a system that has a buffer and can continuously receive instructions transferred from the first instruction execution unit, an error occurs in the first instruction execution unit and an instruction to be canceled in the scalar unit is canceled. Even if a plurality of instructions have already been transferred to the second instruction execution unit, the second instruction execution unit can also cancel all of those instructions. This makes it possible to retry commands, so high reliability can be achieved even in systems that speed up the transmission of commands.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is an example of a system to which the present invention is applied, FIG. 3 is an embodiment of the present invention, and FIG. 4 is a time chart of an embodiment of the present invention. In the figure, 10 is a first instruction execution unit, 11 is a second instruction execution unit, 12 is an instruction transfer circuit, and 13 is a second instruction execution unit.
is an error signal transmission circuit, 14 is a register, and 15 is an error signal transmission circuit.
ID field, 16 is instruction ID generation counter, 1
7 is an instruction holding circuit, 18 is a current ID register,
19 is a time monitoring circuit; 20 is a transfer interruption detection circuit;
21 represents an error instruction cancel circuit, and 22 represents an interrupt instruction cancel circuit.

Claims (1)

[Claims] 1. Information for continuously transferring instructions to be executed by the second instruction execution unit 11 divided into a plurality of opcodes/data from the first instruction execution unit 10 to the second instruction execution unit 11. In the processing device, the first instruction execution unit 10 includes an error signal transmission means 13 for transmitting an error signal to the second instruction execution unit 11 when an error related to the instruction to be transferred is detected; The instruction execution unit 11 generates an instruction to add an instruction identifier to each opcode/data of the instruction transferred from the first instruction execution unit 10.
an ID generating means 16; an instruction holding means 17 for holding each opcode/data of the transferred instruction together with an added instruction identifier; a time monitoring means 19 for monitoring time until the final timing at which an error signal is sent from the instruction execution unit 10; By comparing the instruction identifier with the instruction identifier of each opcode/data held by the instruction holding means 17, the error instruction canceling means 21 generates a cancel signal for the corresponding instruction, and detects that the instruction transfer is interrupted midway. When detected, an interrupted instruction canceling means 22 generates a cancel signal for the corresponding instruction by comparing the instruction identifier of the interrupted instruction with the instruction identifier of each operation code/data held by the instruction holding means 17. An instruction transfer control device comprising: