JPS57162012A - Fault processing system of channel controller - Google Patents

Fault processing system of channel controller

Info

Publication number
JPS57162012A
JPS57162012A JP56047533A JP4753381A JPS57162012A JP S57162012 A JPS57162012 A JP S57162012A JP 56047533 A JP56047533 A JP 56047533A JP 4753381 A JP4753381 A JP 4753381A JP S57162012 A JPS57162012 A JP S57162012A
Authority
JP
Japan
Prior art keywords
channel
fault
cpu
inhibited
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56047533A
Other languages
Japanese (ja)
Other versions
JPS6256544B2 (en
Inventor
Yoshio Sato
Tetsuji Ogawa
Nobuyuki Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56047533A priority Critical patent/JPS57162012A/en
Publication of JPS57162012A publication Critical patent/JPS57162012A/en
Publication of JPS6256544B2 publication Critical patent/JPS6256544B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To prevent decrease of a processing speed of a CPU, by once inhibiting a report of a falt to the CPU when the fault has been detected, and reporting it after a start instruction of a channel device has been received, in a channel controller for controlling plural channel devices by time division. CONSTITUTION:When a channel controlling part CHC of an input/output controller is in a state that no channel device is controlled, if a readout fault of a control storage CS8 occurs in the course of executing a channel control routine of a microprogram, it is detected by a checking circuit 13. In this case, an address updating inhibiting circuit 16 is operated by an output of a latching circuit 15, and by its output, updating of the CS address and a micro instruction are inhibited. Also, the fact that its fault is reported to the CPU is inhibited temporarily. After that, the address updating inhibiting circuit 16 is reset by a start instruction from the channel device, the inhibited state is released, and the report of the fault is executed to the CPU.
JP56047533A 1981-03-31 1981-03-31 Fault processing system of channel controller Granted JPS57162012A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56047533A JPS57162012A (en) 1981-03-31 1981-03-31 Fault processing system of channel controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56047533A JPS57162012A (en) 1981-03-31 1981-03-31 Fault processing system of channel controller

Publications (2)

Publication Number Publication Date
JPS57162012A true JPS57162012A (en) 1982-10-05
JPS6256544B2 JPS6256544B2 (en) 1987-11-26

Family

ID=12777757

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56047533A Granted JPS57162012A (en) 1981-03-31 1981-03-31 Fault processing system of channel controller

Country Status (1)

Country Link
JP (1) JPS57162012A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6324140U (en) * 1986-07-30 1988-02-17

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53142143A (en) * 1977-05-18 1978-12-11 Hitachi Ltd Fault notifying system for input/output device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53142143A (en) * 1977-05-18 1978-12-11 Hitachi Ltd Fault notifying system for input/output device

Also Published As

Publication number Publication date
JPS6256544B2 (en) 1987-11-26

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