JPH0370265B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a channel device that controls an input device (hereinafter abbreviated as I/O and includes an input/output control device) via an I/O interface.

Regarding the I/O interface, see Chapter 3, 3.3.3 of "System Design of Electronic Computers" by Kozo Hagashima, Sanpo.
Control of input/output interfaces, found in
IBM360I/O interface is a typical example.

FIG. 1 shows that in the interface,
It shows a time chart of a polling sequence that occurs based on a processing request from I/O. In FIG. 1, a channel issues a select out signal (SELOUT) when it detects a request in signal (REQIN) from an I/O. REQIN
The I/O that outputs the
When SELOUT is detected, it responds with the operational in signal (OPLIN) and address in signal (ADRIN). Also, set the I/O address to bus in at the same time as ADRIN. When the channel detects ADRIN from the I/O, it
Receives an address and responds with a command out signal (CMDOUT). If this is the I/O status byte (DSB) reporting sequence, the I/O issues the status in signal (STAIN) and sets the DSB to bus in at the same time. Also, if this is a data transfer sequence, I/
O outputs a service-in signal (SRVIN) and at the same time sets read data to bus-in in the case of a read operation. Channel is from I/O
When STAIN or SRVIN is detected, it receives DSB or read data and responds with a service out signal (SRVOUT). Note that the channel responds with CMDOUT to the former STAIN when the DSB cannot be received, and when it is necessary to stop data transfer to the latter SRVIN.

FIG. 2 is a block diagram in the case where the operation of the channel in the polling sequence is completely controlled by a microprogram. Here, the microprogram control section of the channel is common to that of the arithmetic processing unit (BPU) that executes instructions, and the operation of the channel is executed as a steal process. In Figure 2, 201 is REQIN
This is a detection circuit, and when it detects REQIN, it issues a steal request to the microprogram control section.
When the microprogram control unit receives this steal request, it interrupts the execution of the microprogram for the BPU that was being executed up to that point, and branches (steals in) to the microprogram for the channel polling sequence. In addition, 202
is the interface register (IFR),
It has a latch corresponding to each signal on the I/O interface line 205, and the input BSU
203 and output BUS 204, scan in and out can be performed by a microprogram.

FIG. 3 shows the microprogram flow for the polling sequence. When stealing in, first the bit corresponding to SELOUT in 202 is set. As a result, the SELOUT line of the I/O interface line 205 becomes '1'.
becomes. Next, set the initial value to the timer for monitoring the interface time. Next, scan out IFR202 while updating the timer,
Test that OPLIN and ADRIN are rising and loop. When OPLIN and ADRIN become 1', the I/O address on Bus In is received through IFR 202. And similarly to IFR202
Scan in to set CMDOUT and reset SELOUT. Next, test whether ADRIN has fallen by scanning out IFR202 while updating the timer, and loop. After that, proceed in the same way until STAIN, and STAIN becomes 0′.
Resetting SRVOUT terminates the steal processing and returns to the suspended microprogram for the BPU. This method is applied to small-scale information processing devices and can significantly reduce the amount of hardware.

However, in the above method, the channel continues to steal the microprogram until a series of responses from the I/O interface is completed, which reduces the processing time spent on the I/O side and the cable delay of the interface signal. etc. are included in the steal time, and the BPU
This method has the drawback of significantly increasing overhead in terms of macroinstruction execution time.

As a second example of the prior art, contrary to the first example, the response of the I/O interface in the channel is performed by hardware stage control,
There is a method of processing using a microprogram when STAIN is received.

FIG. 4 is a block diagram for implementing this method. In the figure, a channel includes a plurality of interface control units (IFC) 401 and a channel control unit (CHC) 402 that centrally controls them. Multiple IFC401s each have separate I/O
It is connected to the O interface line 403 and controls the I/O interface operation. CHC
402 is a linkage input register (LIR) 40
4 and linkage output register (LOR) 405
and has. The plurality of IFCs 401 are connected to the LIR 404 through a common input bus 406 and connected to the LOR 405 through a common output bus 407. CHC40
2 is IFC401 via LIR404, LOR405
respond to each other.

FIG. 5 shows the relationship between the time chart of the polling sequence and the microprogram processing according to FIG. 4. for example,
When REQIN on the I/O interface 403 connected to a certain IFC 401 becomes '1', that IFC 401 accepts it, activates its internal stage circuit, and sets SELOUT. Subsequent detection of OPLIN and ADRIN is controlled by the corresponding stage signal from the stage circuit, and uniform operations such as CMDOUT response and I/O address capture are also controlled by the stage signal from the stage circuit. Controlled by next
Detection of STAIN is controlled in the same way as OPLIN and ADRIN, and when it is detected, a DSB is captured and a response is performed. This response varies depending on the content of the subchannel, etc.
A signal called CHINT is sent to the CHC402.
The CHC 402 replaces this with a steal request to the microprogram control unit 408, which is commonly used with the BPU (not shown). At this time, LIR404
The I/O address DSB etc. necessary for microprogram processing are set in . When a steal is accepted, the LIR 404 is referenced in the steal processing of the microprogram. That is,
CHC 402 reads the subchannel corresponding to the received I/O address, and sets necessary signals to LOR 405 based on it. For example, when the CHC 402 finds that it only needs to respond with SRVOUT, it sets the SRVOUT set instruction code to the LOR 405 and sends the LOR to the IFC 401.
Transfer the contents of 405. IFC401 decodes this code and sends SRVOUT to interface line 4.
Send to 03.

The above method is applied to relatively large information processing devices, the steal time is suppressed to the necessary minimum, and the overhead on the execution time of macro instructions in the BPU is small. However, general I/O interface control (I/O
It also includes O interface abnormality handling. )
Since this is performed by hardware such as a stage circuit, there is a drawback that the amount of hardware increases. Furthermore, since the hardware becomes complicated, there is a drawback that the number of man-hours for logic design increases.

The purpose of the present invention is to eliminate the problems described in the prior art, and to reduce the amount of hardware by eliminating complicated control of the I/O interface by hardware. The purpose is to provide a channel device with good cost performance.

The channel device of the present invention issues a processing request to the microprogram control section when the input signal from the I/O interface changes. In the microprogram that responds to this processing request, the I/
A signal to be sent to the I/O interface is set by referring to information representing the progress state of the O interface sequence, and the sequence progress state display information is updated in preparation for the next reference. do.

FIG. 6 is a block diagram of a channel device according to an embodiment of the present invention. In FIG. 6, this channel device includes a plurality of channel units (CH) 61.
Contains 0. A microprogram control unit (MC) 600 controls execution of macro instructions in the BPU 601. The MC600 is also used to control channel devices, therefore the MC600
00 is connected to a plurality of CHs 610 through an output bus 620 and an input bus 621. Each CH61
Microprogram for 0 is BPU601
This is done by stealing that of the With this steel treatment, MC600 becomes CH610
It is possible to scan in and scan out the internal information.

Each of CH610 is connected to an I/O interface, and the feature of the present invention is particularly
It is located in the interface control section of 0. In the figure, 1
The details of this part are shown for only one CH, and the other channel units have the same configuration. 625 is REQIN in I/O interface,
An input control bus that receives input control signals such as OPLIN, and each of the plurality of input control signals is received by a separate signal line within the input control bus 625. 626 is an output control bus that transmits output control signals such as SELOUT, CMDOUT, etc. in the I/O interface, and each of the plurality of output control signals is transmitted by a separate signal line in the output control bus 626. . 611 is an input signal register (INLINER) connected to the input control bus 625;
5 has a bit connected to each of a plurality of signal lines. 612 is an output signal register (OUTLINER) connected to the output control bus 626;
It has a bit connected to each of a plurality of signal lines in output control bus 626. 618 is
In principle, this is a rise detection circuit (UP) in the INLINER 611 that constantly monitors all bits at the same time and outputs an output when the signal of any bit rises. The output signal of UP618 is
It is reported as CHINT to the MC 600 on the CHINT report line 630. CHINT is reported from each CH610 to the MC600 on a separate CHINT report line,
632 is a CHINT report line from another CH 610. 617 is a fall control circuit (DOWN) that monitors all the bits in the INLINER 611, and when the signal of any bit falls, raises the signal of a predetermined bit in the OUTLINER 612 according to the said bit. ). 615
is a counter (COUNTER) used for time monitoring of I/O interface signals, 616 is I/O interface bus in 627, bus out 62
This is a buffer register (BR) connected to 8 and used for sending and receiving I/O addresses, DSBs, commands, I/O read data, write data, etc. 6
15 is a counter (COUNTER) used for time monitoring of I/O interface signals, etc., and when a value other than '0' is set, a count of '-1' is activated. . 619 is
This is a zero detection circuit (CTO) that outputs an output when the count value of the COUNTER 615 changes from a non-zero value to '0'. The output signal of CTO619 is also
It is reported as CHINT to the MC 600 on the CHINT report line 630. 631 is UP618 or
The freeze instruction flip-flop (FRZ) is set by the output signal of CTD619.
When 31 is set, INLINER611 and
Update of COUNTER 615 is prohibited.

CHINT based on the output signal of UP 618 or CTD 619 requests MC 600 to branch (steal-in) the microprogram that was being executed to processing for CH 610. In this case, the MC600 determines which CHINT report line the CHINT is reported from.
Identify 10. Control for stealing in the MC 600 is conventionally known, and detailed explanation will be omitted here. Just one example is outlined below. That is, the address next to the final address of the microprogram that has been executed so far is saved in a storage means such as a register. Next, the address read from another storage means is used as the first address, and the address determined by the next address determination means normally used is adopted as the subsequent address, and the microprocessor for the device (channel unit) that made the steal request is used. Run the program. Next, when this microprogram is finished, the address saved as the start address is retrieved and execution of the original microprogram is resumed from there in the same manner as above. 700 is MC600
The interface control memory (IFCM) is an interface control memory (IFCM) whose contents can be referenced and updated by is set. this
The IFCM 700 may use local storage normally provided in the BPU 601.
IFSTGR stores information representing the progress state of the I/O interface sequence, as will be described later. As shown in Figure 8, the contents of one IFSTGR are as follows: bits 0 and 1 indicate interface mode (the combinations are '00' for channel idle, '01' for initial selection sequence, and '10' for interface mode). is a polling sequence, '11' is a burst operation end sequence), and bits 2 to 7 are a sequence code indicating how far the interface has progressed.

FIG. 9 is a time chart when this embodiment is applied to the same polling sequence as in FIGS. 1 and 5. It is clear that this embodiment may be applied to other initial selection sequences and burst operation termination sequences.

In Figure 9, the point where CHINT rises is
When REQIN, ADRIN, STAIN (SRVIN) starts up or COUNTER6
This is the point in time when the value of 15 becomes '0', and is indicated by , , in the figure. In this embodiment, the case where OPLIN increases is excluded from the CHINT set conditions. When CHINT goes up, a steal request occurs, and all processing is left to the microprogram. Also, this sequence
The relationship with the contents of IFSTGR is (00) 16 until SELOUT is issued, (80) 16 from SELOUT to CMDOUT, (81) 16 from CMDOUT to SRVOUT, and (00) 16 after SRVOUT. It corresponds to In other words, IFSTGR is
Channel idol until SELOUT is released.
The period from SELOUT to sending SRVOUT indicates a polling sequence.

FIG. 10 shows the flow of the microprogram steal processing in this embodiment. In steal processing, first, IFSTGR corresponding to the channel is read and the interface mode (bits 0, 1) is decoded. Thereby, the process branches to channel idle, initial selection sequence, polling sequence, or end of burst operation. Further IFSTGR at the branch destination
Decipher the sequence code (bits 2 to 7) of
Find out how far the interface sequence has progressed. As a result, the expected combination of input signals can be determined, and the contents of the INLINER 611 are checked to see if the corresponding signals are present. If the expected input signal has increased, the corresponding output signal is set in the OUTLINER 612 and the value of IFSTGR is updated in order to respond to it. If a combination other than expected values is detected during processing of the microprogram, it is treated as an interface error.

The above is an overview of the steal processing, but as an example, the case of the polling sequence shown in FIG. 9 will be explained in more detail. As shown in Figure 9,
When the rising edge of REQIN is detected by UP 618, CHINT is reported to MC 600 from here.
Also at this time, FRZ631 was set and INLINER
Updates to 611 and COUNTER 615 are prohibited.
When the MC600 receives this CHINT, it first selects the IFSTGR corresponding to that channel unit.
Read from IFCM 700 and decode its bits 0 and 1. At this time, it is '00' so we branch to the channel idle case. In this case, we know that the expected input signal line is REQIN, so we read INLINER 611 and test whether only the REQIN bit is set. If 'Yes', OUTLINER612
Set the SELOUT bit. next,
IFSTGR interface mode (bit 0,
1) is set to ``10'' (polling sequence), the sequence code (bits 2 to 7) is set to ``all 0'', that is, the value of IFSTGR is set to (80)16. Also, for COUNTER615, from SELOUT
In order to monitor the time until STAIN (SRVIN) rises, set an appropriate initial value that is not '0'. Finally, the FRZ631 is reset to '0' and the steal processing is completed. Note that when the FRZ 631 is reset, the COUNTER 615 restarts counting '-1', and the inhibition of updating the INLINER 611 is also lifted. The above is the route shown in FIG.

Next, the interface sequence is OPLIN,
Proceed to ADRIN, as shown in Figure 9.
When CHINT occurs at the rising edge of ADRIN,
Check the contents of IFSTGR in the same way as above. At this time, the value of COUNTER615 is usually not '0', but
Also, the value of IFSTGR is (80)16. Next is the OPLIN that we expect in INLINER611.
Test if the ADRIN bit is set. If 'Yes', add 1 to the sequence code (bits 2 to 7) of IFSTGR and update its contents to (81)16. At this time, since the contents of the bus line, that is, the I/O address, are stored in BR616, next time, in order to read the corresponding subchannel using this I/O address, BR616 is stored.
616 is read. Then, in response to ADRIN, the CMDOUT bit of OUTLINER 612 is set. Finally, the FRZ631 is reset to '0' and the steal processing is completed. Furthermore, FRZ63
When 1 is reset, COUNTER615 is '
The count of -1' is restarted, and the inhibition of updating INLINER 611 is also lifted. The above is the route shown in FIG.

Next, the interface sequence progresses, and as shown in Figure 9, when CHINT occurs at the rising edge of STAIN (SRVIN), processing follows the route shown in Figure 10, and finally STAIN
OUTLINER61 in response to (SRVIN)
Set the SRVOUT bit of 2 and
Clear the contents of IFSTGR. moreover
The contents of the COUNTER 615 are set to '0' to stop the counting operation and the FRZ 631 is reset.

In addition, in the above, when the content of COUNTER615 becomes '0', CHINT
occurs, and processing is performed according to the route shown in FIG. That is, in this case, COUTER6
Because the value of 15 is '0', it is due to timeout.
Determines CHINT and branches to interface error processing.

In the above embodiment, the period of steal processing based on CHINT indicated by , , in FIG. 9,
Updating INLINER611 is now prohibited for the following reasons. As mentioned above, during steal processing, the signal state of the INLINER 611 at the time the request for the steal processing is generated must be referenced, and a new signal must be input from the I/O interface before this reference.
This is to prevent INLINER 611 from being updated.

Furthermore, in the above embodiment, COUNTER615 is
During the steal processing period based on CHINT indicated by , , in FIG. 9, its update is prohibited. This is due to the following reason. steal request
Since the MC600 does not always accept requests immediately, the time required for steal processing is not always constant. Therefore, in order to avoid the effect of fluctuations in the above-mentioned steal processing time, the COUNTER
615 update is stopped. However, if changes in the steal processing time are ignored, updating of the COUNTER 615 may continue during this period.

According to the channel device of the above embodiment, the I/O
Most of the interface controls can be controlled by microprograms, eliminating the need for hardware such as complicated stage circuits. Also,
This can also significantly reduce the number of man-hours for design. In addition, the microprogram steal period of the channel device no longer includes processing time spent on the I/O side, time such as cable delay of interface signals, etc.
It is also possible to reduce the overhead in the execution time of BPU macro instructions.

In addition, in the above embodiment, except for CHINT due to signal time monitoring, CHINT is activated at the rising edge of the signal.
However, it is not necessary to do this, and CHINT may be generated at the falling edge of all or some of the signals.

Further, as a method for detecting the rise or fall of a signal, the target signal may be sampled at a high sampling rate, and a mismatch between the previous sampling value and the current sampling value may be detected.

In addition, MC600 has a channel device and BPU601
However, separate microprogram control units may be provided for the channel device and the BPU 601.

Further, although the COUNTER 615 is provided as an independent circuit, it may be set as one word in the IFCM 700.

Also, COUNTER615 performs a count operation of '-1', and when the count value reaches '0',
Although CHINT is generated, it is also possible to perform a count operation of '+1' and generate CAINT when the count value reaches a predetermined value.

Also, the count value of COUNTER615 is '0'
Although CHINT is generated only once when the count value reaches , it is also possible to set a plurality of arbitrary count values and generate CHINT when each count value is reached. If this method is adopted, it is also possible to generate CHINT periodically.

Furthermore, although the COUNTER 615 monitors the time from the rising edge of SELOUT to the rising edge of STAIN or SRVIN, it is easily inferred that it may also monitor the rising edge or falling edge of another signal.

Further, the count period of the COUNTER 615 may not be constant at all times, but may be made variable depending on the type of sequence and the progress of the sequence.

The present invention has been described in detail above. According to the channel device of the present invention, the I/O interface can be controlled mainly by the microprogram control device, so the hardware is simple, and the microprogram control section can be controlled by the BPU. Even when shared with other devices such as, the overhead of the device can be reduced.

[Brief explanation of drawings]

FIG. 1 is a time chart of a polling sequence in an I/O interface, FIG. 2 is a block diagram of a conventional technique, and FIG. 3 is a diagram showing a microprogram processing flow when using FIG. 2. FIG. 4 is a block diagram of a conventional technology different from FIG. 2, FIG. 5 is a diagram showing the relationship between a time chart and microprogram processing when FIG. 4 is used, and FIG. A block diagram of a channel device according to an embodiment of the invention, FIG. 7 is similar to that in FIG. 6.
The explanatory diagram of IFCM, Figure 8, is the same as in Figure 7.
An explanatory diagram of IFSTGR, FIG. 9 is a time chart of a polling sequence in an embodiment of the present invention, and FIG. 10 is a diagram showing a flow of steal processing of a microprogram in an embodiment of the present invention. In FIG. 6, 600...microprogram control unit (MC), 601...arithmetic processing unit (BPU),
610...Channel unit (CH), 611...Input signal register (INLINER), 612...Output signal register (OUTLINER), 615...Counter (COUNTER), 616...Buffer register (BR), 617...Down control circuit (DOWN) ),
618... Rise detection circuit (UP), 620... Output bus, 621... Input bus, 625... Input control bus, 626... Output control bus, 627... Bus in (BUSIN), 628... Bus out (BUSOUT),
700...Interface control memory (IFCM).

Claims (1)

[Claims] 1. It has a plurality of channel units and a microprogram control section common to the plurality of channel units, and each of the channel units has a signal reception circuit into which a signal from a connected I/O interface is input. , a signal sending circuit in which a signal to be sent to the connected I/O interface is set, and a change in the signal input to the signal receiving circuit, and if there is a change, a processing request is sent to the microprogram control unit. and information that changes as the polling sequence progresses based on processing requests from I/O in the connected I/O interface, and that indicates how far the sequence has progressed. and storage means for storing data for each channel, and the processing request issuing means samples the signal input to the signal reception circuit, and when the previous sampling value and the current sampling value are different, it is determined that there has been a change in the input signal. The microprogram control unit, which has received the processing request, recognizes the channel unit that issued the processing request, reads out the sequence progress status display information from the storage means corresponding to the channel unit, and executes the next processing request. refers to the information and sets a signal in the signal sending circuit, updates the sequence progress status display information with new content in preparation for next reference, sets it in the storage means, and performs the process for the process request. A channel device characterized in that it terminates.