JPS648860B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a data processing apparatus, and more particularly to a data processing apparatus having means for confirming failure processing due to a pseudo failure.

Prior Art As information processing systems become more complex and sophisticated, the processing functions for system failures also become more complex and diverse.
It has become necessary to maintain that level of reliability. Therefore, a method is used to generate a pseudo failure and check whether the processing function operates correctly.

Conventionally, a fault detection circuit is used to detect a fault by applying a pseudo fault to the actual circuit or by directly providing a pseudo fault signal to the fault detection circuit, and then the fault is detected via this circuit. A signal is sent to the fault processing function to notify that the problem has occurred, and the related circuits are activated. That is, it is necessary to add an adding circuit (for example, an OR circuit) for adding a pseudo fault to each circuit, resulting in an increase in hardware for fault processing confirmation.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a data processing device that reduces the amount of hardware required to confirm fault handling.

Structure of the Invention The data processing device according to the present invention includes a fault storage means for detecting and storing faults in each function of the device, and a writing means for writing state information of the device into the main storage means in response to occurrence of a fault. , and a processing means that initializes the device after the writing is completed, analyzes the status information written in the main storage means, and performs predetermined trouble handling, and its characteristics are as follows: means a starting means for starting a writing means at a specified time, and a status information modification that modifies at least one write data specified in advance during a writing operation of the writing means started by this starting means. It consists in having the means.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention includes a processing unit 100 that performs information processing operations, a main memory 200 that stores programs and data, and a main memory 200 that stores programs and data.
The memory access control section 300 controls access to 0, and the service processor section 400 performs failure processing, maintenance, etc.

The processing section 100 includes a plurality of packages 1, 2, and 3, and a diagnosis control section 4 that performs diagnosis of these packages. The package 1 is equipped with a plurality of circuits 11, 12, and 13 that perform predetermined functions, and error detection latch circuits 14, 15, and 16 are added to the outputs of each circuit to detect errors in each output. When an error occurs, it is detected and stored in the flip-flop circuit.
A logic "1" is sent to the terminal to notify that a failure has occurred. Packages 2 and 3 are equipped with circuits similar to package 1 regarding fault detection.

The diagnostic control unit 4 is a circuit that controls the interface between the service processor unit 400 and the processing unit 100, and allows the service processor unit 400 to recognize failure notifications from each package, and at the same time recognizes failure notifications from the service processor unit 400. Processing unit 1 by control
It performs diagnostic control of each circuit in 00.

Error log area 201 in main memory 200
is an area for storing status information of each part of the processing unit 100 at a certain point in time, and the address where the status information is stored is specified corresponding to each part.

A processor 401 in the service processor unit 400 is controlled by a program and handles failures.
It performs diagnosis, maintenance, etc., and the memory 402
stores programs, data, etc. for that purpose.

Flowcharts of this embodiment are shown in FIGS. 2 and 3.
A in FIG. 2 follows A in FIG. Referring to FIGS. 1 to 3, the operation of this embodiment will be described first with respect to the treatment when an actual failure occurs, and then with a failure handling operation confirmation test based on a simulated failure.

For example, if a fault occurs in the circuit 12 in the package 1 installed in the processing unit 100, this is detected by the error detection latch circuit 15, which stores the fact that the fault has occurred, and also performs diagnostic control via the OR gate 17. A logic "1" is sent to section 4 to notify that a failure has occurred. In response to the supply of the fault notification signal, the diagnostic control section 4 stops the clock of the processing section 100, freezes and holds the status information of each section at the time of the fault, and issues an interrupt to the service processor section 400 (step 51).

Thereafter, failure processing is performed by the operation of the processor 401. That is, first, it is determined whether or not the interrupt requests execution of a pseudo-failure setting command, which will be described later (step 52). In this case, due to a real obstacle,
After passing through the N branch of step 52, it is confirmed in step 64 that an actual failure has occurred, and step 62 is entered. If no actual failure has occurred, other processing is performed via the N branch of step 64, but since this is not the subject of explanation, the description will be omitted.

Next, the processor 401 collects the state information in the frozen processing unit 100 mentioned above. That is, the address of the package whose state information is to be collected first (hereinafter the contents stored in the package address register will be abbreviated as PKG-ADRS) is set in the package address register in the processor 401 (step 62). Furthermore, the start address of the error log area 201 in the main memory 200 (hereinafter the contents stored in the main memory address register will be abbreviated as MM-ADRS) in which the status information is to be stored is set in the main memory address register in the processor 401. (Step 63). Next, PKG-ADRS is sent to the diagnostic control unit 4 (step 65), and further
It instructs to read the state information of the flip-flop (F/F) that stores the occurrence of an error in the error detection latch circuit mounted on the package specified by PKG-ADRS (step 66). For this reading, a known method such as a method using a scan path or a switching method using a selector is used. The read status information is received and it is confirmed whether the F/F is installed in the package (steps 67 and 68), and if it is confirmed that the F/F is installed, a pseudo failure is detected. Based on the setting flag, it is determined whether execution of a pseudo fault setting command, which will be described later, is requested (step 69). In this case, due to an actual failure, the read status information is stored in the error log area 201 of the main memory 200 indicated by MM-ADRS (step 73). Next, in order to collect the next package status information, the contents of the main memory address register and package address register, MM-ADRS and PKG-ADRS, are updated (steps 74 and 76), and the process returns to step 65, where the process described above is performed. The operation is repeated to collect all state information in the processing unit 100. When it is confirmed in step 68 that the F/F is installed, there is no valid status information, so the process continues through the N branch of step 68 without storing this status information in the error log area 201. 75 to 76, and the next step is to collect the status information of the package.

It is confirmed in step 75 that the status information of all packages has been collected and stored, and the process goes through this Y branch to reach step 77, sets the false failure setting flag to 0, and in step 78, the diagnostic control unit 4 is informed of the processing unit 100. Instruct the initial settings and restore the state before the failure occurred. Thereafter, the status information collected in the error log area 201 of the main memory 200 is analyzed and troubleshooting is performed (step 79). This failure handling is a well-known technique and is not the subject of explanation of this embodiment, so its explanation will be omitted.

This concludes the explanation of what to do when an actual failure occurs, but the point is that what is necessary for failure handling is how to collect status information of each part at the time of failure.In other words, failure handling In order to confirm the operation, the question is how to create status information of each part in the error log area 201 at the time of failure. The above-mentioned matter, that is, a processing operation confirmation test using a pseudo failure will be described below regarding this embodiment. The processing section 100 is performing arbitrary processing, and the operation is confirmed when a failure occurs at a specified part of the processing section 100 at a specified time during the processing.

First, the diagnostic control section 4 issues an interrupt to the service processor section 400 (step 51). From then on,
Processor 401 proceeds with the operation. That is, it is recognized that this interrupt requests execution of an instruction for setting a pseudo fault (hereinafter referred to as a pseudo fault setting command) (step 52). The pseudo-fault setting command specifies at least the time at which the pseudo-fault should occur (for example, if the pseudo-fault is to occur 50 μsec after the current time, the unit is "5" if the unit is 10 μsec; hereinafter, this will be referred to as pseudo-fault setting time information). )
and designation of the location where the pseudo failure should occur (for example, the mounting location of a package in which the F/F of a specific error detection latch circuit is mounted and the location of the F/F in the package: hereinafter referred to as error latch address information) ). The specification of the time includes a case where the processor 401 in the service processor unit 400 arbitrarily selects and specifies the time. The designation in this case is, for example, "A".

Next, the process moves to an operation to start an operation for collecting status information of each part at the time specified by the pseudo-failure setting time information. That is, error latch address information is received from the diagnostic control section 4 (step 53) and stored in the memory 402 of the service processor section 400 (step 54). Furthermore, pseudo-failure setting time information (in this case, "5") is received from the diagnostic control unit 4 (step 55), and the process moves to a time monitoring operation. When the simulated fault setting time information is "A", the numerical value selected by the processor 401 becomes the pseudo fault setting time information used for the time monitoring operation. First, it is determined whether or not this pseudo failure setting time information is 0 (step 56), and if it is not 0, after a time of 10 μsec has elapsed (step 57), "1" is subtracted from the pseudo fault setting time information and the result is "4". '' (step 58), then the process moves to step 56 and is repeated thereafter. When the false fault setting time information becomes "0", the diagnostic control unit 4 passes through the Y branch of step 56.
In response to this, the clock of the processing section 100 is stopped and the state information of each section is instructed to be frozen at the simulated fault setting time (step 59). After receiving the freezing completion report from the diagnostic control unit 4 (step 60), the memory 4
The pseudo fault setting flag provided in step 02 is set to "1" (step 61). This flag is displayed as "1" only when a pseudo fault is set and a fault processing test is being performed, and is set to "0" in other cases to clearly indicate that the test is in progress.

Next, an operation is performed to collect status information of each frozen part, and this operation is the same as the operation at the time of an actual failure described above, except for the following operations, and is performed from step 62 to step 76.

Since the pseudo fault setting flag is set to "1" in step 61, the next pseudo fault operation is executed via the Y branch in step 69.

That is, the error latch address information stored in the memory 402 is read out (step 70),
It is checked whether the error latch specified by this information is installed in the package for which scan read has just been performed (step 71). Specifically, a match is made between the package address field in the error latch address information and the package address for scan read. If it is not implemented, the scan read data as it is is sent to the error log area 20 in step 73 from the N branch.
Store in 1. However, if it is implemented, the corresponding bit in the scan read data (specifically, the bit specified in the in-package flip-flop number field in the error latch address information) is replaced with 1 (step 72). ) Later, in step 73, the updated scan read data is stored in the error log area 201.

This means that the F/F of the error latch circuit in the processing unit 100, which is the source of the information to be stored at the address, has been set to logic 1 due to a fault, creating status information equivalent to the fact that it has generated a fault signal. It turns out. In other words, a pseudo failure has occurred at a specified location at a specified time.

In this way, the same information as the actual occurrence of a fault has been stored in the error log area 201, and the fault handling can be checked through steps 78 and 79 in the same way as when an actual fault has occurred.

As described above, in this embodiment, the status information of each part of the processing unit 100 is frozen at a specified time, this status information is stored in the error log area 201, and then the status information of the specified part is frozen at a specified time. This state information is set in the state information, and a confirmation test of fault handling is performed using this state information, and there is no need to prepare an additional circuit for each circuit to add a pseudo fault as in the conventional device.

In this embodiment, only the collection of F/F status information of the error detection latch circuit has been described, but the present invention is not limited thereto. In other words, the present invention can also be applied to the case of collecting all state information of each circuit that is subject to failure processing. Furthermore, in this embodiment, a case has been described in which the pseudo failure is set for the bits of the error log area corresponding to the F/F, but the present invention is not limited to this, and the failure notification is sent to the F/F. This method can also be applied to the case where a pseudo fault is set including the corresponding bits of each circuit that causes the fault to occur, that is, when a plurality of state information is changed.

Effects of the Invention As described above, according to the present invention, status information is collected in the main memory and pseudo-failure information is set therein, so that it is much easier to add pseudo-faults than conventional devices. This makes it possible to reduce the amount of hardware.

[Brief explanation of drawings]

FIG. 1 is a diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are flowcharts showing the operation of the blocks in FIG. 1. Explanation of symbols of main parts, 4...Diagnostic control unit, 1
4, 15, 16...Error detection latch circuit, 10
0... Processing unit, 200... Main memory, 201... Error log area, 300... Memory access control unit, 400... Service processor, 401...
Processor, 402...Memory.

Claims (1)

[Scope of Claims] 1. A plurality of fault storage means for detecting and storing faults in each function of the device, and status information of the device including the contents of the plurality of fault storage means in response to the occurrence of the fault. a writing means for collecting the information and writing it into the main storage means, and a process for initializing the device after completing the writing, analyzing the status information written in the main storage means, and performing predetermined trouble handling. a first starting means for starting the writing means when testing the fault handling function; and a writing operation of the writing means started by the first starting means. and a state information modifying means that modifies at least one pre-specified piece of the collected state information; A data processing device comprising: second activation means for activating the processing means.