JPH0546426A - Self-diagnostic circuit - Google Patents

Abstract

PURPOSE:To improve the reliability and the maintainability of a processor by providing a self-diagnosis part, an abnormality generating part, and a means which inputs the abnormal state to the self-diagnosis part to discriminate the indefectible state of the self-diagnosis part. CONSTITUTION:A self-diagnosis part 4 which detects the abnormal state, an abnormality generating part 6 which artificially generates the abnormal state for the purpose of confirming the indefectible state of the self-diagnosis part 4, and a means which inputs the abnormal state from the abnormality generating part 6 to discriminate the indefectible state of the self-diagnosis part 4 are provided. In this case, the abnormality generating part 6 outputs the artificial abnormal state to the self-diagnosis part 4, and this part 4 takes this abnormal state as the input to discriminate the indefectible state of the self-diagnosis part 5, and the indefectible state of the self-diagnosis part 4 of the processor is confirmed. Thus, the reliability and the maintainability of the processor itself are improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-diagnosis circuit provided in a processor, and more particularly to a self-diagnosis circuit for confirming the soundness of itself.

[0002]

2. Description of the Related Art A processing device employs a self-diagnosis circuit for detecting an abnormality of the device. An example in which the self-diagnosis circuit of this processing device is applied to a conventional plant monitoring device will be described with reference to FIG.

In the figure, the plant monitoring apparatus 1 is provided with a microprocessor 2, a memory 3 for storing a program of the microprocessor 2, and a self-diagnosis unit 4 for diagnosing whether or not there is any abnormality in the plant monitoring apparatus 1.
The input / output means for collecting data from the plant and the like are omitted in the drawing.

Generally, when the plant monitoring apparatus 1 is started up, the process for monitoring the state of the plant is started after performing the processing shown in FIG.

First, the hardware is initialized (101). Then, the microprocessor 2 checks whether the constituent elements of the device operate properly. For this check, for example, it is confirmed whether the read / write operation of the memory 3 is normally performed (102). At this time, if there is an abnormality, the initialization is performed again. When the components of the plant monitoring device 1 are determined to be normal, it is next checked whether the self-diagnosis unit 4 detects an abnormality (10
3).

There are various types of self-diagnosis section 4, for example, the watchdog timer 4 shown in FIG.
In a, a timer is provided inside and the reset signal a is input to the watchdog timer 4a within a certain set time by the processing of the microprocessor 2. The reset signal a resets the timer of the watchdog timer 4a and restarts the timer. However, Figure 1
As shown in 4, if the reset signal a is not input for some reason at the time t1, the watchdog timer detects an error at the time t2 and outputs the watchdog timer error signal b. As a result, not only a hardware failure but also a program mistake can be detected.

In addition to the watchdog timer 4a, there is a self-diagnosis unit 4 that detects a memory parity error, a response timeout, a clock stop and the like.
When these abnormalities occur, failures such as detailed factors and the time of occurrence are logged in a specific area in the memory to facilitate failure analysis.

When the self-diagnosis unit 4 detects an abnormality, the process returns to the first step again and is initialized. A program for the microprocessor 2 for performing the above-mentioned processing is stored in the memory 3, and self-diagnosis of the device is performed even after the operation is started.

[0009]

However, if there is an abnormality in the self-diagnosis section 4 itself, there is a problem that the abnormality in the apparatus cannot be detected correctly. The self-diagnosis unit 4
Since the abnormality is extracted as a detection signal in the device by the processing of the microprocessor 2, the plant monitoring device 1 processes the device as normal when the self-diagnosis unit 4 itself is not healthy. Therefore, when the self-diagnosis unit 4 has an abnormality, the plant monitoring device 1 has a problem that incorrect data is displayed or an error factor is not correctly logged and it takes a lot of time for failure analysis. This has been a factor that reduces the reliability and maintainability of the plant monitoring device 1, that is, the processing device.

Therefore, an object of the present invention is to provide a self-diagnosis circuit which improves the reliability and maintainability of a processing device.

[0011]

SUMMARY OF THE INVENTION The present invention is directed to a self-diagnosis unit for detecting an abnormal state of a processing device, and an abnormality generation unit for simulating the abnormality state to confirm the soundness of the self-diagnosis unit. And means for determining the soundness of the self-diagnosis unit by inputting the abnormal state of the abnormality generation unit to the self-diagnosis unit.

[0012]

With the above configuration, the abnormality generation section outputs a simulated abnormal state to the self-diagnosis section. The self-diagnosis unit inputs this abnormal state and judges the soundness of the self-diagnosis unit.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram in which a self-diagnosis circuit showing an embodiment of the present invention is applied to a plant monitoring device. Figure 1
The difference from 1 is that an anomaly generator 6 is additionally provided as the self-diagnosis circuit 5. The abnormality generation unit 6 simulates an abnormality signal of the device by a command from the microprocessor 2 and inputs it to the self-diagnosis unit 4.

The plant monitoring apparatus 1 having the above configuration is shown in FIG.
In the same manner as described above, at the time of startup, generally, the operation of monitoring the plant is started through the processing procedure shown in FIG.

First, the hardware is initialized (201). Next, the microprocessor 2 determines whether the device configuration operates correctly (202). If the components of the device are judged to be normal, it is checked whether the self-diagnosis unit 4 detects an abnormality (203).

If the self-diagnosis unit 4 does not detect any abnormality, it is checked whether the self-diagnosis unit 4 is sound (204). That is, the abnormality generation unit 6 simulatedly outputs an abnormality signal to the self-diagnosis unit 4 according to a command from the microprocessor 2,
Determines whether to detect an abnormal signal correctly. As a result, when the soundness of the self-diagnosis unit 4 is confirmed, the plant monitoring operation is started (205). At this time, it is checked whether the information regarding the abnormality is correctly logged in the memory 3. It should be noted that if there is an abnormality in a component, if the self-diagnosis unit 4 detects an abnormality, or if the soundness of the self-diagnosis unit 4 cannot be confirmed, the initialization is started again (201).

Here, the above-mentioned self-diagnosis circuit will be specifically described.

First, the self-diagnosis circuit 5 for detecting a watchdog timer error is constructed as shown in FIG. 3, and an AND gate 7 is provided in the abnormality generation unit 6 and a watchdog timer 4a is provided in the self-diagnosis unit 4. ..

The AND gate 7 of the abnormality generator 6 is connected so that the reset signal a and the control signal b are input. The control signal b is set to "1" by a command stored in advance in the program in the memory 3, and the reset signal a is set to "1" at a constant set time in the normal state as shown in FIG. input. In this AND gate 7,
When the reset signal a is input, the AND condition is satisfied, and the gate output signal c is input to the watchdog timer 4a corresponding to the reset signal a at fixed time intervals. The watchdog timer 4a resets the timer accordingly.

However, when the microprocessor 2 sets the control signal b to "0" at the time t1 by a command prestored in the program in the memory 3 during the soundness confirmation, as shown in FIG. Of the gate output signal c of "2" remains "0" at the time t2. As a result, the watchdog timer 4a cannot reset the timer after a certain time, and the countover detects the watchdog timer error signal d at time t3. This watchdog timer error signal d is notified to the microprocessor 2 by means such as an interrupt.

When the present invention is applied to the clock stop detection circuit, it becomes as shown in FIGS.

Both the clock signal a and the control signal b are input to the AND gate 7 of the abnormality generator 6 as "1", and the gate output signal c is "1" corresponding to the clock signal a in the normal state. Is output. The clock stop detection circuit 4b is
Since "1" of the gate output signal c is input, the clock stop is not detected, and the clock abnormality signal d is not output at the time t1.

When confirming the soundness of the clock stop detection circuit 4b, the microprocessor 2 sets the control signal b to "0" by the command of the memory 3 at time t1. As a result, the gate output signal c becomes "0", and the clock stop detection circuit 4b outputs the clock abnormality signal d at time t2.
The clock abnormality signal d is notified to the microprocessor 2.

When the present invention is applied to the response time-out circuit, it becomes as shown in FIGS.

In this embodiment, the activation signal a is input to the response timer 4c of the self-diagnosis unit 4, while the response signal b and the control signal c are input to the AND gate 7 of the abnormality generation unit 6. In the normal state, the response timer 4c checks, for example, whether the response signal b is returned within a certain time T1 at the time t2 after the activation signal a is input at the time t1. Here, if the control signal c is set to "0" at the time t3 at the time of confirming soundness, the gate output signal d becomes "0". Since the gate output signal d remains “0” at the time t4, the response timer 4c counts over, and the response timer 4c counts at t5.
At this point, the response timeout error e is detected and the microprocessor 2 is notified.

When the present invention is applied to the parity check circuit, it becomes as shown in FIG. 9 and FIG.

The parity bit a and the control signal b are input to the AND gate 7 of the abnormality generating section 6, and the AND gate 7
The gate output signal c of is input to the parity check circuit 4d together with the data d. Here, for even parity,
In the normal state, for example, when the data d read from the memory 3 is "0" from the time t1 to the time t2, the parity bit a from the memory 3 is also "0" and the gate output signal c outputs "0". .. Similarly, when the data d read from the memory 3 is "1" from time t2 to time t3, the parity bit a is "1" and the gate output signal c is output. Therefore, the number of "1" input to the parity check circuit 4d is always kept even.

When confirming the soundness, if the control signal b is set to "0" at time t3, the gate output signal c becomes "0" at time t4, and it is not possible to maintain an even number. As a result, the parity check circuit 4d outputs the parity error signal e, and this signal is notified to the microprocessor 2.

In this way, the abnormality generation section 6 outputs a simulated abnormality signal to the self-diagnosis section 4 in response to a command from the microprocessor. The self-diagnosis unit 4 detects the simulated abnormal signal and notifies the microprocessor 2 of it. Therefore, by checking the soundness of the self-diagnosis unit 4 in more detail, the plant monitoring device 1 including the self-diagnosis circuit 5
Can improve reliability and maintainability. In addition, since the failure can be simulated by the instruction of the microprocessor 2, it is possible to automate the test and save labor. In the present embodiment, the example in which the present invention is applied to the plant monitoring device 1 has been described, but it is obvious that the present invention is not limited to this and can be applied to a processing device including a self-diagnosis unit.

[0031]

As described above, according to the present invention, the soundness of the self-diagnosis unit of the processing apparatus can be confirmed, and the reliability and maintainability of the processing apparatus itself can be improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a plant monitoring apparatus including a self-diagnosis circuit according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a process when the device is started up.

FIG. 3 is a configuration diagram showing an example in which a self-diagnosis circuit of the device is applied to a watchdog timer.

FIG. 4 is a time chart showing the operation of FIG. 3 of the same device.

FIG. 5 is a configuration diagram showing an example in which a self-diagnosis circuit of the device is applied to a clock stop detection circuit.

FIG. 6 is a time chart showing the operation of FIG. 5 of the same device.

FIG. 7 is a configuration diagram showing an example in which a self-diagnosis circuit of the device is applied to a response timer.

FIG. 8 is a time chart showing the operation of FIG. 7 of the same device.

FIG. 9 is a configuration diagram showing an example in which a self-diagnosis circuit of the device is applied to a parity check circuit.

FIG. 10 is a flowchart showing an operation of the apparatus shown in FIG.

FIG. 11 is a configuration diagram showing a plant monitoring device including a self-diagnosis unit showing a conventional example.

FIG. 12 is a flowchart showing a process when the device is activated.

FIG. 13 is a configuration diagram showing an example of a self-diagnosis unit of the apparatus.

FIG. 14 is a time chart showing the operation of the apparatus shown in FIG.

[Explanation of symbols]

 1 plant monitoring device 2 microprocessor 3 memory 4 self-diagnosis unit 5 self-diagnosis circuit

Claims (1)

[Claims] 1. A self-diagnosis unit that detects an abnormal state of a processing device, an abnormality generation unit that artificially generates the abnormal state in order to confirm the soundness of the self-diagnosis unit, and the abnormality generation unit described above. A self-diagnosis circuit, comprising means for inputting an abnormal state to the self-diagnosis unit and determining the soundness of the self-diagnosis unit.