JPS5911452A - Test system of parity check circuit - Google Patents

Abstract

PURPOSE:To conduct the test on a parity check circuit, by checking the presence of an error detecting signal from the parity check circuit when a CPU accesses a parity error data stored in advance. CONSTITUTION:The CPU2 accesses a parity error data stored in an address A of a memory 3 and the result is transmitted to the CPU2 via a common bus 4. Then, the parity check circuit 1 performs the parity check on the bus 4. As a result, when the circuit 1 is normal, an interruption signal MI is inputted to a parity check test section 2a of the CPU2. The test section 2a discriminates whether or not the signal MI is inputted to a preset point of time. When the result of test is correct, it is discriminated that the circuit 1 is normal and the CPU2 starts normal processing. Further, if the result of test is nor normal, the CPU2 informs it to the operator by means of alarm or the like.

Description

DETAILED DESCRIPTION OF THE INVENTION 0 Technical Field of the Invention The present invention relates to a test method for a parity check circuit in a data processing device that performs a data harness check.

Background of the Technology In a common bus type data processing device, data sent and received between a processing device (hereinafter referred to as a CPU), an input/output device, and a memory is generally checked. This is done by a parity check circuit connected to the common bus ζ and checking data output from the bus l.

0 Prior Art and Problems As shown in FIG. 1, a parity check circuit 1 is connected to a data bus and a data parity bit line in a common bus (not shown).

A data bus valid signal line provided from the CPU or the like is also input. In other words, during the period when it is notified from this data bus valid signal line that the information on the data bus is valid, the parity check circuit 1 ensures that the data on the data bus and the data on the parity bit line are in a predetermined relationship. However, if the parity check circuit II is defective and a data parity error cannot be detected correctly,
It causes the disorder of Mumu. For example, if error detection is not performed on data read by the CPU from memory, the CPU may run out of control.

Conventionally, this parity check circuit has not been subjected to a self-function test. That is, at the time of manufacturing the device, the parity check circuit was only tested by supplying data onto the bus from an external tester or the like.

0 OBJECTS OF THE INVENTION In order to eliminate the above-mentioned conventional drawbacks, an object of the present invention is to actively test the parity check circuit as a self-test function of data processing equipment, and to provide a system that can be easily executed by the equipment itself. The purpose of the present invention is to provide a test method for a parity check circuit that can be performed.

0 Structure of the Invention In order to achieve the above object, the testing method of the parity check circuit of the present invention is such that parity error data is stored in advance in a data area of a memory, and a processing device accesses and accesses the parity error data. This method is characterized by checking the presence or absence of a parity error detection signal from a parity check circuit for data.

0 Examples of the invention The present invention will be explained in detail below using Examples.

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a flowchart showing the operation of the embodiment device shown in FIG. In Figure 1, 1 is a parity check circuit, 2 is a CP
U, 3 is a memory, and 4 is a common bus.

The CPU 2, memory 3, and parity check circuit 1 are each connected via a common bus 4. The connection buses to the parity check circuit 1 are the data bus shown in FIG.
Contains data parity bit lines and data bus valid signal lines.

The operation of the device according to the embodiment will be explained below based on the flowchart in FIG.
When restarting the system, the CPU 2 initializes each part of the device (
initialize). For example, an internal register of the CPU 2, an input/output device (not shown) connected to the common bus 4
This applies to the initial state settings in the valleys, etc.

The CPU 2 further tests the parity check circuit 1 according to the initial program stored in the memory 31.

The memory 3 is a non-volatile memory (ROM) that stores all the operation start-up programs for the CPU 2, and is an essential node part of the device. Test by running 2a'r.

On the other hand, data that will cause a parity error is stored in advance in a predetermined area of the memory 3 (a certain area starting from address A in the figure). The memory 31 is shown in FIG.
Parity bit information is also stored corresponding to each piece of data. CPU2 reads memory 3 according to the initial program.
Access all parity error data. That is, it outputs address information indicating address A onto the address bus of the common bus 4, and also specifies the read mode for the memory 3. Upon access from the CPU 2, the memory 3 transfers the data stored at address A to the CPU via the data bus of the common bus 4.
Send to U2. As a result, the parity check circuit 1 performs a parity check on the data on the data bus. Incidentally, it can be considered that the data bus valid signal line shown in FIG. 1 is given a signal indicating validity at the same time as the initial operation of the CPU 2.

As a result, since the data at address A is parity error data, if parity check circuit 1 is normal, C
Interrupt signal M indicating parity error occurrence to PU2
it-output. This interrupt signal M1 is input to the parity check test section 2a. Normally, this interrupt signal Mi causes the CPU 2 to perform interrupt processing, but due to the operation of the parity check test section 2a, it is not treated as a regular interrupt signal.

The parity check test section 2a determines whether or not the parity error interrupt signal Mi is input at a preset time. The parity check test section 2a includes a CPU
The memory address at which 2 accesses memory 3 is input. Therefore, from this address I, it is known when the parity check circuitry should detect a parity error.

In this embodiment, a plurality of address areas are provided to store this high IJ error data. That is, parity error data is stored in several addresses within this area. In this way, the parity check circuit engineer can test the parity check circuit more accurately by providing data for which parity errors should be detected in a plurality of locations and on a single occasion. When the test of the parity check circuit 1 based on the data access ζ in the test area is completed and the test result is correct, the CPU 2 starts normal processing.

Further, it goes without saying that if the test result of the parity check circuit 1 is not good, the CPU'2 notifies the operator by means of an alarm or the like.

Effects of the Invention As detailed above, according to the present invention, the function test of the parity check circuit 1 can be performed during the initial operation of the device by the CPU 2, and malfunction of the device due to parity check circuit failure can be completely prevented. - This can be prevented.

[Brief explanation of the drawing]

1 is a diagram explaining the entire operation of the parity check circuit 1, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a flowchart showing the operation of the embodiment. 1 is a parity check circuit, 2 is a CPU, 3 is a memory, and 4 is a common path. Figure Z Figure 5

Claims (1)

[Claims] In a data processing device in which a processing device, a memory, and a parity check circuit are each connected to a common bus, and the parity check circuit performs a parity check on data on a common pan, data with a parity error is stored in a predetermined area of the memory in advance. At the same time, the processing device accesses the parity error data and performs a functional test of the parity check circuit depending on the presence or absence of a parity error detection signal from the parity check circuit for the accessed data. Test method for parity check circuit.