JPH0310347A - Trouble detecting circuit - Google Patents

Abstract

PURPOSE:To quickly confirm a faulty RAM and a faulty data bus bit by providing a diagnostic ROM and a decoder which decodes information to select a RAM which is outputted from the diagnostic ROM. CONSTITUTION:When a CPU 4 apparently reads out a diagnostic memory 1, the output of a RAM selecting part 1C is sent through a decoder 2 to successively select RAMs 6 in the system where trouble occurs, and the address to designate the area where test data should be written, from an address storage part 1A, a test data from storage part 1B, and write condition from read/write data part 1D respectively are outputted to these RAMs 6 to store test data. Thereafter, a buffer 10 goes to the diasable state, and a read condition is outputted from the read/write data part 1D, and the CPU 4 reads out test data written in RAMs 6 and compares it with data of a correct answer value in a CS 5. Thus, a faulty part is quickly detected with each bit of a data line as the unit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a fault detection circuit, and to fault detection in a data transfer path of a 1% volatile memory.

[Conventional technology]

In conventional data transfer hardware, a data parity check section is provided on a data transfer path in order to improve the reliability of data transferred on a bus, data read from memory, and the like.

When a data parity error occurs due to a mismatch between the data stored in the memory and the parity pit, noise generation on the data line, or cutting of a printed circuit board pattern, this causes an interrupt to be sent to the microprogram control device. Reported.

When the data parity error mentioned above occurs, the microinstruction enters a diagnostic routine and becomes stalled, so it is necessary to restart it again or replace the logic card if the cause is a hardware failure. .

[Problem to be solved by the invention]

As mentioned above, in the conventional method, when a data parity error occurs, the microinstruction enters the diagnostic routine and becomes stalled, so it is necessary to restart the microinstruction, but if the data line connected to the RAMK When a data parity error occurs due to a hardware failure, it is not known in which RAM section the failure occurred, so a replacement card must be arranged and reinstalled, and the defective card is returned to the factory. The drawback is that it takes a lot of man-hours to conduct the investigation.

[Means for solving confusing problems]

The fault detection circuit of the present invention writes and reads test data to and from RAM in order to detect a faulty RAM system when a data parity error occurs when several RAMs are accessed in normal operation. It has a diagnostic memory (ROM) in which diagnostic data is stored and a decoder that decodes information for selecting a RAM output from the diagnostic memory (ROM).

〔Example〕

Next, details of embodiments of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 11 is a diagnostic memory (R, OM) that stores test data that is activated when a data parity error occurs, and 2 is for selecting a RAM that has several when a data parity error occurs. decoder, 3
4 is an error indicator that holds the output of the parity checker; 4 is a microprogram controller (CPU);
5 is a control register (CS) in which normally activated microinstructions are stored, 6 is R and AM in which normal data is stored, 7 is a parity checker (PC), 8 is a multiplexer, and 9 is a bidirectional buffer. , 10.11 are buffers, 100 is a chip enable signal for accessing the RAM during normal operation, and 200 is an interrupt signal input from the error indicator to the CPU 4 when a data parity error occurs.

The operation will be explained below.

In normal operation, the CPU 4 accesses microinstructions stored in the C85 and performs various processes.

In this processing operation, R
When AM6 writes to or reads from the
When the PC 7 detects a mismatch between the data and the parity bit due to a failure of the RAM 6 or a pattern cut on the printed circuit board of the data line system of the RAM 6, a data parity error occurs and is stored in the error indicator 3.

The error indicator 3 notifies the CPU 4 via an interrupt signal 200 that a data parity error has occurred.

Having recognized the occurrence of the interrupt, the CPU 4 shifts to a subroutine process for controlling test data for detecting a faulty RAM system existing in the diagnostic memory 1. When entering the subroutine processing for testing the RA λ 46 of the faulty system, the multiplexer 8 selects the output of the diagnostic memory 1, the buffer 10 is switched to the enabled state,
Error indicator 3 becomes disabled.

After that, when the CPU 4 shifts to the control of apparently reading out the diagnostic memory 1, the output of the RAM select section IC is sent out via the decoder 2, and it sequentially selects the RAM 6 of the faulty system, and , from the address storage section IA, there is an address specifying the area where the test data should be loaded, and from the data storage section IB, the test data is read/write. conduct.

After storing the test data, the buffer 10 becomes disabled, and the read condition is output from the read 15 itte data section ID, and the CPU 4 reads out the written test data in the RAM 6, which has been previously stored in the C85. Compare with the correct value data.

In the test data, all bits of the cheetah line are H level and L level.
Since it is composed of a combination of values that form a level, faulty parts can be detected for each bit of the cheater line. After storing the comparison result information in main memory, the microinstruction enters a stall state.

〔Effect of the invention〕

As described above, the present invention is capable of dealing with faulty RAM by adding a simple hardware configuration for performing test data write/read tests when a data fault occurs on the RAM data = 6 bus. Because the failure data bus pit of the RAM can be confirmed, it can be quickly performed at the user's site.
It is effective in dealing with disabilities.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. ■...Diagnostic memory, 2...Decoder, 3.
...Error indicator, 4...Micro program controller fM, 5...;Control register, 6...RAM, 7...Parity checker 18...Multiplexer, 9...
...Bidirectional buffer, 10°11...Buffer, 100...Chip enable pool signal, 200...
...Interrupt signal, one person...address storage section, IB...data storage section, IC...RAM selection section, ID ・
...Read/write data section. 4C Sohachi to C Uchino, Ki7- 281-

Claims (1)

[Claims] When a data parity error occurs when several RAMs are accessed during normal operation, diagnostic data is stored to write and read test data to and from the RAM in order to detect the faulty RAM system. Diagnostic RO
A failure detection circuit comprising: M and a decoder for decoding information for selecting a RAM output from the diagnostic ROM.