JPS60101649A - Diagnosis device of electronic computer - Google Patents

Abstract

PURPOSE:To obtain a simple and inexpensive diagnosis device by producing an indication for a diagnosis action to produce an error by decoding the memory address information of a memory and facilitating the timing control for generation of the error in a diagnosis mode of the memory. CONSTITUTION:A diagnosis mode signal is sent to a diagnosis device 10 from a central processor 1a via a signal line 13. Thus a decoding circuit 11 is set under a decodable state. The diagnosis program instructions are executed successively, and an instruction is executed for, e.g., an address 2010 where an instruction to read out an address 1000 as an execution operand address is stored. As a result, the contents of the address 1000 are read out of a memory 7 and this data is sent to an error producing circuit 8. While the circuit 11 sends a signal to the circuit 8 via an indication line 50 to invert the read-out data by one bit since the memory address information is identical with the address 1000. Thus an inverse signal is sent to an error detecting circuit 9. The circuit 9 performs a parity check of said data and produces an error signal owing to a 1-bit error to inform the generation of the error to the processor 1a.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a diagnostic device for an electronic computer.

[Prior art]

BACKGROUND OF THE INVENTION Central processing units and storage devices of electronic computers are equipped with error detection circuits and circuits that automatically correct errors in order to prevent malfunctions due to failures or the like. Some of these error detection circuits and error correction circuits operate only when an error occurs, and it is not sufficient to simply confirm that the equipment operates without abnormality using information and signals in a normal state without errors. . Therefore, some devices have been designed to allow testing and verification of error generation circuits and error correction circuits by generating errors using a diagnostic device.

FIG. 1 is a block diagram showing an example of this type of device. In this figure, 1 is a central processing unit, 2 is a diagnostic device, and 6 is a storage device for storing programs and data.

The diagnostic device 2 includes a selection circuit 5 that selects the diagnostic device 2 based on input/output control information sent from the central processing device 1 to control the input/output devices, and a data register 4 that stores data transferred from the central processing device 1. and a combinational circuit 5 that combines the contents from the data register 4 to generate various error occurrence signals. The storage device 6 also includes a memory array 7, an error generation circuit 8 that inverts data read from the memory array 7 by one pit, and an error detection circuit 9 using a parity check method.

Next, the operation of this device will be explained. When the diagnostic device 2 is not operating, the error generation circuit 8
The read data is sent to the error detection circuit 9 without inverting one bit, and a parity check is performed. That is, during non-diagnostic operation, the storage device 6 is connected to the memory array 7.
Error detection is performed.

In order to operate the diagnostic device 2, the central processing unit 1 reads and decodes the diagnostic program stored in the storage device B, and sends input/output control information such as the device address of the input/output device to the diagnostic device 2. Diagnostic device 2 by selection circuit 6
is selected. Next, the central processing unit 1 transfers data instructing the diagnostic device 2 to invert the read data of the storage device 6 by 1 bit, and transfers the data to the data register 2.
Set this to . The contents of this data register 4 are decoded by a combinational circuit 5, and a 1-bit inversion instruction is transmitted to the error generation circuit 8 via a 1-bit inversion instruction line 50. In the central processing unit 1, instructions are fetched one after another from the memory device #6, and from the time when the instruction to invert one bit of the read data is transmitted from the diagnostic device 2 to the memory device 6, the data read from the memory array 7 is 1 in the error generation circuit 8.
The bits are inverted and parity checked by the error detection circuit 9, and a parity check error occurs in the read data as the storage device 6. Conventionally, errors were generated in this way. That is, the diagnostic device 2 is assigned as one of the input/output devices, and a signal that causes an error is generated based on input/output commands and transfer data.

In the conventional device configured in this manner, the diagnostic device is assigned as one of the input/output devices, so it is necessary to prohibit the use of the device address of the diagnostic device in general programs other than the diagnostic program. In addition, in the case of diagnosing a storage device, the central processing unit retrieves input/output commands from the storage device, starts up the diagnostic device, sends error indication data, and accesses the storage device. Since the operation timing between the storage device and the storage device is different,
This method has drawbacks such as the difficulty of generating the timing to cause an error or the timing to stop the occurrence of an error.

[Summary of the invention]

The present invention has been made to eliminate these drawbacks of conventional devices, and it eliminates the need to allocate a diagnostic device as one of the input/output devices, and also makes it easy to control the timing that causes errors when diagnosing storage devices. Therefore, the aim is to realize a diagnostic device with a simple and inexpensive configuration.The diagnostic device is configured to include a decoding circuit, and the instruction for the diagnostic operation that causes the error is decoded by the memory address information of the storage device using the decoding circuit. This is so that an error occurs when a storage area that matches the memory address information is accessed.

[Embodiments of the invention]

FIG. 2 is a block diagram showing an example of a device according to the present invention. In the figure, 1a is a central processing unit, 6 is a storage device, and is composed of a memory array 7, an error generation circuit 8 that inverts read data by 1 bit, and an error detection circuit 9 using a parity check method. 10 is a diagnostic device;
It is configured to include a decoding circuit 11. This decoding circuit 11 is connected to a diagnostic mode line 13 from the central processing unit @1a.
It inputs the diagnostic mode signal sent out via the memory address information line 12, decodes the memory address information sent out via the memory address information line 12, and outputs the decoding result to the instruction line 50 as an error instruction signal.

The operation of the device configured in this way will be explained next.

A diagnostic program is stored in the storage device #B, and the central processing unit \t1a retrieves and executes the instructions of this diagnostic program. Then, a diagnostic mode signal is sent from the central processing unit 1a to the diagnostic device 10 via the signal line 13 as a signal indicating that a diagnostic operation is to be performed by a command or switch operation exclusively for C1 diagnosis. In the diagnostic device 10, the decoding circuit 11 enters a decodable state upon receiving this diagnostic mode signal. Here, if memory address information indicating, for example, address 1000 is output via the memory address information line 12, the decoding circuit 11 instructs the error generation circuit 8 to invert one bit via the instruction line 50. It is assumed that the It is also assumed that the instructions of the diagnostic program are stored at addresses higher than address 2000, and that an instruction to read address 1000 as an execution operand address is stored at address 2010@, which is 11.

Now, the instructions of the diagnostic program are being executed one after another, the decoding circuit 11 is in a decoding enabled state by the diagnostic mode signal, and when the instruction at address 2010 is executed, 1o
The contents of address oo are read from memory array 7 and this data is sent to error generation circuit 8. On the other hand, the diagnostic device 10
In the decoding circuit 11, the memory address information is 100.
Since the address is 0, a signal is sent to the error generation circuit 8 via the instruction line 50 to invert the read data by 1 bit. In response to this signal, the error generation circuit 8 inverts the data by one bit and sends it to the error detection circuit 9. The error detection circuit 9 performs a parity check on this data, generates a parity check error signal because one bit is erroneous, and notifies the central processing unit 1a of this.

In the above embodiment, only memory address information is used as the decoding condition of the decoding circuit 11, but a combination of memory address information and data written to or read from the storage device may be used.

Furthermore, the decoding circuit 11 may be constructed of a read-only memory IJ (ROM) or the like as long as it has a decoding function. Further, in the above description, a 1-bit error in read data in a storage device has been described, but the error may be in a central processing unit.

〔Effect of the invention〕

As explained above, the present invention is configured to generate an instruction for a diagnostic operation that causes an error by decoding memory address information of a storage device, and there is no need to allocate a diagnostic device as one of the input/output devices. Furthermore, in the case of diagnosing a storage device, timing control for generating errors becomes easy, and a diagnostic device with a simple configuration and low cost can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional device, and FIG. 2 is a block diagram showing an example of a device according to the present invention. DESCRIPTION OF SYMBOLS 1...Central processing unit, 6...Storage device, 7...Memory array, 8...Error generation circuit, 9...Error detection circuit, 10...Diagnostic device, 11...Decoding circuit. Note that the same reference numerals in each figure indicate the same or equivalent parts. Agent Patent Attorney Sanro Kimura

Claims (1)

[Claims] III. A central processing unit, a storage device including a memory array, an error generation circuit that inverts data read from the memory array by one bit, and an error detection circuit that inputs data from the error generation circuit, and diagnosis from the central processing unit. a decoding circuit that inputs a signal indicating an operation and memory address information to be output to the memory array, decodes the memory address information, and outputs a sliding signal that causes an error to the error generation circuit; A diagnostic device for an electronic computer that includes a diagnostic device.