JPS63110944U - - Google Patents
Info
- Publication number
- JPS63110944U JPS63110944U JP115187U JP115187U JPS63110944U JP S63110944 U JPS63110944 U JP S63110944U JP 115187 U JP115187 U JP 115187U JP 115187 U JP115187 U JP 115187U JP S63110944 U JPS63110944 U JP S63110944U
- Authority
- JP
- Japan
- Prior art keywords
- cpu
- handshake
- signal
- monitoring electronic
- electronic circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012544 monitoring process Methods 0.000 claims description 3
- 230000005856 abnormality Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図は本考案の実施例に係るウオツチドツグ
回路のブロツク図、第２図は従来のウオツチドツ
グ回路のブロツク図である。
１…制御用ＣＰＵ、２…監視用外部電子回路、
３…アラーム回路。
FIG. 1 is a block diagram of a watchdog circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional watchdog circuit. 1... Control CPU, 2... Monitoring external electronic circuit,
3...Alarm circuit.
Claims (1)
るウオツチドツグ回路であつて、 前記ＣＰＵと前記監視用電子回路との間で信号
をハンドシエイクする構成とし、当該ハンドシエ
イクされる信号に基づいて両者が相互に異常検出
を行う様にしたことを特徴とするウオツチドツグ
回路。[Claims for Utility Model Registration] A watchdog circuit equipped with a monitoring electronic circuit for detecting runaway of a CPU, which is configured to handshake a signal between the CPU and the monitoring electronic circuit, and the handshake signal A watchdog circuit characterized in that both sides mutually detect abnormalities based on the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP115187U JPS63110944U (en) | 1987-01-08 | 1987-01-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP115187U JPS63110944U (en) | 1987-01-08 | 1987-01-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63110944U true JPS63110944U (en) | 1988-07-16 |
Family
ID=30778787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP115187U Pending JPS63110944U (en) | 1987-01-08 | 1987-01-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63110944U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5911452A (en) * | 1982-07-13 | 1984-01-21 | Fujitsu Ltd | Test system of parity check circuit |
| JPS60101649A (en) * | 1983-11-07 | 1985-06-05 | Mitsubishi Electric Corp | Diagnosis device of electronic computer |
-
1987
- 1987-01-08 JP JP115187U patent/JPS63110944U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5911452A (en) * | 1982-07-13 | 1984-01-21 | Fujitsu Ltd | Test system of parity check circuit |
| JPS60101649A (en) * | 1983-11-07 | 1985-06-05 | Mitsubishi Electric Corp | Diagnosis device of electronic computer |
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