JPS5931800B2 - Control memory diagnostic method - Google Patents
Control memory diagnostic methodInfo
- Publication number
- JPS5931800B2 JPS5931800B2 JP53098866A JP9886678A JPS5931800B2 JP S5931800 B2 JPS5931800 B2 JP S5931800B2 JP 53098866 A JP53098866 A JP 53098866A JP 9886678 A JP9886678 A JP 9886678A JP S5931800 B2 JPS5931800 B2 JP S5931800B2
- Authority
- JP
- Japan
- Prior art keywords
- control memory
- diagnosis
- data processing
- processing device
- parity check
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Description
【発明の詳細な説明】
本発明は２重化構成をとるデータ処理装置の割判メモリ
診断方式に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a split memory diagnostic method for a data processing device having a duplex configuration.
従来、制御メモリの診断方式として動作中の装置から停
止中の装置に対して１マイクロステップ実行指示を行な
い、１マイクロステップ実行と共にその時読み出された
制御メモリ情報を他装置から読み出す方式があつた。Conventionally, as a method for diagnosing control memory, there was a method in which an operating device instructs a stopped device to execute one microstep, and when the one microstep is executed, the control memory information read at that time is read out from another device. .
しかし、この方式では次の３つの欠点があつた。However, this method had the following three drawbacks.
第１にエラーを検出した時点において、誤つた制゛御メ
モリの内容で装置を制御してしまい場合によつてはオン
ラインで動作中の装置にまで影響が及びオンラインの処
理に悪影響を及ぼす事があつた。第２の欠点としては診
断時は診断に必要な最少の回路を動作させる事が好まし
く、制御メモリ診断時に制御メモリを読み出したために
制御メモリ及びその周辺回路以外の回路まで動作し、そ
の状態を変えてしまうことである。第３の欠点としては
、他装置から制御メモリの内容を読み出すために多くの
ハードウェアを必要とすることである。First, when an error is detected, the device may be controlled using the incorrect contents of the control memory, and in some cases, the device may be affected while it is operating online, and online processing may be adversely affected. It was hot. The second drawback is that during diagnosis, it is preferable to operate the minimum number of circuits necessary for diagnosis, and because the control memory is read during control memory diagnosis, circuits other than the control memory and its peripheral circuits may operate and change their state. It's something that happens. A third drawback is that it requires a lot of hardware to read the contents of the control memory from other devices.
本発明は診断時の制御メモリ読出しにおいて、読み出し
た制御メモリの出力を無効にする手段を設けることによ
り上記欠点を解決し、診断時に被診断装置が読み出され
た制御メモリの内容によつて誤動作及び診断上に必要以
上な動作をしない診断方式を提供するものである。The present invention solves the above-mentioned drawbacks by providing a means for disabling the output of the read control memory when reading the control memory at the time of diagnosis. The present invention also provides a diagnostic method that does not perform operations more than necessary for diagnosis.
動作中の装置から停止中の装置を診断する場合動作中の
装置は停止中の装置に対し、読み出された制御メモリ出
力を無効とする診断モードを設定し、次に診断すべき制
御メモリのアドレスを送出する。When diagnosing a stopped device from an operating device, the operating device sets a diagnostic mode for the stopped device that disables the read control memory output, and then sets the diagnostic mode for the stopped device to disable the read control memory output. Send address.
被診断装置は受信したアドレスに従つて制御メモリを読
み出しパリテイチエツクを行なう。ここで従来までは制
御メモリ出力は有効で読み出された制御メモリにより実
際に装置を制御してしまう。その結果制御メモリに異常
があつた場合、その動作は保障されず診断装置にまで悪
影響を及ぼすことがある。本発明によれば制御メモリ出
力は無効であるため装置の内部状態（制御メモリ以外）
を乱すことなくパリテイチエツクを行ない、ついで診断
装置からパリテイチエツク結果を読み出すことで容易に
しかも他への影響なしに制御メモリ診断を可能としたも
のである。The device to be diagnosed reads the control memory according to the received address and performs a parity check. Here, conventionally, the control memory output is valid and the device is actually controlled by the read control memory. As a result, if an abnormality occurs in the control memory, its operation is not guaranteed and the diagnostic device may be adversely affected. According to the present invention, since the control memory output is invalid, the internal state of the device (other than the control memory)
By performing a parity check without disturbing the memory and then reading out the parity check result from the diagnostic device, control memory diagnosis can be easily performed without affecting others.
ここで制御メモリの異常検出の手段としてパリテイチエ
ツクを採用しているが、制御メモリ及びそのパリテイチ
エツク回路は同一パツケージ内に実装することが多く、
さらに２ビツト以上の障害はほとんどまれである事から
、パリテイチエツクで十分な効果が得られる。次に本発
明の実施例について、図面を参照して説明する。Here, a parity check is adopted as a means of detecting abnormalities in the control memory, but the control memory and its parity check circuit are often mounted in the same package.
Furthermore, since failures of 2 bits or more are rare, a parity check can be sufficiently effective. Next, embodiments of the present invention will be described with reference to the drawings.
図は本発明の一実施例を示すプロツク図である。The figure is a block diagram showing one embodiment of the present invention.
動作中の診断装置１から停止中の被診断装置２に対して
診断を行なう場合、アンドゲート５を介し診断モードフ
リツプフロツプ１２のＱ出力を゛１゛にセツトする。次
にアンドゲート４を介し、診断すべき制御メモリのアド
レスを送出する。被診断装置２では受信した該アドレス
を制御メモリアドレスレジスタ（ＣＭＡＲ）７に設定す
る。その結果制御メモリ（ＣＭ）８から読み出された制
御メモリ情報は制御メモリラツチレジスタ（ＣＭＩＲ）
９にセツトされる。ここで１３，１４は制御メモリデコ
ーダ、１５はマイクロ命令タイプ指定用デコーダである
が、前記したようにフリツプフロツプ１２はＱ−゛１゛
となつているためＱ−゛０゛でマイクロ命令タイプ指定
用デコーダは禁止され出力は全でＯ゛となる。従つて制
御メモリデコーダ１３，１４は禁止され出力は全で０゛
となり装置内の制御は何も行なわない。ここでパリテイ
チエツク回路（ＰＣ）１１により制御メモリのパリテイ
チエツクを行なう。診断装置１ではアンドゲート３によ
りパリテイチエツク結果を読みとることで制御メモリ１
ワードの診断が完了する。同様にアドレスを変えて必要
な制御メモリのワード数だけ診断を行なう。最後にアン
ドゲート６によりフリツプフロツプ１２をりセツトし、
１３，１４，１５のデコーダを有効とする。以上のよう
に本発明によれば、被診断装置は診断装置からの指示に
より装置内及び装置外に影響を与えることなく容易に制
御メモリの診断を可能とするものである。When diagnosing the stopped device 2 from the operating diagnostic device 1, the Q output of the diagnostic mode flip-flop 12 is set to ``1'' via the AND gate 5. Next, the address of the control memory to be diagnosed is sent out via the AND gate 4. The device to be diagnosed 2 sets the received address in the control memory address register (CMAR) 7. As a result, the control memory information read from the control memory (CM) 8 is stored in the control memory latch register (CMIR).
It is set to 9. Here, 13 and 14 are control memory decoders, and 15 is a decoder for specifying the microinstruction type.As mentioned above, since the flip-flop 12 is Q-1, Q-00 is used for specifying the microinstruction type. The decoder is inhibited and the output becomes O゛ in total. Therefore, the control memory decoders 13 and 14 are inhibited, and the outputs are all 0', and no control is performed within the device. Here, the parity check circuit (PC) 11 performs a parity check on the control memory. In the diagnostic device 1, the control memory 1 is read by reading the parity check result using the AND gate 3.
Word diagnostics complete. Diagnosis is performed in the same way by changing the address and as many words as necessary in the control memory. Finally, flip-flop 12 is reset by AND gate 6,
Enable decoders 13, 14, and 15. As described above, according to the present invention, the device to be diagnosed can easily diagnose the control memory according to instructions from the diagnostic device without affecting the inside or outside of the device.
本発明は以上説明したように、診断時に制御メモリの出
力を無効にするように構成することにより、誤つた制御
メモリ内容で動作し他装置へ悪影響を及ぼす事がなく、
さらに制御メモリとその周辺回路以外の回路の状態を変
えることなく診断を可能とする効果がある。As explained above, the present invention is configured to disable the output of the control memory at the time of diagnosis, so that it does not operate with incorrect control memory contents and adversely affect other devices.
Furthermore, there is an effect that diagnosis can be performed without changing the state of circuits other than the control memory and its peripheral circuits.
図は本発明の一実施例を部分的にプロツク図で示した回
路図である。
１・・・・・・診断装置、２・・・・・・被診断装置、
３〜６・・・・・・アンドゲート、７・・・・・・制御
メモリアドレスレジスタ、８・・・・・・制御メモリ、
９・・・・・・制御メモリラツチレジスタ、１０・・・
・・・＋１アダー回路、１１・・・・・・パリテイチエ
ツク回路、１２・・・・・・フリツプフロツプ、１３〜
１５・・・・・・デコーダ。The figure is a circuit diagram showing a partial block diagram of an embodiment of the present invention. 1...Diagnosis device, 2...Diagnosed device,
3 to 6...AND gate, 7...Control memory address register, 8...Control memory,
9... Control memory latch register, 10...
... +1 adder circuit, 11 ... parity check circuit, 12 ... flip-flop, 13 -
15...Decoder.
Claims (1)
装置複数台により構成されるシステムにおいて、該シス
テムで動作中のデータ処理装置から該システムで動作を
中断している非動作中のデータ処理装置に対して制御メ
モリの診断を指示する第１の手段と、該第１の手段によ
り診断を指示されたデータ処理装置において、該指示に
より制御メモリの読み出し出力を無効にする第２の手段
と、前記第１の手段により診断を指示されたデータ処理
装置において制御メモリのバリテイチェックを行なう第
３の手段と、前記第１の手段により診断を指示したデー
タ処理装置において、前記第３の手段によるバリテイチ
ェック結果を読みとる第４の手段とを有することを特徴
とする制御メモリ診断方式。1. In a system consisting of multiple data processing devices controlled by a microprogram, from a data processing device in operation in the system to a non-operation data processing device in the system whose operation is suspended. a first means for instructing diagnosis of the control memory; a second means for disabling read output of the control memory in accordance with the instruction in a data processing apparatus instructed to perform diagnosis by the first means; a third means for performing a validity check of the control memory in the data processing device for which the diagnosis was instructed by the means; and a third means for performing a validity check by the third means in the data processing device for which the diagnosis was instructed by the first means. and fourth means for reading the results.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53098866A JPS5931800B2 (en) | 1978-08-14 | 1978-08-14 | Control memory diagnostic method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53098866A JPS5931800B2 (en) | 1978-08-14 | 1978-08-14 | Control memory diagnostic method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5525868A JPS5525868A (en) | 1980-02-23 |
| JPS5931800B2 true JPS5931800B2 (en) | 1984-08-04 |
Family
ID=14231109
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP53098866A Expired JPS5931800B2 (en) | 1978-08-14 | 1978-08-14 | Control memory diagnostic method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5931800B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57133597A (en) * | 1981-02-10 | 1982-08-18 | Nec Corp | Information processing device |
| JPH0797341B2 (en) * | 1986-05-20 | 1995-10-18 | 株式会社ピーエフユー | System logging control method |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3831148A (en) * | 1973-01-02 | 1974-08-20 | Honeywell Inf Systems | Nonexecute test apparatus |
| JPS51138136A (en) * | 1975-05-26 | 1976-11-29 | Nec Corp | Main memory access controller |
| JPS5283033A (en) * | 1975-12-29 | 1977-07-11 | Fujitsu Ltd | Memory diagnostic system |
| JPS5283044A (en) * | 1975-12-29 | 1977-07-11 | Honeywell Inf Systems | Device and method of checking control memory |
| JPS5356933A (en) * | 1976-11-02 | 1978-05-23 | Sharp Corp | Memory unit provided with self-diagnostic function |
| JPS5376637A (en) * | 1976-12-17 | 1978-07-07 | Nec Corp | Diagnostic system of memory device only for reading |
| JPS5426630A (en) * | 1977-07-29 | 1979-02-28 | Omron Tateisi Electronics Co | Inspection system of rom |
| JPS5426631A (en) * | 1977-07-29 | 1979-02-28 | Omron Tateisi Electronics Co | Inspection system of rom |
-
1978
- 1978-08-14 JP JP53098866A patent/JPS5931800B2/en not_active Expired
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3831148A (en) * | 1973-01-02 | 1974-08-20 | Honeywell Inf Systems | Nonexecute test apparatus |
| JPS51138136A (en) * | 1975-05-26 | 1976-11-29 | Nec Corp | Main memory access controller |
| JPS5283033A (en) * | 1975-12-29 | 1977-07-11 | Fujitsu Ltd | Memory diagnostic system |
| JPS5283044A (en) * | 1975-12-29 | 1977-07-11 | Honeywell Inf Systems | Device and method of checking control memory |
| JPS5356933A (en) * | 1976-11-02 | 1978-05-23 | Sharp Corp | Memory unit provided with self-diagnostic function |
| JPS5376637A (en) * | 1976-12-17 | 1978-07-07 | Nec Corp | Diagnostic system of memory device only for reading |
| JPS5426630A (en) * | 1977-07-29 | 1979-02-28 | Omron Tateisi Electronics Co | Inspection system of rom |
| JPS5426631A (en) * | 1977-07-29 | 1979-02-28 | Omron Tateisi Electronics Co | Inspection system of rom |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5525868A (en) | 1980-02-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS5931800B2 (en) | Control memory diagnostic method | |
| JPS60101649A (en) | Diagnosis device of electronic computer | |
| JPH0474254A (en) | Microprocessor diagnostic system | |
| JPS6158051A (en) | False trouble generating system | |
| JP2760027B2 (en) | I / O device | |
| JPS5936859A (en) | Information processing device | |
| JPH039438A (en) | Diagnostic circuit | |
| JPS60251438A (en) | Self-diagnosis method of control memory | |
| JPS63305433A (en) | Diagnosis system for control device | |
| JPS63174141A (en) | Diagnosing system for test of information processor | |
| JPS58121459A (en) | Service processor of electronic computer | |
| JPH05189332A (en) | Information processor | |
| JPH0535455B2 (en) | ||
| JPH05289946A (en) | Memory control system | |
| JPH08297592A (en) | Controller | |
| JPS6381531A (en) | Microprogram control system | |
| JPS6131901B2 (en) | ||
| JPH0214331A (en) | Duplex system diagnosing system | |
| JPS628829B2 (en) | ||
| JPH03184133A (en) | Pseudo fault generating mechanism for data processor | |
| JPS6326416B2 (en) | ||
| JPS6115458B2 (en) | ||
| JPS6211743B2 (en) | ||
| JPS6341098B2 (en) | ||
| JPH04332997A (en) | Troubleshooting system |