JPS6381531A - Microprogram control system - Google Patents

Abstract

PURPOSE:To improve the reliability of system remarkably by using the hardware so as to read and correct a microprogram stored in a main storage device at a fault of a control storage automatically. CONSTITUTION:If an error exists in the control storage 2, a detection circuit 4 detects the error, a parity error flip-flop 4-1 is set and the suppression of instruction execution is requested to a microinstruction control section 10 through a signal line 4-2. After the data on a data bus 1-c are stored once in a read data register 13, the data are outputted to an internal bus 15 through a data line 13-1 according to the instruction of a microinstruction control section 10 and written in the control storage 2 via a data line 15-1. Simultaneously, the correct value of microinstruction is rewritten in a 3rd register 3 through a data line 15-2, the parity error flip-flop 4-1 is reset and the microinstruction control section 10 brings a microinstruction execution suppression signal 10-2 to '0' to restart the execution of the microinstruction.

Description

Detailed Description of the Invention Technical Field The present invention relates to a microprogram control system, and in particular to a microprogram control method in which a microprogram is transferred from a main memory to a control memory and is controlled by a microprogram stored in the control memory. Regarding the method.

PRIOR ART In such a microprogram control system, conventional methods for detecting failures in the control storage unit that stores microprograms include a method of adding a parity bit to perform a parity check, and a method of adding an FCC bit (error correction code) to detect errors. There is a method for performing detection and correction.

Although the method of adding a parity bit requires little investment in hardware, there is a high possibility that the processor or system will go down because there is no recovery means when a parity error is detected.

In addition, the method of adding an error correction code requires a data correction circuit, so the investment in hardware is larger than the former method, and moreover, it requires more than 2 bits.

The disadvantage of the above failure is that it is unrecoverable.

OBJECT OF THE INVENTION Therefore, the present invention has been made to eliminate the drawbacks of the conventional system, and its purpose is to enable failure detection and recovery of the control storage unit with a small amount of hardware, and to improve the system. The purpose is to provide a microprogram control method that eliminates downtime.

According to the present invention, a microprogram consisting of microinstruction words to which parity bits are respectively added is transferred from a main memory to a control memory, and a microprogram controlled by the microprogram stored in this control memory is transferred. a program control system, the first controller storing an address in the control memory of a microinstruction word read from the control memory;
a second register that holds the storage start address of the microprogram in the main memory, a third register that stores the microinstruction word read from the control storage; a check circuit that performs a parity check of the instruction word and an adder that adds the contents of the first and second registers, and inhibits execution of the microinstruction when an error is detected by the check circuit; Data was read from the main memory using the addition output of the adder as an address, the read data was written to the address indicated by the first register in the control memory, and this data was stored in the third register. A microprogram control method is obtained which is characterized in that execution of microinstructions is resumed later.

Example Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, 1 is the main memory, 2 is the control memory, 6 is the first register (MAR) that stores the address in the control memory of the microinstruction being executed, and 5 is the storage start address for storing the microphone program in the main memory. The second register (BADR
), 3 is a third register (MiR) that stores the microinstruction being executed, 10 is a control unit that controls the execution of the microinstruction, 8 is a selection circuit that selects the read address of the control memory, and 4 is the control memory. A check circuit 4-1 detects a parity error in read data, and 4-1 is a flip-flop that stores the check result of this check circuit.

7 is an adder that adds the contents of the second register 5 and the first register 6 to obtain a read address of the main memory 1; 11 is a memory address register (MADR) that stores the address of the main memory 1; and 9 is an adder This is a memory access control circuit that controls access to the main memory 1. Further, 12 is a memory command register (CMR), 13 is a memory read data register (RDR), and 14 is a memory write data register (WDR).

The configuration inside the main memory 1 is shown in FIG. The main memory 1 consists of one word of 8 bytes, and has a pointer at address 100 indicating the start address where the microprogram is stored, and in this example, the microprogram is stored at address 3000000.

Loading of the microprogram from an external memory (not shown) to the main memory 1 is performed by small-capacity reading and a microprogram in the dedicated memory (ROM), and loading from the main memory 1 to the control memory 2 is performed by external diagnostics. This is done under the control of a processor (not shown).

Figure 3 shows the configuration of the microprogram. One word in main memory 1 corresponds to one microinstruction. Bits O~61 are instructions, bits 62 and 63 are parity bits, and bits O~31 and 32~6 of the instruction, respectively.
Odd parity for 1.

Next, microinstruction execution control will be described.

Returning to FIG. 1, when the loading of the microprogram from the main memory 1 to the control memory 2 is completed, the clock stops with the address selection circuit 8 pointing to address O. The diagnostic processor reads the contents of address 100 of the main memory 1 and sets the start address of the microprogram on the main memory, in this example [3000J], in the second register 5, which is one of the features of the present invention. The diagnostic processor then starts the controller clock. When the clock is supplied, the first register 6 is set to 0'', and the third register 3 is set to the contents of the control memory 2 at address O.The contents of the third register 3 are set to microinstruction control. At the same time, the address selection circuit 8 instructs the address selection circuit 8 to select a branch destination microinstruction address.Hereafter, the address selected by the address selection circuit 8 is read out from the control memory 2. are executed sequentially.

Next, a recovery method when a failure occurs in the control memory, which is a feature of the present invention, will be explained.

If there is a failure in the control memory 2, the detection circuit 4 detects the failure, sets the parity error flip-flop 4-1, and requests the microinstruction control unit 10 to suppress instruction execution via the signal line 4-2. .

The microinstruction control unit 10 suppresses the execution of microinstructions by setting the microinstruction execution inhibition signal line 10-2 to ``1'', and also sends a main signal to the memory access control circuit 9 via the memory access request line 10-3. Requests reading of storage device 1. A second register 5 that stores the microprogram storage start address in the next main memory 1 and a first register 6 that stores the control memory address that caused the failure.
The contents of (address 101 in this example) are added by the adder 7, and the result is loaded into the memory address register 11 and used as the main memory address. However, data obtained by shifting the contents of the first register 6 to the left by 3 bits is added.

The memory access control circuit 9 sets a memory read command in the memory command register 12 in response to a request from the microinstruction control section, and sets the memory request signal line 9-1 to "1". An acceptance permission signal is sent from the main memory device 1 via the memory accept signal line 9-2, and after a certain period of time, the read data (3808808 address memory 1 is outputted from the memory 1 of the control memory 2) on the data bus me b.
This is normal data at address 01.

Data on data bus 1-c is read data register 13
After being stored in the memory, the data is output to the internal bus 15 through the data line 13-1 according to an instruction (not shown) from the microinstruction control unit 10, and further written into the control memory 2 through the data line 15-1. At this time, the contents of the first register 6 are selected by the address selection circuit 8 as the address of the control memory 2 .

Simultaneously with writing to the control memory 1, the third register 3 is also rewritten to the correct value of the microinstruction via the data line 15-2, and the parity error flip-flop 4-1 is reset. When the flip-flop 4-1 is reset, the microinstruction control unit 10 outputs the microinstruction execution inhibition signal 10-
Execution of the microinstruction is restarted by setting 2 to "0".

As is clear from the above explanation, it is possible to detect a fault in the control memory simply by adding a small number of parity hits to the control memory, and it is possible to perform fault recovery without giving II to firmware and software. FIG. 4 is a diagram expressing the above explanation using a time chart.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, when a failure occurs in the control memory, the microprogram stored in the main memory is automatically read and corrected by hardware, thereby preventing system downtime even in the event of a failure in multiple bits. It is possible to provide a micro-programmed control device that does not lead to high performance, thereby significantly increasing the reliability of the system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing the contents of the main memory, FIG. 3 is a format diagram showing the configuration of a microprogram, and FIG. 4 is a diagram showing the operation of the blocks in FIG. 1. This is a time chart 1-. Explanation of symbols of main parts 1... Main memory 2... Control memory 3... Third register 4... Parity check circuit 5... ...Second register 6...First register 7...Adder

Claims (1)

[Claims] A microprogram control method in which a microprogram consisting of microinstruction words to which parity bits are respectively added is transferred from a main memory to a control memory and controlled by the microprogram stored in the control memory,
a first register that stores an address in the control storage of a microinstruction word read from the control storage; a second register that holds a storage start address of the microprogram in the main storage; a third register for storing the microinstruction word read from the storage section; a check circuit for performing a parity check on the read microinstruction word; and an adder for adding the contents of the first and second registers. is provided, and when an error is detected by the check circuit, execution of the microinstruction is inhibited, data is read from the main memory section using the addition output of the adder as an address, and this read data is stored in the control memory section. A microprogram control system characterized in that execution of the microinstruction is resumed after writing to the address indicated by the first register and storing this data in the third register.