JPH01166144A - Debugging system for firmware program - Google Patents

Abstract

PURPOSE:To realize a firmware program debug function with little hardware by using an ECC memory as a trace memory and providing a counter as a trace code generating means. CONSTITUTION:First, the address of an instruction step to start the debug of the firmware program is designated and a trace code is written into an ECC memory 2. At the time of executing the above-mentioned program, the trace code is read out. A trace control circuit 3 resets a counter and makes it start a count action when it detects the trace code and makes it stop it when it reaches a prescribed value. The counter 6 counts +1 and generates the trace code of a sequence number to change in a rising sequence each time a program memory 1 is accessed. The trace code generated by the counter 6 is written into the address of the ECC memory 2 accessed at that time.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a debugging method for a firmware program built into a device.

The purpose is to provide a debugging mechanism within the device that allows tracing of firmware programs with a slight increase in the amount of hardware.

a trace control circuit coupled to the ECC memory and configured to control the collection of trace information indicating the order of execution of instruction steps of the firmware program;

and a counter that generates a trace code that identifies the execution order of instruction steps of the firmware program, and sets a trace code indicating the start of tracing at an address at which tracing of the ECC memory should be started from the outside;
Trace control circuit.

When the trace code indicating the start of the trace is detected from the ECC memory, a counter is started to generate a trace code with a sequence number that is sequentially updated each time the program memory is accessed, and It has a configuration that writes to the ECC memory using the address of the program memory.

[Industrial application field]

The present invention relates to a method for debugging a firmware program built into a device.

With the advancement of LSI technology, when realizing various target devices, gate array LSIs are used exclusively for that device to realize an optimal processor, and firmware programs are built in to perform the desired control. The number of people who have done this is increasing.

There are currently various processor analyzers on the market. However, none of these methods is suitable for use in debugging firmware programs built into specialized processors such as those described above. Therefore, it is necessary to implement some kind of debugging mechanism in advance within the device itself.

The present invention provides one method of such a firmware program debugging mechanism.

[Conventional technology]

FIG. 4 is a block diagram of a conventional device containing a firmware program.

In the figure, 11 is a program memory that stores a firmware program, and 12 has the same address structure as the program memory 11;
ECC generated for the instruction at the corresponding address of 1
ECC memory in which data is stored; 13 is a program memory;
An ECC circuit performs error checking and error correction based on instructions read from the memory 11 and ECC data read from the ECC memory 12, and 14 is a processor that executes instructions whose validity is guaranteed by the ECC circuit 13. It is.

The conditions shown in the following items (1), (2), and (2) are indispensable as conditions required for a debugging mechanism for a firmware program built into such a device.

■ The amount of hardware required for the entire device is negligible.

■ Debugging firmware programs.

It is often necessary to preserve timing relationships,
It is desirable that the debugging mechanism has no effect on the running steps of the firmware program.

■ Functionally, various things can be considered, but at least
It is necessary to be able to trace the running step order of the firmware program.

As conventional techniques to meet such demands, the following five types are often used.

(1) Branch trace
ce) Sequentially store addresses where branch statements of the firmware program occur in the trace memory.

(2) Break point
t) Stop running the firmware program at the address of the firmware program step by some means.

(3) Address comparison
Suspension due to e).

By preparing a comparison circuit implemented in hardware and a storage memory for the comparison address for the memory address where the trace firmware program is stored, running can be stopped or stopped when the storage memory address is accessed. Or run a trace.

(4) Create a certain number of trace execution routines in advance in the program steps.

In this way, the running order is recorded by embedding the function of recording the running steps of the program itself into the program itself.

[Problem that the invention seeks to solve]

In 10 to 4) of the prior art described above, (1)
inevitably generates unnecessary traces.

(2) has the problem that the firmware program stops running. In addition, in (3), there is an increase in the amount of hardware, and due to the limitation of the amount of hardware,
The number of specified address points is usually limited to about 1 or 2, and (4) requires processing for tracing, which is an invalid step for the program itself.
There was a problem that only the points set at the time of program creation could be traced. In both cases, trace memory was also required.

The present invention provides a debugging mechanism that enables tracing of firmware programs with a slight increase in the amount of hardware.
The purpose is to install it inside the device.

[Means for solving problems]

In the processor of a conventional device, a firmware program is stored in a memory with an ECC that can detect and correct errors in order to prevent errors. A RAM is generally used as this memory in order to increase the speed.

The present invention is characterized in that the ECC data used to prevent errors in the firmware program is actually unnecessary during debugging, and that the ECC data used to prevent errors in the firmware program is
Focusing on the fact that the corresponding address areas of the C memory are read out simultaneously in synchronization, the memory area where the ECC is stored is used as a trace area for the firmware program during debugging.

FIG. 1 shows the basic configuration of the present invention.

In fig.

1 is a program memory that stores a firmware program.

2 is an ECC memory composed of RAM.

ECC data is stored during normal operation, and trace code is written during debug operation.

This trace code includes information indicating the starting position of the trace and information indicating the execution order of instruction steps in the firmware program.The former trace code is set externally. , the latter trace code is generated internally.

A trace control circuit 3 detects when a trace code indicating a trace start position is read from the ECC memory 2 during execution of the firmware program and starts trace control.

A trace code indicating the execution order is set at the address in the ECC memory 2 corresponding to the instruction step executed at -Vt.

Reference numeral 4 denotes an ECC circuit which performs error checking and error correction using the instruction data read from the program memory 1 and the ECC data read from the ECC memory 2, thereby guaranteeing the validity of the instruction data.

5 is a processor with program memories 1 and E
CC memory 2 is accessed and each instruction read from program memory 1 is executed.

6 is a counter, which is used to generate a trace code representing a sequence number that makes it possible to identify the order in which instruction steps are executed. This counter 6 is controlled by the trace control circuit 3, and the trace counter 6 is controlled by the trace control circuit 3.
When a code is detected, it is reset and starts counting, and when it reaches a predetermined value, it stops counting.

[Effect]

In FIG. 1, a debugging operator uses an appropriate means (not shown) such as a console connected to the outside of the device to specify the address of the instruction step at which debugging of the firmware program is to be started. A trace code indicating the start of tracing is written to the corresponding address in memory 2. For example, convert this trace code to “OO
゛.

Further, the operation of the ECC circuit 4 is prohibited.

When the firmware program is executed and the instruction step at the address at which debugging is to be started is read from the program memory 1, trace code 00' is read from the ECC memory 2.

The trace control circuit 3 uses this trace code '00°
When detected, the counter 6 is reset to start counting, and stopped when a predetermined value is reached. The predetermined value can be the maximum value of the counter 6 or any value smaller than that.

The counter 6 counts +1 each time the program memory 1 is accessed, that is, each time an instruction of the firmware program is fetched, and the counter 6 counts “00°”.
Generate trace codes with sequence numbers that change in ascending order, such as '01' and '02'.

The trace code generated by the counter 6 is written to the address of the ECC memory 2 that is being accessed at that time.

In this way, as execution of the firmware program progresses, the EC
A series of trace codes indicating the execution order are written to each address in the C memory 2 to create trace information.

When debugging is performed next time, the execution order can be confirmed by accessing the ECC memory 2, searching the trace code in ascending order starting from 00°, and reading the corresponding instruction.

〔Example〕

FIG. 2 shows the configuration of an apparatus according to one embodiment of the present invention.

In the figure, l is a program memory, 2 is an ECC memory, 3 is a trace control circuit, 4 is an ECC circuit, 5 is a processor, 6 is a counter, 7 is a write circuit, 8 is an address selector, 9 is an ECC inhibition circuit, 10 is a console.

Program memory 1 and ECC memory 2.

It is composed of RAM. The data width (instruction length) of the program memory 1 is 2-bit, and during normal operation, 6-bit ECC data that can correct 1-bit errors and detect 2-bit errors is stored in the ECC memory 2.

The trace control circuit 3 has a function of controlling the start and end of the trace operation.

FIG. 3 shows the detailed configuration of the trace control circuit 3. In the figure, 31 is a decoder that monitors the output of the ECC memory 2 in FIG. 2 to detect X "00°," and 32 monitors the output of the counter 6 in FIG. 2 to detect X "2F". It is a decoder that detects.

33 is an RS flip-flop, which is set on by the output of the decoder 31 and reset to off by the output of the decoder 32.

When the decoder 31 detects that the trace code X "00°" is output from the ECC memory 2.

It outputs a counter reset signal and turns on the RS flip-flop. RS flip flop 33
turns on, turns on the counter start/stop signal. Thereafter, when the decoder 32 detects the trace code X "2F" in the output of the counter 6, it turns off the RS flip-flop 33 and turns off the counter start/stop signal.

Returning to FIG. 2, counter 6 is a 6-bit counter that counts the access clock of program memory 1 during operation and outputs a trace code.

During normal operation, the processor 5 stores program memory! and send the address to ECC memory 2.

Access each of the instruction data and its corresponding E
Selling CC data.

Both the read instruction data and ECC data are E.
The data is sent to the CC circuit 4, subjected to error checking and error correction, and sent to the processor 5 as instruction data whose validity is guaranteed. In this way, the firmware
Each instruction of the program is read and executed by the processor 5.

The address selector 8 is selected by the processor via the processor bus, and is used when outputting the same address as the program memory to the ECC memory, and when the processor outputs the same address as the program memory to the ECC memory.
Select whether to set the trace code inside the CC memory or output the processor specified address when referencing the trace contents.

The tracing operation is performed according to instructions from the console 10.

First, a trace start address is given from the console 10 using a trace control command. This command switches the address selector 8 to the right address input, applies the trace start address transferred via the processor bus to the ECC memory 2, and also applies the trace code x' sent from the processor bus. Write oo'.

When writing is completed, the address selector 8 is returned to the left address input.

This trace control command also turns on the prohibition instruction in the ECC prohibition circuit 9 via the processor bus, and
The function of the C circuit 4 is stopped. In this state, the instruction data read from the program memory 1 is transferred to the processor 5 as is without an ECC check.

Next, run the firmware program. Here, first trace code x'oo' of ECC memory 2
Program memory l corresponding to the address written
When the instruction at address 2 is accessed, ECC memory 2
Trace code X“00゛” is read from.

The trace control circuit 3 resets the counter 6 when detecting the trace code X°00°.

Start counting operation.

The counter 6 originally has a counting function from x'oo' to X "3F". However, trace control circuit 3
When X “2F” is detected in the output of the counter 6, the counting operation of the counter 6 is stopped. Therefore, after counting up to X'2F', the counter 6 maintains f&X'2F'.

After starting, the counter 6 counts the access clock each time an instruction in the program memory 1 is accessed, and generates a trace code that is updated in ascending order such as X '01', X '02', etc. occurs.

These trace codes are sent to E via write circuit 7.
The data is sent to the CC memory 2 and written to the address given at that time.

As a result, a trace of the execution instructions of the firmware program is recorded in the ECC memory in an orderable manner by a series of trace codes.

The trace information recorded in the ECC memory 2 is as follows.

Trace using one of the firmware programs.
The code can be searched in ascending order and the corresponding instructions can be sold.

〔Effect of the invention〕

The present invention utilizes an ECC memory as a trace memory and provides a counter as a trace code generating means, thereby realizing a firmware program debugging mechanism with a small amount of hardware and a simple control mechanism.

Further, the present invention has the advantage that there is no need to add an extra instruction step for trace control to the firmware program, and the execution time of the firmware program is not delayed by the trace operation.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 is a diagram showing the configuration of one embodiment of the device of the present invention, FIG. 3 is a detailed configuration diagram of the trace control circuit in FIG. 2, and FIG. 4 is a diagram of the conventional device. FIG. In Figure 1. 1 Niprogram, Memory 2: ECC memory 3 Nidress control circuit 4: Ecc circuit 5: Processor 6 = Count

Claims (1)

[Claims] A device comprising a program memory (1) and an ECC memory (2) and incorporating and operating a firmware program with ECC, wherein the device is coupled to the ECC memory (2) and carries out instructions of the firmware program. A trace control circuit (3) that performs control to collect trace information indicating the order of execution of steps, and a counter (6) that generates a trace code that identifies the order of execution of instruction steps of the firmware program.
When debugging a firmware program, a trace code indicating the start of tracing is set at the address where tracing of the ECC memory (2) should be started from the outside, and the trace control circuit (3) ), and when the trace code indicating the start of tracing is detected, a counter (6) is activated and is updated sequentially each time the program memory (1) is accessed. Trace sequence number
write the generated trace code to the address of the ECC memory (2) corresponding to the accessed address of the program memory (1), representing the execution order of the instruction steps of the firmware program; A firmware program debugging method characterized by creating trace information.