JPH06175883A - Program debugger - Google Patents

Abstract

PURPOSE:To provide the program debugger which can improve exactness or efficiency for debugging a program and does not require any large capacity trace memory. CONSTITUTION:This device is provided with a mapping memory 12 for storing a program to perform debugging, flag memory 13 for storing information showing which of a loop starting instruction, loop repeating instruction, loop ending instruction and other instruction a certain instruction is corresponding to the respective instructions of the program stored in this mapping memory 12, CPU 11 for outputting trace information by executing the program stored in the mapping memory 12, address control circuit 15 for deciding an address to store the trace information based on the information stored in the flag memory 13, and trace memory 14 for storing the trace information at the address decided by the address control circuit 15.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a CPU (Central Proc
The present invention relates to a program debug device for debugging a program executed by an essing unit).

[0002]

2. Description of the Related Art As a conventional program debug device, for example, execution address, status information, read / write
Information indicating the execution state of write data (hereinafter referred to as “trace information”) is sequentially stored in the trace memory, and the stored trace information is displayed on the display to display the CP.
There is known a format in which debugging work is performed by checking the execution state of U.

In such a conventional debug device, the CP
All trace information about the instructions executed by U can be stored in trace memory. Further, of the trace information about the instructions executed by the CPU, only a program debug device capable of storing only the address range specified by the user in the trace memory, or storing only a specific instruction in the trace memory Program debug devices are also known.

[0004]

When tracing is performed using such a debug device, when the CPU repeatedly executes the same processing in a loop routine or a loop module, such as a software timer, many times, The same trace information is repeatedly stored in the trace memory.

Therefore, when the number of instructions of the loop routine or loop module to be executed is large or the number of repetitions is large, the trace memory may be filled with only the loop routine or loop module. In such a case, since it becomes impossible to store all the trace information about the instructions executed by the CPU in the trace memory in one trace, it may be difficult to judge the flow of processing of the entire program. is there. Also, in the case of a program in which a loop routine or a loop module is called as a subroutine or a function, if the number of instructions or the number of repetitions of the loop routine is large, the trace information such as the processing after the end of the loop and the current processing status will be displayed. There is a risk that it will not be possible to store them in the trace memory, making these checks impossible.

These drawbacks have been factors that reduce the accuracy and efficiency of the program debugging work.

In order to eliminate such a drawback, the capacity of the trace memory should be increased. However,
It is practically difficult to make such a capacity extremely large in terms of cost and the like.

The present invention has been made in view of the above-mentioned drawbacks of the prior art, and is capable of improving the accuracy and efficiency of the program debugging work and does not require a large-capacity trace memory. The purpose is to provide.

[0009]

A program debugging apparatus according to the present invention is a mapping memory for storing a program to be debugged and a loop of the instruction corresponding to each instruction of the program stored in the mapping memory. An instruction information storage memory that stores information as to which of a start instruction, a loop repeat instruction, a loop end instruction, or another instruction, and a CPU that executes the program stored in the mapping memory and outputs trace information An address control circuit for determining an address for storing the trace information based on the information stored in the instruction information storage memory; and a trace memory for storing the trace information at the address determined by the address control circuit, It is characterized by having.

[0010]

By providing an instruction information storage memory that stores information indicating the type of instruction, and determining the storage address in the trace memory based on this information, the trace information of exactly the same content is repeatedly stored in the trace memory. You can prevent it from being done. This allows
The substantial amount of trace information stored in the trace memory can be increased without increasing the capacity of the trace memory.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the program debug device according to the present invention will be described.

FIG. 1 is a block diagram schematically showing a circuit configuration of a trace circuit 10 in a program debug device according to this embodiment.

In FIG. 1, the evaluation CPU 11 executes a program to be debugged. A program executed by the evaluation CPU 11 is stored in the mapping memory 12.

The flag memory (instruction information storage memory of the present invention) 13 stores information indicating the type of the instruction in association with each instruction of the program stored in the mapping memory 12. Here, the type of instruction includes an instruction to start a loop (hereinafter, loop start instruction), an instruction to repeat a loop (hereinafter, loop repeat instruction), an instruction to exit from a loop (hereinafter, loop end instruction), and a normal execution. There are four types of instructions (instructions that do not correspond to any of the above three types of instructions). Further, this flag memory 13 is
When a command is read from the mapping memory 12 to the evaluation CPU 11, a loop start signal, a loop repeat signal or a loop end signal is output according to the content of information corresponding to this command.

The trace memory 14 includes the evaluation CPU 1
The trace information of the program executed in 1 is stored. Further, the address control circuit 15 uses the flag memory 13
The trace memory 14 receives the signal output by the
Outputs the storage address when storing trace information.

Next, the circuit configuration of the address control circuit 15 will be described with reference to FIG.

In the figure, the counter 21 generates a storage address 31 for storing the trace information in the trace memory 14. The storage address 31 output from the counter 21 is incremented by "1" each time the write signal 32 is input. Also, as will be described later, each buffer 22,
The storage address 31 output by 23 or 24 is loaded.

The initial value setting buffer 22 is a control CPU.
When the initial value control signal 35 is input from (not shown), the initial value 34 of the storage address is fetched from this control CPU and output to the counter 21.

When the loop start signal 36 is input from the flag memory 13, the start address buffer 23 fetches the storage address 31 output from the counter 21. Further, when the output control signal 37 is input from the buffer control circuit 26 described later, the storage address 31 is output to the counter 21.

The repeat address buffer 24 receives the loop repeat signal 38 from the flag memory 13,
The storage address 31 output from the counter 21 is fetched.
When the loop end signal 39 is input from the flag memory 13, the storage address 31 is output to the counter 21.

The flip-flop 25 is a flag memory 1
3 from the loop repeat signal 38 and write signal 3
When 2 is input, the load signal 33 is output.

The buffer control circuit 26 outputs the output control signal 37 when the loop end information 39 is not input, and stops the output of the output control signal 37 when the loop end information 39 is input.

Next, the operation of the trace circuit 10 in the program debug device according to this embodiment will be described.

First, the initial value setting buffer 22 in the address control circuit 15 fetches the initial value 34 of the storage address from the control CPU (not shown) and outputs it to the counter 21. The counter 21 loads the initial value 34 of this storage address and outputs it as the storage address 31.

The evaluation CPU 11 also reads the first instruction from the program stored in the mapping memory 12. At this time, the information corresponding to this instruction is read from the flag memory 13. If the read information is a loop start instruction, a loop repeat instruction or a loop end instruction, a loop start signal, a loop repeat signal or a loop end signal is output accordingly. On the other hand, when the read information is a normal execution instruction, no signal is output.

The trace memory 14 receives the storage address 31 from the address control circuit 15 and receives the evaluation C data.
The trace information is input from the PU 11, and the write control signal 32 is input.
This trace information is stored in the address indicated by the storage address 31 in accordance with the timing of.

The write control signal 32 is also input to the counter 21 in the address control circuit 15. Then, the counter 21 increments the value of the storage address 21 to be output by “1” according to the input timing of the write control signal 32.

As a result, when the next instruction read from the mapping memory 12 by the evaluation CPU 11 is not the loop start instruction, loop repeat instruction or loop end instruction, the trace information is stored in the storage area in which the trace information was previously stored. It is stored in the storage area of the next address.

On the other hand, when the instruction read from the mapping memory 12 by the evaluation CPU 11 is the loop start instruction, as described above, the start address buffer 2
3 fetches the storage address 31 output from the counter 21. At this time, since the flag memory 13 does not output the loop end signal, the buffer control circuit 26 outputs the output control signal 3
7, the start address buffer 23 outputs the fetched storage address 31 as it is. However, since the repeat instruction 38 is also not output from the flag memory 13, the flip-flop 25 does not output the load signal 33, and therefore the storage address 31 output by the start address buffer 23 is not loaded in the counter 21.

After that, when the write control signal 32 is input to the trace memory 14 and the counter 21, the trace memory 14 stores the trace information in the storage area indicated by the storage address 31, and the counter 21 outputs the same, as described above. The value of the storage address 31 is incremented by "1".

Next, when the instruction read from the mapping memory 12 by the evaluation CPU 11 is a loop repeat instruction, the repeat address buffer 23 outputs the storage address 31 output from the counter 21 as described above.
Take in.

Thereafter, when the write control signal 32 is input to the trace memory 14, the trace information is stored. At this time, the flip-flop 25 outputs the load signal 33, so that the storage address 31 output from the start address buffer 23 is loaded into the counter 21, and the storage address is output from the counter 21. Therefore,
The trace information to be stored in the trace memory 14 the next time will be stored in the area where the trace information related to the loop start instruction described above was previously stored. At this time,
The trace information related to this loop start instruction is erased.

In this way, each instruction forming the loop is repeatedly stored in the same storage area in the trace memory 14.

Then, at the end of the loop (ie,
When the loop end instruction is executed), the loop end signal is output from the flag memory 13. As a result, the buffer control circuit 26 stops outputting the output control signal 37, so that the start address buffer 23 stores the storage address 31.
Is no longer output, and the address buffer 24 repeatedly outputs the storage address 31. Then, the counter 21
The storage address 31 output from the repeat address buffer 24 is loaded and output as the storage address 31. Thus, the trace information related to the instruction next to the loop end instruction can be stored in the storage area of the address next to the trace information related to the previous repeat instruction.

As described above, in the program debug device of this embodiment, since each instruction forming the loop is repeatedly stored in the same storage area in the trace memory 14, finally, the loop is executed once. Only the trace information of will be stored in the trace memory 14.

Therefore, when the loop is executed, the storage area occupied by the trace information in the trace memory 14 can be reduced.

In this embodiment, the trace information about the last executed loop is left in the trace memory, but only the trace information about the first executed loop may be left in the trace memory. It is also possible to leave trace information for a preset number of loops in the trace memory by newly adding a counter that counts the number of loop repetitions.

[0038]

As described in detail above, according to the program debugging apparatus of the present invention, the storage area occupied by the trace information when the loop is executed in the trace memory can be reduced.

Therefore, the accuracy and efficiency of the program debugging work can be improved without increasing the capacity of the trace memory.

[Brief description of drawings]

FIG. 1 is a block diagram schematically showing a configuration of a trace circuit in a program debug device according to an embodiment of the present invention.

FIG. 2 is a block diagram schematically showing a configuration of an address control circuit shown in FIG.

[Explanation of symbols]

 11 evaluation CPU 12 mapping memory 13 flag memory 14 trace memory 15 address control circuit 21 counter 22 initial value setting buffer 23 start address buffer 24 repeat address buffer 25 flip-flop 26 buffer control circuit 31 storage address 32 write signal 33 load signal 34 Initial value of storage address 35 Initial value control signal 36 Loop start signal 37 Output control signal 38 Loop repeat signal 39 Loop end signal

Claims (2)

[Claims] 1. A mapping memory for storing a program to be debugged, and the instruction corresponding to each instruction of the program stored in the mapping memory is a loop start instruction, a loop repeat instruction, a loop end instruction, or another instruction. An instruction information storage memory that stores information on which of the instructions is applicable, a CPU that executes the program stored in the mapping memory and outputs trace information, and the information stored in the instruction information storage memory A program debug device, comprising: an address control circuit that determines an address for storing the trace information based on the above; and a trace memory that stores the trace information at the address determined by the address control circuit. 2. When the CPU repeatedly executes each instruction from the loop start instruction to the loop repeat instruction a plurality of times, the trace information for each instruction is stored in the same storage area in the trace memory. 2. The program debug device according to claim 1, wherein the address control circuit determines an address so that the address is repeatedly stored.