JPH05342378A - Evaluation chip - Google Patents

Abstract

PURPOSE:To easily perform the external control by providing a monitor ROM where specific instructions are stored and control bits are provided. CONSTITUTION:A NOP instruction which executes nothing, a jump (JMP) instruction, a transfer instruction group for internal register read, and a transfer instruction group for internal register write are stored in an output instruction part (INSTRUCTION) of a monitor ROM 1. Control bit parts M0 to M3 of the monitor ROM 1 are connected to a latch 2. The latch output M0 controls reset of a program counter 12. The output M1 controls selection of the instruction part of the monitor ROM 1 and an address register 11 at the time of execution of the JMP instruction in the monitor ROM 1. Outputs M2 and M3 control a flip flop 7. Thus, only address designation of the monitor ROM 1 is fundamentally performed as the control from the outside to realize the debugging function.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a large scale integrated circuit (LS).
I) Variation chip in I), more specifically, it is advantageously applied to a one-chip microcomputer, a digital signal processor, etc., and relates to an LSI evaluation chip (variation chip) having a program memory inside or outside the chip. ..

[0002]

2. Description of the Related Art Conventionally, this kind of variation chip has realized functions such as instruction insertion from the outside, execution control, display / change of internal registers, etc. with dedicated logic so that a program can be debugged. It was

[0003]

However, in such a conventional technique, since the dedicated logic is used for debugging in accordance with the internal timing of the microcomputer or the like, a great deal of labor is required for its development, and it is originally necessary. It was easy to cause bugs such as different operation from the chips of.

Further, the conventional functional design as the variation chip tends to be neglected in comparison with, for example, the present chip functioning as a microcomputer in practice, and an approach of performing a lot of control outside the chip is generally used. Met. As a result, the variation chip had a complicated interface for instruction insertion, execution control, and internal register display. As a result, the external interface becomes complicated and it is very difficult to use.

It is an object of the present invention to solve the above-mentioned drawbacks of the prior art and to provide an variation chip which allows easy external control by providing the variation chip with a monitor ROM for performing more general-purpose control. And

[0006]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a variation chip used for debugging a large scale integrated circuit, which has a plurality of instructions for executing a specific instruction. Is stored and has a storage means provided with several control bits, a register and a counter controlled by the control bit, and at the time of debugging, by the instruction and the control bit of the storage means, Debug processing is performed by selectively executing the instructions of the storage means and the program memory of the large scale integrated circuit.

[0007]

Embodiments of the variation chip according to the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. Reference numeral 1 is a monitor RO for storing a specific instruction.
M, reference numerals 3 and 4 are selectors, reference numeral 5 is an instruction register (IR), reference numeral 6 is a program counter (P
C), reference numeral 10 is a break pointer (BP), reference numeral 11
Is an address register (ADR), reference numeral 12 is a monitor RO
An M program counter (PC0), reference numeral 13 is an input / output register (I / O).

The output / instruction section (INSTRUTION) of the monitor ROM 1 executes N
An OP instruction, a jump instruction, an internal register / read transfer instruction group, an internal register / write transfer instruction group, and the like are stored. In the output / instruction section of the monitor ROM 1, a part of the address section or the like is input to the selector 3, and the other part is input to the selector 4 together with the output of the selector 3.

On the other hand, at the other input terminal of the selector 3,
It is connected to the output terminal of the address register 11 for setting the start address when executing the program, and the other input terminal of the selector 4 is connected to the output terminal of the program memory 15 addressed by the program counter 6. .. Further, the control bit parts (M ₀ , M ₁ , M ₂ , M ₃ ) of the monitor ROM ₁ are connected to the latch 2, and the control bits M ₀ , M ₁ , M ₂ ,
M ₃ is input.

The debug data bus DBi terminal is connected to the debug registers 10, 11, 12, and 13 to read / write data. Bar RD, Bar WR, D
The Ai terminal is input to the asynchronous interface control circuit 14 and, after being synchronized with the internal timing, reads / writes the debug registers 10 to 13. It should be noted that, in the drawings, the symbol with a "|" in the symbol indicates "bar RD".
As described above, in the present specification, a "bar" is added before it.

The input / output register 13 is connected to the internal data bus and performs reading / writing of the register originally possessed by the microcomputer or the like, that is, the input register, the output register, the temporary register or the accumulator. The program counter 12 is a monitor ROM
This is a counter for designating an address of 1.

The break pointer 10 is a pointer to which a stop address for executing a program is set, and its output terminal is connected to the comparator 9. The output of the program counter 6 is connected to the other input terminal of the comparator 9. The output of the comparator 9 becomes "1" when these two addresses match, and is output to the input terminal of the OR circuit 8.

An external reset (RESET) and the latch output M ₃ from the latch circuit 2 are input to the other input terminal of the OR circuit 8. The output terminal of the OR circuit 7 is connected to the set side of the flip-flop 7 having a set / reset terminal. The latch output M ₂ of the latch circuit ₂ is input to the reset side of the flip-flop 7.

The output terminal Q of the flip-flop 7 is connected to the external FLAG terminal, the increment prohibition control terminal INH of the program counter 6 and the control terminal of the selector 4. The selector 4 is controlled by the output Q of the flip-flop 7.

The latch output Mφ of the latch circuit 2 is input to the reset terminal R of the program counter 12 to control the reset of the counter PC0. Latch output M
₁ is output to the control terminal of the selector 3
Control.

Here, the meaning of the latch outputs M _{0 to} M ₃ will be described. The output M ₀ is an output for performing the reset control of the program counter 12, and when it is “1”, the counter 12 is reset to “0”. Output M ₁ is monitor ROM ₁
Is an output for performing selection control between the instruction section of the monitor ROM 1 and the address register 11 when the JMP instruction is executed. When this signal is "1", the address register 1
The content of 1 is selected as the jump address.

The output M ₂ controls the flip-flop 7. When this signal is "1", the output of the flip-flop 7 becomes "0", and the program counter 6 is incremented. The output of the flip-flop is also input to the selector 4, and the output of the program memory 15 is selected as an instruction. Output M
Reference numeral ₃ controls the set signal of the flip-flop 7 through the OR circuit 8. When this signal is "1", the output of the flip-flop 7 becomes "1" and the program counter 1
Increment of 5 is suppressed, and monitor ROM1
Is output as an instruction by the selector 4.

Next, the operation of this embodiment will be described with reference to FIGS.

After releasing the RESET signal, PC and PC0
Is reset to “0”, and the S-RFF of 7 is
It is set to "1". Therefore, as mentioned above, P
The C increment is suppressed, and the instruction executes address 0 in the monitor ROM. Next, from the time chart of FIG. 2, the program counter 12 (PC0) is set by the latch output M ₀ and the address 0, that is, NOP.
Continue executing instructions.

Next, the case of executing from a specific address to a specific address will be described. At this time, it is assumed that the start address (n address) is written in the address 11 and the stop address (m address) is written in the break pointer 10, respectively.

From the bar WR terminal to the program counter PC
Write address 2 to 0. Monitor R by the output of this PC0
The address 2 of OM1 is read and the JMP instruction is set in the instruction register (IR) 5. At this time,
The output of the address 11 is selected as the jump address by the latch output M ₁ .

When this JMP instruction is executed, the program counter 6 (PC) becomes the address n, the flip-flop 7 is reset to "0" by the latch output M ₂ , and the prohibition of increment of the program counter PC is released. Further, the selector 4 selects the output of the program memory 15, and the control is transferred to the program memory 15 side. Therefore, the execution is started from the address n of the program memory.

The program counter PC0 has a latch output M.
Continue to specify 0 address by ₀ signal. When the program counter PC reaches the address m, the output of the comparator 9 is "1".
Then, the flip-flop 7 is set to "1", the control returns to the monitor ROM 1, and the NOP instruction at the address 0 continues to be executed. This completes the execution of the program from addresses n to m.

Next, the MOV instruction is executed by writing the address 3 to the program counter PC0, and the value of the internal register is transferred to the input / output register 13. In this case, regardless of the latch output M _3, the output of the flip-flop maintains "1". This input / output register 13 is read out of the evaluation chip by the external bar RD signal. From address 4, address 5,
The contents of all the registers can be read by repeating the address n-1. Note that the 1st address of the monitor ROM 1 is an address used for a forced break at the time of program runaway.

[0026]

As described above, according to the variation chip of the present invention, by incorporating the monitor ROM and its control circuit, it is possible to greatly simplify the structure of the ever-evaluating chip. Further, since the control from the outside can basically realize the debug function only by specifying the address of the monitor ROM, the interface can be made very simple. Therefore, by applying the variation chip according to the present invention to a microcomputer, a digital signal processor or the like, it becomes possible to perform debugging quickly and accurately.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing an embodiment of an variation chip according to the present invention,

FIG. 2 is a time chart showing an operation sequence in the embodiment shown in FIG.

[Explanation of symbols]

 1 Monitor ROM 3, 4 Selector 5 Instruction Register 6 Program Counter 10 Break Pointer 11 Address Register 12 Monitor ROM Program Counter 13 Input / Output Register

Claims (1)

[Claims] 1. A memory in which a plurality of instructions for executing a specific instruction are stored and a few control bits are provided in an variation chip used for debugging a large-scale integrated circuit. Means and a register and a counter controlled by the control bit, and when debugging, store the instruction of the storage means and the program memory of the large scale integrated circuit by the instruction and control bit of the storage means. The variation chip is characterized in that debug processing is performed by selectively executing any of the predetermined instructions that have been executed.