JPS6230453B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to electronic computers. For more details,
This invention relates to a microcomputer using a microprogram control method that enables simple and high-speed inspection. A microcomputer consists of one or more
Although it is an electronic computer composed of LSI chips, it is difficult to observe arbitrary signals inside the LSI chip, and the number of terminals on the package is limited. The task of checking whether or not the In addition, the length of inspection time greatly affects the price of LSI. Figure 1 shows an example of a conventional microprogram computer. In the figure, 100 is
101 is a main memory for storing machine language and data; 102 is a main memory address register (hereinafter referred to as MAR); 103 is an instruction counter (hereinafter referred to as IC);
104 is a general-purpose register and arithmetic unit (hereinafter referred to as RALU). 105 is main storage device 1
This bus connects 01, MAR 102, IC 103, RALU 104, and instruction register 106 (hereinafter referred to as IR). 107 is a programmable logic array (hereinafter referred to as PLA), 108 is a micro address counter (hereinafter referred to as MAC), 109 is a control storage unit, 110 and 111 are part of the output signal of the micro instruction decoder 112; teeth
A signal 111 instructs an operation to store the output of the PLA 107 in the MAC 108, and a command signal 111 instructs an operation to increase the contents of the MAC 108 by one. The operation of the apparatus shown in FIG. 1 will be explained according to the program shown in Table 1.

【table】

[Table] Table 1 is stored in the control memory 109 in FIG.
1 shows an example of a program that emulates a machine language program stored in the main storage device 101 using the device shown in FIG. When the device of FIG. 1 starts machine language emulation, the value of MAC 108 is initially 0,
The microinstruction at address 0, that is, the first row of Table 1, is read out and input to the decoder 112.
By the output signal of the decoder, IC103 and RALU
104 is controlled, and the contents of IC103 are transferred to bus 10.
5 to the RALU 104, an effect of adding 1 is performed, and the result is stored in the IC 103 via the bus 105 again. At the same time signal 111
turns ON, and the contents of MAC 108 also increase by 1. As a result, the value of MAC108 becomes 1,
The microinstruction at address 1 of the control memory, ie, the second row of Table 1, is executed. 2nd line IC → MAR
When this microinstruction is executed, the contents of the IC 103 are transferred to the MAR 102 via the bus 105, and at the same time the contents of the MAC 108 are increased by 1 to become 2. Next, when the microinstruction on the third line of Table 1 is executed, the contents of MAR102 are input to the main memory 101 as an address, and the contents of the corresponding address are transferred from the main memory 101 to the bus 105.
The data is stored in the IR 106 via the . That is, the machine language instructions in the main memory 101 are read out to the IR 106. The contents of IR106 are PLA10
7, and the start address of the microprogram routine corresponding to the machine language instruction is output from the PLA. Here, for example, a machine language instruction stored in the IR 106 is stored in register 1 in the RLAU 104.
Similarly, if the contents of (R1) are the main memory address,
If the instruction is to write the data held in register 0 (R0) in the RALU 104 to the main memory 101, the output value of the PLA 107 is 100.
becomes. When the microinstruction in the fourth row of Table 1 is executed, the signal 110 turns ON and the output of the PLA 107 is stored in the MAC 108. That is, the value of MAC 108 is 100. This then causes the control memory 109
The contents of address 100, the microinstruction R1→MAR is read, and the contents of register 1 are read.
Transferred to MAR102. Next, the control storage unit 10
The contents of address 101 of register 9 are read out, and the contents of register 0 are transferred to main storage device 101.
The emulation of the machine language instructions stored in the IR 106 is now complete. Next, when the contents of address 102 of control storage unit 109 are executed, the value of MAC 108 becomes 0 again, execution of the microinstruction of address 0 begins, and the machine code of the next address in main memory 101 is executed. Instruction reading begins. When manufacturing and inspecting a device such as that shown in FIG. 1, it is necessary to check whether the contents of the control storage section 109 are stored correctly. However, the control storage unit 1
Since the contents of 09 cannot be directly read from outside the CPU chip, it is necessary to try to operate all the microprograms written in the control storage section 109. Therefore, it is necessary to emulate all the machine languages that drive the microprogram routines in the control storage section 109, making the test program complex and requiring a long test time. The present invention solves these drawbacks,
The present invention provides a microcomputer that makes it possible to easily and quickly test a microcomputer composed of an LSI. FIG. 2 is an example of a microprogram controlled electronic computer according to the present invention. 301~ in the diagram
Reference numeral 311 has the same functions as 101 to 111 in FIG. 1, and the explanation thereof will be omitted. 312
313 is a microinstruction decoder, and 313 is a control storage unit 309 for emulation (hereinafter referred to as CMA).
and the output of a test control storage unit 314 (hereinafter referred to as CMB), according to the value of a signal 317, and inputs the selected signal to the decoder 312. 315 is a test micro address counter (hereinafter referred to as MACB). ), 316 is its output signal. 317 is a control signal that specifies whether to put the CPU 300 in a normal operating state or a test state, and 318 is ON when 315 is at a specific value.
The signal 319 is a signal that instructs the operation to increase the contents of the micro address counter 308 (hereinafter referred to as MACA) for CMA by 1. 320 is a logic circuit that generates a signal 319 from signals 311, 317, and 318. FIG. 3 shows a specific example of the MACB 315 and logic circuit 320 in FIG. 2.
411 and 415 to 419 in Figure 3 are 3 in Figure 2.
11 and 315 to 319, respectively. 4
15 is a D-type flip-flop, and since the inverted output signal 418 is applied to the D input, it alternately takes values of 0 and 1 each time the clock input 400 is turned ON. That is, it operates as a 1-bit counter. When signal 417 is 0, ie, OFF, flip-flop 415 remains reset and signals 416 and 418 do not change. Also, signal 418 does not affect signal 419,
The value of signal 411 is transmitted to signal 419 as is. If the signal 417 is 1, that is, in the ON state,
Flip-flop 415 receives clock signal 400.
The output is inverted every time it turns ON, and the signal 41
1 does not affect signal 419 and signal 418 becomes signal 4.
19. In the device shown in FIG. 2, whether the signal 317 is ON or not
It has two different operation modes depending on whether it is OFF or not. First, a case where the signal 317 is OFF will be described. When the signal 317 is OFF, the multiplexer 313 selects the output of the CMA 309 and inputs it to the decoder 312. Logic circuit 320 also transmits the value of signal 311 to signal 319. The device of FIG. 2 thus operates in the same way as the device of FIG. Next, the operation when the signal 317 is in the ON state will be explained. When the signal 317 is ON, the multiplexer 313 selects the output of the CMB 314 and inputs it to the decoder 312. Logic circuit 320 is also in a state of transmitting signal 318 to signal 319. Therefore, the device in Figure 2 is CMB31
The operation is performed according to the microphone program stored in 4. CMB 314 consists of two words and has only addresses 0 and 1. MACB315 is 1
It operates as a bit counter and the signal 316 is 0.
and 1 alternately. Therefore, the contents of addresses 0 and 1 of CMB 314 are read out alternately and executed repeatedly. The operation of the program written in the CMB 314 will be explained in more detail using the example shown in Table 2.

[Table] When the value of MACB315 becomes 0 and the microinstruction at address 0 of CMB314, that is, the first line of Table 2, is read and executed, the contents of MAR302 will be
Increase by 1. Next, when the microinstruction at address 1 of CMB 314, that is, the second row of Table 2, is executed, the contents of CMA 309 are read and
5 and is stored in the main storage device 301. The main memory address to be stored is determined by the contents of MAR302. Further, the value read from the CMA 309 at this time is the content of the address held in the MACA 308. The signal 419 in FIG. 3 is 1 because the signal 419 is 1.
Since 6 is 0, when address 0 of CMB 314 is read, signal 319 is turned ON and MACA 308 is increased by 1. Therefore,
Each time the two microinstructions at addresses 0 and 1 of CMB314 are executed, MACA308
is increased by 1, and the contents of MAR302 are also increased by 1. Therefore, by repeating this operation,
The contents of consecutive addresses in the control storage unit 309 are stored one after another in consecutive addresses in the main storage device 301 . As described above, by using the method of the present invention, the contents of the control storage section can be easily and quickly stored by the CPU.
can be output to the outside, and inspection time is also shortened. The present invention includes two control storage sections and two control storage address counters, one control storage section and address counter supplying microinstructions to a decoder, and the other control storage section and the other address counter supplying microinstructions to a decoder. By being freed from the control of the CPU and allowing the other address counter to operate as a read counter for the other control memory and the other control memory to function as a data source,
This provides a method for outputting the contents of the control storage section to the outside of the CPU. In the above embodiment, to simplify the explanation, the number of words in the control memory storing the test microprogram was set to 2, and the bit width of the address counter in the control memory was set to 1 bit. It is clear that there is no limit to the number of words stored and the bit width of both address counters.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional microprogram type electronic computer, and FIG. 2 is a block diagram of a computer according to an embodiment of the present invention.
FIG. 3 is a block diagram showing an example of a specific configuration of a part thereof. 301... Main memory device, 302... Main memory address register, 303... Instruction counter, 304
... General-purpose register and arithmetic unit, 305 ... Bus,
306...Instruction register, 307...Programmable logic array, 308...Micro address counter, 309...Emulation control storage section, 312...Micro instruction decoder, 31
3... Multiplexer, 314... Control storage unit for inspection, 315... Micro address counter, 3
20...Logic circuit, 415...Flip-flop.

Claims (1)

[Claims] 1 A first counter, a first control storage section that uses the counter as an address input, a second counter, a second control storage section that uses the counter as an address input, and first and second control A selector that selects the output of the storage section and inputs it to the decoder, a first signal that controls the selection operation of the selector, and a second signal that indicates that the value of the second counter has reached a specific value. and the third signal output from the decoder
a logic circuit that generates a fourth signal that instructs the counter to increase; a first mode that inputs the output of the first control storage section to the decoder; and a logic circuit that inputs the output of the second control storage section to the decoder; A microcomputer characterized by having a second input mode, and outputting the contents of the first control storage section to the outside of the chip by operating in the second mode.