JPH0215090B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a memory circuit useful for testing and diagnosing logic devices. Conventional memory circuits include a write address designation signal, a read address designation signal, write data, a read data output, and a clock signal that defines the write timing, and write data given to an address designated by the write address designation signal. It is configured to write in synchronization with the supply of a clock signal, and to read out the stored contents at an address designated by a read address designation signal as read data. This storage circuit is used for the purpose of temporarily holding data to be processed within the logic device. It is generally known that a functional test of a sequential logic circuit device composed of gate circuits and registers can be easily performed by converting the target sequential logic circuit into a pseudo combinational circuit at the time of testing. In other words, in this method, in addition to the original function of each register in the circuit under test, a configuration is adopted in which all registers function as shift registers based on control signals, and during testing, all registers are configured to function as shift registers via the shift register path. An arbitrary value is set, and after normal operation of the circuit, the contents of all registers are read out again via the shift register path by a control signal.
This makes it possible to treat all registers of the target sequential circuit equally as circuit input terminals and circuit output terminals. However, in order to apply this test method to a conventional logic device including the aforementioned memory circuit, it is necessary to incorporate all the bits of the memory circuit into the shift register path, but it is necessary to perform a shift operation on all the memory cells of the memory circuit. It is difficult to add such circuits because the amount of addition is enormous and the additional circuits significantly degrade the original performance of the memory circuit.
For this reason, during testing, as shown in FIG. A method has been adopted to do so. In this method, it is necessary to operate the data switching circuit 15 using the state designation signal 14 to switch between the data 16 from the storage circuit and the data from the detour 17. In this method, when testing using a shift register path, the memory circuit is not tested, so a separate test must be performed, which complicates the test.Furthermore, the data output of this memory circuit is If the signal does not include a register circuit and is again input to the memory circuit 13 via the second logic circuit 12 and the first logic circuit 11, a logic signal loop may occur and the logic state may not be determined. It has the following disadvantages. Next, when the device is powered on, the states of each memory cell in the memory circuit built into it vary.
Memory contents cannot be determined. Therefore, when the power is turned on, the correspondence between the data stored in the memory circuit and these parity check bits is different, so it is necessary to perform certain initial settings, or initialization, before using this memory circuit. be. In conventional initialization,
A certain amount of data is written through normal read/write operations, but it is difficult to control because it is performed via logic circuits surrounding the memory circuit, and the number of write operations is equivalent to the number of addresses in the memory circuit. Further, if there is an abnormality in the peripheral logic circuit, initialization cannot be performed correctly. There is also a method of uniform initialization by manipulating the writing means to simultaneously write the same data to all addresses, but since all memory cells operate at the same time, this causes a large change in the power supply current at once, resulting in stable operation of the circuit. It has the disadvantage of being undesirable. SUMMARY OF THE INVENTION An object of the present invention is to provide a memory circuit which eliminates the drawbacks of the conventional apparatus described above, is easy to initialize, and is effective for inspection and diagnosis. The circuit of the present invention includes a memory means for storing data, a state specifying means for specifying whether the memory means should be used in a normal state, a shifted state, or an initialized state, and a shift state by the state specifying means. an address counter whose contents are incremented in synchronization with a clock signal when one of the states and the initialization state is specified; and a write address given from the outside when the normal state is specified by the state specifying means. writing means for writing write data into a storage location of the storage means determined by the output signal of the address counter when either one of the shift state and the initialization state is specified by the signal; reading means for reading data from a storage location corresponding to the storage state determined by a read address signal externally applied when a state is designated and by an output signal of the address counter when a shift state is designated; When the normal state is designated by the designation means, the data given from the outside is designated, and when the shift state is designated, the data read out by the reading means and shifted by 1 bit, and the data shifted by 1 bit from the outside are designated, and the initialization state is designated. and write data supply means for supplying predetermined data as write data to the storage means when the storage means is written. Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 2 shows an embodiment of the memory circuit of the present invention, including a state designation signal input 100, a clock signal input 22, an address counter 23, a write circuit 24, a read circuit 25, and a write data supply circuit 2.
6 are configured. The state designation signal 100 is a 2-bit signal that designates the state as shown in the table below.

[Table] The address counter 23 receives the state designation signal 100.
is in the shifted state and initialized state (signal 1
Clock signal 2 when 00-1 is logical value “1”)
It is incremented by 1 only at the leading edge of 22 (when changing from logical value "0" to logical value "1"), and the state designation signal 100 is in the normal state (signal 100
-1 is the logical value "0"), the output state is held regardless of changes in the clock, and the reset signal 27 is set to the address counter 23.
It has a function to set the data to a predetermined initial state. The write circuit 24 includes a write address selection circuit 28,
Write address storage circuit 29, write address decoding circuit 3
0 and an AND circuit 31. The storage circuit referred to here is a circuit that outputs the input as is when the applied clock signal has a logical value of "0", and holds the output when the applied clock signal has a logical value of "1". Logic value state designation signal 100 is in normal state (signal 100-1
is the logical value “0”), the write address selection circuit 28
selects the write address designation signal 32 from the outside and puts it in the shift state and initialize state (signal 100-
1 is logical value “1”), address counter 2
3 output signals are selected. The selected write address designation signal is input to the signal only address storage circuit 29, and the output of the write address storage circuit 29 is input to the write address decoding circuit 30. The decoding result of the write address decoding circuit 30 and the clock signal 22 are supplied to an AND circuit 31. As a result of the decoding from the write address decoding circuit 30, only one output signal has a logic value "1" according to the output of the write address storage circuit 29, and all others have a logic value "0".
becomes. Therefore, the AND circuit 3 given the output signal of the logic value "0" of the write address decoding circuit 30
The output of the AND circuit 31, which is given the only output of the write address decoding circuit 30 with the logic value "1", has a logic value of "0" regardless of the state of the clock signal 22. When the logical value is "1", the logical value is "1", and when the logical value is "0", the logical value is "0". Each output signal of the AND circuit 31 and the output signal 33 of the write data supply circuit 26 are applied to a memory cell 34 at each intersection arranged in a matrix. This operation of changing the state of the memory cell 34 is performed by the write address decoding circuit 30 with the only logical value "1".
The output from the AND circuit 31 selected depending on the state is set to a logic value "1" by the clock signal 22, and the data holding function of the memory cell 34 connected to this output is temporarily lost. This is executed by setting the state corresponding to the state of the output). Next, in the readout circuit 25, a readout address selection circuit 35 selects the external readout address designation signal 36 when the state designation signal 100 is in the normal state, and selects the output signal of the address counter 23 when the state designation signal 100 is in the shift state. . In the read operation, the output of the read address selection circuit 35 is decoded by the read address decoding circuit 37, and the content of the memory cell at the activated address is transmitted via the sense line 38 by the output having the only logic value "1". The data is read out by the output buffer circuit 39 and executed by being output to the data output terminal 40. Furthermore, the write data supply circuit 26
consists of a write data selection circuit 41 and a write data storage circuit 42. When the state designation signal 100 is normally external (signal 100-1 is logic value "0" and memory 100-
When the external write data signal 43 is in the shifted state (the signal 100-1 is the logic value "1" and the signal 100-2 is the logic value "0"), the output buffer circuit 39 When the data obtained by shifting the data by one bit is in the initialized state (both the memory 100-1 and the signal 100-2 have a logical value of "1"), the fixed data signal 80 is selected. In the shift state, the missing bit position due to a 1-bit shift is filled with external shift input data 44.
is supplied. The output of the write data selection circuit 41 is input to the write data storage circuit 42, and when the clock signal 22 has a logic value of "0", the input is output as is, and when the clock signal 22 has a logic value of "1", the output is held. Note that the data output (40 at the right end) which is not connected to the write data selection circuit 41 due to the 1-bit shift is treated as a shifted output in the shifted state. Now, when the state designation signal 100 is in the normal state and the clock signal 22 has a logical value of "0", the write address selection circuit 28, the read address selection circuit 35, and the write data selection circuit 41 receive the write address designation signal 32 from the outside, respectively. The read address designation signal 36 and the write data input 43 are selected, and the write address storage circuit 29 and the write data storage circuit 42 are in a state of outputting the inputs as they are. At this time, since the clock signal 22 has a logic value of "0", all output signals of the AND circuit 31 have a logic value of "0", and all memory cells are not affected in any way. As the clock signal 22 changes from the logic value "0" to the logic value "1", both storage circuits 29 and 42 shift to the output holding state, and the memory cell 34 at the address specified by the write address storage circuit 29 is Write data storage circuit 4
Transition to a state where the state of 2 is output as is. Subsequent changes in the state of the write address designation signal 32 and the write data input 43 are caused by the internal storage cell 3 because both storage circuits 29 and 42 are in the holding state.
4 has no effect. In other words, the write operation is performed using the write address designation signal at the time when the clock signal 22 changes from the logical value "0" to the logical value "1";
This is done using write data. Further, the contents of the storage address designated by the read address designation signal 36 are read out to the data output terminal 40. Next, when the state designation signal 100 designates the shift state, the write address selection circuit 28 and the read address selection circuit 35 both select the output of the address counter 23, and the write data selection circuit 41 selects the data of the output buffer circuit 39 by 1. The bit-shifted data and the shift input data 44 are selected, and the address counter 23 is in a state where it can step in synchronization with the clock signal 22. In this state, if the clock signal 22 has a logical value of "0", the write address storage circuit 29 and the write data storage circuit 4
2 is a state where the input is output as is,
All the output signals of the AND circuit 31 are logical “0”
Therefore, all storage cells are not affected in any way. At this time, both address decoding circuits 30 and 37
both designate the same address because their input address designation signals are the outputs of the address counter 23. Therefore, the address being read at this point is the address to be written next, and the write data is a combination of the data being read at that point shifted by 1 bit and the shifted input data. be. As the clock signal 22 changes from the logical value "0" to the logical value "1", both storage circuits 29 and 42 shift to the output holding state, and the memory cell 34 designated by the write address storage circuit 29 receives the write data. The state shifts to a state where the state of the storage circuit 42 is output as is. At this time, the address counter 23 is also incremented and its contents are incremented by one. Therefore, the output of the read address decoding circuit 37 changes and the contents of the next address are read, but since both storage circuits 29 and 42 are in the holding state, the internal memory cell 34 is not affected at all. As a result, the contents of one address are shifted by one bit and rewritten. Note that shift input data from the outside is written in the bit positions that are shifted and missing at this time. 4 words about shift operation in shift state ×
Further explanation will be given by taking a 4-bit memory circuit as an example. In FIG. 3A, the states of the 16-bit memory cells of this memory circuit are A, B...O, P (each character represents a logic value "1" or a logic value "0"), and the shift input data terminal ( Only the shift output (lower right: output data that is not rewritten), and the address specified by the address counter (arrow on the right side) are shown. When the clock signal changes from the logical value "0" to the logical value "1" in this state, as shown in Figure 3B, 3 bits of the contents of address 0 are written in a state shifted by 1 bit to the right and shifted at the same time. Input data Q is written to the leftmost bit position. Also, at this time, since the contents of the address counter are incremented by 1, the contents of address 1 are read out to the output terminal. Similarly, FIGS. 3C to 3H show how the memory circuit changes each time the clock signal changes from logic value "0" to logic value "1". As the clock is further changed, it is easy to see that the data input from the shift input terminal is output in the same order as when it was input. Next, FIG. 4 shows how a plurality of such memory circuits are cascaded with respect to the shift path. In this figure, the shift output 51 of the first storage circuit 50 is connected to the shift input data terminal 53 of the second storage circuit 52.
and the shift output 5 of the second storage circuit 52
4 is connected to the shift input data terminal 56 of the third storage circuit 55. Thereby, a shift register is formed which includes all the bits of the storage circuit in its path between the shift input data terminal 57 and the shift output terminal 58 when the shift state is designated by the state designation signal. Therefore, in the logic circuit device using the memory circuit of this embodiment, the state of all memory elements (registers and memory circuits) in the device can be set to any value via the shift register path using the state designation signal. Furthermore, after normal operation, the contents of all storage elements can be read out again via the shift register path in response to a state designation signal. This makes it possible to treat all memory elements of the logic circuit device including memory elements equally as input terminals and output terminals of the device. Next, when the state designation signal 100 designates the initialized state, the write address selection circuit 28 selects the output of the address counter 23, the write data selection circuit 41 selects the fixed data signal 80, and the address counter 23 is synchronized with the clock signal 22. He is now in a position where he can make progress. In this state, if the clock signal 22 has a logical value of "0", the write address storage circuit 29 and the write data storage circuit 4
2 is a state where the input is output as is,
All the output signals of the AND circuit 31 are logical “0”
Therefore, all storage cells are not affected in any way. When the clock signal 22 changes from the logical value "0" to the logical value "1", both storage circuits 29 and 42 shift to the output holding state, and the storage cell 34 specified by the write address storage circuit 29
The state shifts to a state where the state of the write data storage circuit 42 is output as is. At this time, the address counter 23 is also incremented and its contents are incremented by one.
However, since both storage circuits 29 and 42 are in the holding state, there is no effect on the internal storage cell 34. A fixed data signal 8 is sent to the memory cell 34 belonging to one address by a clock with a logical value of "1".
This means that 0 has been written. Thereafter, as the address counter 23 increments, the fixed data signal 80 is
is written in the memory cell 34 at each address, and thus the randomness of the memory state of each memory cell when the power is turned on can be sorted out and set to a constant state. When a large-capacity storage circuit is configured using such a storage circuit as a unit, the above-described initialization method is even more effective. In other words, in a normal state, if you use the external write address designation signal 32 and the external write data signal 43, you can write to only one address with one clock, and it takes several addresses to initialize all addresses. number of clocks required. However, in this embodiment, initialization can be performed in parallel for each unit storage circuit that constitutes a large-capacity storage circuit, and no matter how large the storage circuit is, the number of clocks required to initialize one unit storage circuit is limited. It will be fine. In other words, the time required to initialize a large capacity storage circuit having m times the number of words of a unit storage circuit can be reduced to 1/m in this embodiment compared to the conventional storage circuit configuration. Note that in this embodiment, the fixed data signal supply is treated separately from the external write data signal supply for convenience of explanation, but the present invention is not limited to this, and the fixed data signal supply is handled separately from the external write data signal supply. Data signals can also be supplied externally, and the supply lines can be the same. In this case, the selection in the write data selection circuit 41 is made by the signal 100-
Regardless of the logical value of 1, when the signal 100-2 has a logical value of "1", it receives a write data signal from the outside, and when it has a logical value of "0", it outputs the write data signal from the output buffer circuit 3.
The data obtained by shifting the data of 9 by 1 bit and the shift input data 44 are selected. Furthermore, although this embodiment has shown an example in which the external write address designation signal and the external read address designation signal are independent, the present invention can also be applied to a configuration in which they are shared. In this case, it is possible to share the address decoding circuit, the bit line, the sense line, etc., but in the normal state, the write operation and the read operation cannot be executed independently. However, this does not pose any problem in the shift state and initialization state. As described above, the present invention is configured so that all bits of the storage circuit are incorporated into the shift register path by the state designation signal, and by initializing by writing fixed data by the state designation signal, the initialization time can be shortened and the storage circuit can be inspected. This has the effect of making diagnosis easier.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a logic device including a conventional memory circuit, FIG. 2 is a diagram showing an embodiment of the present invention, and FIGS. 3A to 3H explain the operation of the embodiment of the present invention. FIG. 4 is a diagram showing a state in which the memory circuits of the present invention are connected in cascade with respect to the shift path. In the figure, 11, 12...logic circuit, 1
3, 50, 52, 55...memory circuit, 14, 15...
Data switching circuit, 22... Clock signal, 23... Address counter, 24... Write circuit, 25... Read circuit, 26... Write data supply circuit, 28... Write address selection circuit, 29... Write address storage circuit,
30...Write address decoding circuit, 31...AND circuit,
32... External write address designation signal, 34... Memory cell, 35... Read address selection circuit, 36... External read address designation signal, 37... Read address decoding circuit, 39... Output buffer circuit, 40... Data output terminal , 41...Write data selection circuit, 42...
Write data storage circuit, 43... External write data signal, 44, 53, 56, 57... Shift input data, 51, 54, 58... Shift output, 80
. . . fixed data signal; 100 . . . state designation signal.

Claims (1)

[Scope of Claims] 1. Storage means for storing data; State specification means for specifying whether the storage means should be used in a normal state, a shifted state, or an initialized state; and the state specification means. an address counter whose contents are incremented in synchronization with a clock signal when either one of the shift state and the initialization state is designated, and a write provided externally when the normal state is designated by the state designation means. writing means for writing write data into a storage location of the storage means determined by an output signal of the address counter when one of the shift state and the initialization state is designated by the address signal; and the state designation means. reading means for reading data from a corresponding storage location of the storage means determined by a read address signal externally applied when a normal state is designated and by an output signal of the address counter when a shift state is designated; When the normal means is specified by the state specifying means, the data given from the outside is specified, and when the shift state is specified, the data read out by the reading means and shifted by 1 bit and the input data shifted by 1 bit from the outside are also specified to the initialize state. write data supply means for supplying predetermined data as write data to the storage means when the write data is written to the storage means. 2. When either the normal state or the initialized state is specified by the state specifying means, the data given from the outside is used, and when the shift state is specified, the data read out by the reading means and shifted by 1 bit and the 1 bit from the outside are used. 2. The storage circuit according to claim 1, further comprising write data supply means for supplying bit shift input data to the storage means as write data.