JP2002197900A - Semiconductor integrated circuit, and memory test method for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory test method for a semiconductor integrated circuit in which a testing cost is reduced without providing an exclusive circuit for a memory test to perform a self-test of a memory incorporated in a semiconductor integrated circuit. SOLUTION: This is a method for testing a memory of a semiconductor integrated circuit including a memory and an FPGA(field programmable gate array), the method comprises a step 201 in which constitution is switched so as to load a circuit to the FPGA, a step 202 in which a circuit performing a self-test of a memory is loaded to the FPGA, a step 203 in which signal connection circuit constitution for performing a self-test is changed, and a step 204 in which a self-test of a memory is performed based on a circuit performing a loaded self test.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technique for testing a memory built in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art As a test method of a memory built in a semiconductor integrated circuit, a self-test test method is used. It has a built-in circuit that automatically generates the address and data of the target memory, generates a pattern from that circuit during the memory test mode, inputs the pattern to the memory, and compares the input pattern with the output result in that circuit. And outputting the compared test results to the outside of the integrated circuit. When this method is used, it is possible to obtain the effect that the speed of the memory test can be increased and the number of pins required for the test can be reduced.

[0003]

However, in the above-mentioned conventional method, a circuit dedicated to a memory test is required, that is, a chip area is increased by a circuit which can be said to be unnecessary for processing which the integrated circuit should perform. There was a problem. In particular, when a plurality of memories having different configurations are included, different self-test circuits are required, so that many circuits only for testing are required, and the chip area is increased and the cost is increased. was there.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to maintain the effects of increasing the speed and reducing the number of pins in a self-test of a memory built in a semiconductor integrated circuit. It is an object of the present invention to provide a low-cost semiconductor integrated circuit and a memory test method thereof without providing a dedicated test circuit.

[0005]

In order to achieve the above object, a first memory test method for a semiconductor integrated circuit according to the present invention comprises a semiconductor integrated circuit including a memory and a field programmable gate array (FPGA). A method of switching to a configuration for loading a circuit into an FPGA, a step of loading a circuit for performing a self-test of a memory on the FPGA, and a change of a signal connection circuit configuration for performing a self-test. Performing a self-test of the memory based on the loaded circuit for performing the self-test.

In order to achieve the above object, in a first semiconductor integrated circuit according to the present invention, a memory and a circuit for a normal operation are loaded when performing a normal operation, and a memory is loaded when performing a memory test. A field programmable gate array (FPGA) into which a memory test circuit is loaded, and an access signal from a block that accesses the memory during normal operation, and an access signal from the FPGA during a memory test. , A memory access switching circuit for switching an access signal path between a normal operation and a memory test, an external connection switching circuit for switching a connection to an external terminal between a normal operation and a memory test, and a memory access switching Mode signal generation circuit for generating a mode signal for controlling the circuit and the external connection switching circuit. Characterized by comprising and.

According to the first memory test method and the first semiconductor integrated circuit, at the time of a memory test, a memory self-test circuit is loaded on an FPGA built in the semiconductor integrated circuit, and at the time of normal operation, By loading and configuring the normal operation circuit from the outside on the FPGA, unnecessary circuits dedicated to the memory test can be eliminated, and the chip area can be reduced and the cost can be reduced. .

In order to achieve the above object, a second semiconductor integrated circuit according to the present invention is provided with a memory and a normal access signal from a block accessing the memory during normal operation. Is a field in which a circuit for normal operation is loaded and a memory is accessed by a normal access signal, and a memory test circuit is loaded and a memory is accessed by an access signal from the memory test circuit when performing a memory test.・
A programmable gate array (FPGA); an external connection switching circuit for switching a connection to an external terminal between a normal operation and a memory test; and a mode signal generating circuit for generating a mode signal for controlling the external connection switching circuit. It is characterized by having.

According to the second semiconductor integrated circuit, it is possible to construct a minimum circuit configuration in accordance with each operation mode, thereby further reducing the chip area.
It becomes possible to realize high-speed memory access during normal operation.

In order to achieve the above object, a second memory test method for a semiconductor integrated circuit according to the present invention comprises a memory and a field programmable gate array (FPG).
A) The method for testing the memory of a semiconductor integrated circuit including the method of (A), comprising:
Switching to a configuration for loading a circuit into the FP;
Loading a circuit for performing a self-test of the memory from the storage circuit into a GA; changing a signal connection circuit configuration for performing a self-test; and performing a self-test of the memory based on the loaded circuit for performing the self-test. And performing the steps of:

In order to achieve the above object, in a third semiconductor integrated circuit according to the present invention, a memory and a circuit for a normal operation are loaded when performing a normal operation, and a memory test is performed when performing a memory test. Programmable Gate Array (FP) loaded with circuits for
GA), a storage element for holding circuit information related to a memory test circuit, and an access signal from a block accessing the memory during normal operation, and an access signal from an FPGA during a memory test. A memory access switching circuit for switching a path of an access signal between a normal operation and a memory test;
When performing normal operation on the GA, select a path on which a circuit for normal operation is loaded via an external terminal,
When performing a memory test, a path on which the memory test circuit is loaded is selected based on circuit information from a storage element, and an FPGA is used during normal operation and during memory test.
An external connection switching circuit that switches a load path to the external connection terminal and a connection to an external terminal, a memory access switching circuit, and a mode signal generation circuit that generates a mode signal for controlling the external connection switching circuit. .

According to the second memory test method and the third semiconductor integrated circuit, the self-test circuit data of the memory is held in the non-volatile memory which is a built-in storage element, so that the load to the FPGA can be performed at high speed. In addition to this, it becomes possible to execute the loading to the FPGA without using the external terminal, and it is possible to perform another test using the external terminal in parallel during the loading. As a result, it is possible to shorten the entire test time of the semiconductor integrated circuit.

In order to achieve the above object, a fourth semiconductor integrated circuit according to the present invention includes a CPU, a CPU memory used by the CPU, and a circuit for normal operation when performing normal operation, When a memory test is performed, a memory test circuit is loaded. The memory test circuit includes a field programmable gate array (FPGA) for directly accessing a CPU memory via the CPU from the memory test circuit. CPU
For a memory, an address signal from an internal address generation circuit is selected during normal operation, and F is selected during a memory test.
A selection circuit for selecting an address signal from the PGA is provided.

According to the fourth semiconductor integrated circuit, the CP
In the self test of the memory accessed by U, the CPU
By switching between the memory test path and the normal operation path internally, a circuit configuration that prioritizes normal operation can be taken.As a result, the self-test mechanism can be implemented without deteriorating performance during normal operation. It can be realized.

In order to achieve the above object, in a fifth semiconductor integrated circuit according to the present invention, a plurality of memories and a circuit for a normal operation are loaded when performing a normal operation, and a memory test is performed when performing a memory test. Selecting a field programmable gate array (FPGA) into which a memory test circuit is loaded and an access signal from a block that accesses the memory during normal operation for each of the plurality of memories; Sometimes FPGA
Memory access switching circuits that switch the access signal path between normal operation and memory test by selecting an access signal from the external device, and external connection switching that switches the connection to external terminals during normal operation and memory test And a mode signal generating circuit for generating a mode signal for controlling the memory access switching circuit and the external connection switching circuit.

According to the fifth semiconductor integrated circuit, even in a semiconductor integrated circuit including a plurality of memories, one FP can be used.
All self-test circuits can be realized in the GA area, and the effect of reducing unnecessary circuits during normal operation increases.

The fifth semiconductor integrated circuit includes a storage element for holding circuit information relating to a memory test circuit for a plurality of memories. At the time of the memory test, an external connection switching circuit transmits the memory test signal from the storage element to the FPGA. It is preferable that the storage element sequentially switches to the path for loading the circuit, and the storage element sequentially loads a memory test circuit into the FPGA based on the circuit information for each of the plurality of memories.

According to this configuration, the self-test circuit data of the plurality of memories is held in the non-volatile memory which is a built-in storage element, so that the loading to the FPGA can be performed at a high speed and the external terminal , It is possible to execute loading to the FPGA without using any other device, and it is possible to perform other tests using external terminals in parallel during the execution of loading. As a result, when there are a plurality of memories, the total test time of the semiconductor integrated circuit can be further reduced. Further, the memory for performing the self-test has a non-volatile memory that holds a minimum necessary circuit data for performing the self-test, and when performing a test of a certain memory, first, the circuit data for performing the self-test of the target memory in the FPGA And performs a memory test using the circuit on the FPGA. After the self-test for the target memory is completed, the circuit data for performing the self-test on the next target memory is loaded and the next self-test is performed. Perform a test. These operations are sequentially repeated so that a self-test of all memories can be performed.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) First, a first embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a block diagram showing a configuration example of the semiconductor integrated circuit according to the first embodiment of the present invention.

In FIG. 1, reference numeral 101 denotes a memory (RA
M), 102 are field programmable gates
An array (FPGA), 103 is a memory access switching circuit for switching an access signal to the memory 101 in a normal operation and a memory test, 104 is a memory access block in a normal operation, and 105 is an external connection for switching a connection to an external terminal. A switching circuit 106 is a mode signal generation block that generates a mode signal for controlling the memory access switching circuit 103 and the external connection switching circuit 105.

Reference numeral 111 denotes an access signal from the FPGA 102 to the memory 101, reference numeral 112 denotes an access signal from the memory access block 104 to the memory 101 during normal operation, and reference numeral 113 denotes a connection signal between the FPGA 102 and an external terminal. And 114 is a mode signal.

FIG. 2 is a flowchart showing a processing procedure in the memory test method according to the present embodiment.

In FIG. 2, reference numeral 201 denotes a step of switching a load mode to the FPGA 102 to a load mode for a memory test; 202, a step of loading a circuit for self-test on the FPGA 102; 203, a step of switching to a self-test mode; A step of executing a self-test of the memory 101 by the use circuit; a step 205 of switching a load mode to the FPGA 102 to a load mode for normal operation;
Is a step of loading a circuit for normal operation into the FPGA 102.

Next, the memory test method according to the present embodiment will be specifically described with reference to FIGS.

First, the signal connection to the external terminal is switched from the signal connection to another internal circuit to the signal connection to the FPGA 102 by the external connection switching circuit 105 (step 201).

Next, a self-test circuit is loaded into the FPGA 102 from an external terminal (step 202).

Next, a memory test mode is set, and the memory access switching circuit 103 switches the access signal 112 from the memory access block 104 during normal operation to the access signal 111 from the FPGA 102 for the memory 101. External connection switching circuit 10
5, the signal connection to the external terminal is switched to be connected to the signal group used in the self test (step 203).

Next, the FPGA is connected via an external connection signal.
The self-test circuit configured on the memory 102 is controlled, the self-test of the memory 101 is executed, and the test result is output to the outside through the connection signal 113 (step 20).
4).

After the memory test is completed, the external connection switching circuit 105 switches the connection to load the normal operation circuit from the outside to the FPGA 102 (step 205), and loads the normal operation circuit into the FPGA 102 (step 205). Step 206).

Thereafter, the external connection switching circuit 105
The signal connection to the external terminal is switched to the state of the normal operation, and the memory access switching circuit 103
The access signal 111 from the FPGA 102 is transmitted to the memory 101 in the memory access block 10 during normal operation.
4 to the access signal 112.

With the above processing, the self-test can be performed without the dedicated circuit for the self-test of the memory 101 resident in the integrated circuit.

Next, a modification of this embodiment will be described with reference to FIG.
This will be described with reference to FIG. 3 to 5, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 3 is a block diagram showing a modification of the present embodiment.

As shown in FIG. 3, in this modification, the memory access switching circuit 103 is deleted, and the access signal 112 from the memory access block 104 during normal operation is provided.
Is input to the FPGA 302, and the memory 101 is accessed by the access signal 311 from the memory access block 104 via the FPGA 302 during the normal operation.

FIG. 4 is a block diagram showing a circuit configured on the FPGA 302 during normal operation. In FIG. 4, reference numeral 307 denotes a normal operation circuit block configured on the FPGA 302;
2, a circuit capable of directly connecting the access signal 112 from the memory access block 104 during normal operation to the access signal 311 to the memory 101 in addition to the circuit block 307 for normal operation is configured.

FIG. 5 shows the FPGA 302 during the memory test.
It is a block diagram which shows the circuit comprised above. In FIG. 5, reference numeral 308 denotes a circuit block for self-test configured on the FPGA 302, and a circuit capable of directly accessing the memory 101 from the circuit block for self-test 308 at the time of a memory test.

According to this modification, the memory 101 can be directly accessed without the memory access switching circuit 103 during the normal operation and the memory test, so that the access time to the memory 101 can be prevented from increasing. Becomes

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. In FIGS. 6 and 7, the same components and steps as those in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof will be omitted.

FIG. 6 is a block diagram showing a configuration example of a semiconductor integrated circuit according to the second embodiment of the present invention. FIG.
As shown in (1), this embodiment differs from the first embodiment in that a nonvolatile memory 601 (storage element) for storing circuit information relating to a self-test circuit of the memory 101 is provided.

FIG. 7 is a flowchart showing a processing procedure in the memory test method according to the present embodiment.

In FIG. 7, reference numeral 701 denotes a first load mode switching step for the FPGA 102, reference numeral 702 denotes a step of loading circuit information of a self-test circuit from the nonvolatile memory 601 to the FPGA 102, and reference numeral 703 denotes an FPGA
This is a second load mode switching step for the CPU 102.

Next, the memory test method according to the present embodiment will be specifically described with reference to FIGS.

First, in the first load mode, the external connection switching circuit 105 switches the external signal connection of the FPGA 102 to a signal connection required for loading from the nonvolatile memory 601 to the FPGA 102 (step 70).
1).

Next, from the nonvolatile memory 601 to the FPGA
The self-test circuit of the memory 101 is loaded into the memory 102 (step 702).

Thereafter, switching to the self-test mode (step 203) and execution of the self-test (step 204) are performed in the same manner as in the first embodiment.

After the memory test is completed, the external connection switching circuit 105 sets the FPG to the second load mode.
A102 external signal connection from external terminal to FPGA10
The connection is switched to the signal connection required for loading to the FPGA 2 (step 703), and the normal operation circuit is loaded to the FPGA 102 (step 206).

As described above, according to the present embodiment, by providing the nonvolatile memory 601 for storing the circuit information relating to the self-test circuit of the memory 101, the external memory can be used during the loading step from the nonvolatile memory 601 to the FPGA 102. Control using terminals is not required, and tests other than the memory test can be easily performed in parallel.

In this embodiment, as a modification similar to the first embodiment, the same effect can be obtained by using a circuit configuration for performing memory access during normal operation via the FPGA. It is.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIG.

FIG. 8 is a block diagram showing a configuration example of a semiconductor integrated circuit according to the third embodiment of the present invention. In FIG. 8, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In FIG. 8, reference numeral 802 denotes an FPGA;
Is a signal connected to the CPU 807 to access the memory 101 from the FPGA 802, and 812 is an access signal from the CPU 807 to the memory 101.

The processing procedure in the memory test method according to the present embodiment follows the procedure of the flowchart in FIG.

Next, the memory test method according to the present embodiment will be specifically described with reference to FIGS.

First, the step 201 for switching the load mode to the FPGA 802 to the memory test and the FPG
Step 20 for loading a circuit for self-test into A802
Step 2 is performed in the same manner as in the first embodiment.

Next, in step 203 of switching the memory 101 to the self-test mode, the memory access circuit inside the CPU 807 is switched to a signal from the FPGA 802. Subsequent steps 204 to 206 are the same as in the first embodiment.

Hereinafter, the circuit configuration inside the CPU 807 will be described with reference to FIGS. 9 and 10.

FIG. 9 is a diagram showing a schematic configuration example of an address generation circuit for a conventional memory. In FIG. 9, addresses are generated by registers 901, 902, and 903. The values of registers 901 and 902 are processed by combinational circuits 904 and 905, respectively, and ALU
An operation is performed at 906 to generate an address. On the other hand, for the register 903, the register value is used as an address as it is. As the address to the memory 101, either the address from the ALU 906 or the address from the register 903 is selected and used by the selector 907.

In the case of the address generation circuit having such a configuration, the path from the register 901 or 902 becomes a critical path. Such a CPU has an FPGA 80
When a circuit for selecting the path from the path 2 is inserted, if it is inserted on the memory 101 side rather than the selector 907, the critical path will be further delayed, and the performance of the CPU will be degraded.

Therefore, as shown in FIG. 10, the selector 1010 is provided to the register 903 having a sufficient timing.
(Selection circuit) is inserted so that the access signal 1008 from the FPGA 802 can be selected. At this time, F
A mode signal for selecting a signal from PGA 802 controls both selectors 907 and 1010.

As described above, according to the present embodiment, the CP
The access from the U807 to the memory 101 can be realized by a circuit that gives priority to the access during the normal operation. Therefore, it is easy to guarantee high-speed access from the CPU 807 to the memory 101.

The signal for connecting the FPGA 802 and the CPU 807 may be dedicated to the memory test, or may be shared with the signal line used during normal operation. Further, it is possible to combine this embodiment with a nonvolatile memory for storing circuit information of a self-test circuit as in the second embodiment, and in that case, the effects of both embodiments can be obtained simultaneously. Will be possible.

The FPGA according to the embodiment of the present invention
May have any configuration as long as it has the ability to be rewritten a plurality of times. When there are a plurality of memories, a plurality of memory access switching circuits having the same configuration are provided, or an access signal from a block for accessing each memory is connected to the FPGA, and access is switched by a mode signal generation circuit. Thus, it is possible to deal with a plurality of memories.

In this case, the memory for performing the self-test has a non-volatile memory which holds the minimum necessary circuit data for performing the self-test.
The PGA is loaded with circuit data for performing a self test of the target memory, a memory test is performed using the circuit on the FPGA, and after the self test for the target memory is completed, the self test of the next target memory is performed. Load the circuit data to be tested and perform the next self test. By repeating these steps sequentially, the self-test of all memories can be performed.

[0066]

As described above, according to the present invention,
During the memory test, the FPG built in the semiconductor integrated circuit
Load and configure the memory self-test circuit on A,
At the time of normal operation, by loading a circuit for normal operation from the outside on the FPGA and configuring it, unnecessary circuits dedicated to the memory test can be deleted, and the chip area can be reduced and cost can be reduced. Will be possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of a semiconductor integrated circuit according to a first embodiment of the present invention;

FIG. 2 is a flowchart showing a processing procedure in a memory test method according to the first embodiment of the present invention;

FIG. 3 is a block diagram showing a modification of the semiconductor integrated circuit according to the first embodiment of the present invention;

FIG. 4 shows the FPG of the semiconductor integrated circuit of FIG. 3 during a normal operation;
FIG. 2 is a block diagram illustrating a circuit configured on the A302.

FIG. 5 is a diagram showing an F of the semiconductor integrated circuit of FIG. 3 during a memory test;
FIG. 2 is a block diagram showing a circuit configured on the PGA 302

FIG. 6 is a block diagram showing a configuration example of a semiconductor integrated circuit according to a second embodiment of the present invention;

FIG. 7 is a flowchart showing a processing procedure in a memory test method according to the second embodiment of the present invention;

FIG. 8 is a block diagram showing a configuration example of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 9 is a schematic configuration diagram of an address generation circuit built in a conventional CPU.

FIG. 10 is a configuration diagram of an address generation circuit and a selector circuit 1010 built in the CPU 807 of FIG. 8;

[Explanation of symbols]

Reference Signs List 101 memory 102, 302, 802 FPGA 103 memory access switching circuit 104 memory access block during normal operation 105 external connection switching circuit 106, 306 mode signal generation circuit 111 access signal from FPGA 102 to memory 101 112 memory access block during normal operation Access signal from 104 113 Connection signal between FPGA 102 and external terminal 114 Mode signal 201 Step of switching load mode to FPGA to memory test 202 Step of loading circuit for self-test to FPGA 203 Step of switching to self-test mode 204 Self-test execution step of memory 205 Step of switching load mode to FPGA to normal operation 206 Loading step of normal operation circuit to FPGA 60 Non-Volatile Memory (Storage Element) 701 First Load Mode Switching Step for FPGA 702 Step of Loading Circuit Information of Self-Test Circuit from Non-Volatile Memory to FPGA 703 Second Load Mode Switching Step for FPGA 807 CPU 1010 Selector ( Selection circuit)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 15/78 510 G01R 31/28 W (72) Inventor: Mitsuhiko Aiba 1006 Odakadoma, Kadoma, Osaka Matsushita Electric Within Sangyo Co., Ltd. Person Junya Yamamoto 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture F-term in Matsushita System Techno Co., Ltd.

Claims (8)

[Claims] A memory and a field programmable device
A method for testing the memory of a semiconductor integrated circuit including a gate array (FPGA), comprising: switching to a configuration for loading a circuit on the FPGA; and loading a circuit for performing a self-test of the memory on the FPGA. A step of changing a signal connection circuit configuration for performing the self-test, and a step of self-testing the memory based on the loaded circuit for performing the self-test. Test method. 2. A memory, a field programmable gate array (FPGA) into which a circuit for normal operation is loaded when performing a normal operation, and a circuit for memory test is loaded when performing a memory test. For the memory, an access signal from a block accessing the memory is selected during a normal operation, and an access signal from the FPGA is selected during a memory test. A memory access switching circuit for switching a path, an external connection switching circuit for switching a connection to an external terminal between a normal operation and a memory test, and a mode for generating a mode signal for controlling the memory access switching circuit and the external connection switching circuit A semiconductor integrated circuit, comprising: a signal generation circuit. 3. A memory and a normal access signal from a block that accesses the memory during a normal operation are input. When performing a normal operation, a circuit for a normal operation is loaded and the normal access signal is supplied by the normal access signal. When a memory is accessed and a memory test is performed, a memory test circuit is loaded and a field programmable gate array (FPGA) for accessing the memory by an access signal from the memory test circuit; A semiconductor integrated circuit, comprising: an external connection switching circuit that switches a connection to an external terminal between a time and a memory test; and a mode signal generation circuit that generates a mode signal for controlling the external connection switching circuit. 4. A memory and a field programmable device.
A method for testing the memory of a semiconductor integrated circuit including a gate array (FPGA), comprising: switching to a configuration in which a circuit is loaded from a storage element in the semiconductor integrated circuit to the FPGA; Loading a circuit for performing a self-test from the storage circuit; changing a signal connection circuit configuration for performing the self-test; and performing a self-test on the memory based on the loaded circuit for performing the self-test. And a memory test method for a semiconductor integrated circuit. 5. A memory and a field programmable gate array (FPGA) loaded with a circuit for a normal operation when performing a normal operation and loaded with a circuit for a memory test when performing a memory test. A memory element for holding circuit information relating to the memory test circuit; an access signal from the block accessing the memory during normal operation; and an access signal from the FPGA during memory test. A memory access switching circuit for selecting and switching an access signal path between a normal operation and a memory test; and a circuit for the normal operation via an external terminal when performing a normal operation on the FPGA. When selecting a path to be loaded and performing a memory test, the memory element performs An external connection switching circuit that selects a path on which the memory test circuit is loaded based on the information, switches a load path to the FPGA and switches a connection to the external terminal between a normal operation and a memory test. A semiconductor integrated circuit, comprising: a mode signal generation circuit that generates a mode signal for controlling the memory access switching circuit and the external connection switching circuit. 6. A CPU, a CPU memory used by the CPU, a circuit for a normal operation is loaded for performing a normal operation, and a circuit for a memory test is loaded for performing a memory test. A field programmable gate array (FPGA) for directly accessing the CPU memory from the memory test circuit via the CPU, wherein the CPU has an internal address for the CPU memory during normal operation. A semiconductor integrated circuit comprising: a selection circuit that selects an address signal from a generation circuit and selects an address signal from the FPGA during a memory test. 7. A field programmable gate array (FPGA) in which a plurality of memories and a circuit for normal operation are loaded when performing a normal operation, and a circuit for memory test is loaded when performing a memory test. ), For each of the plurality of memories, select an access signal from a block that accesses the memory during normal operation, select an access signal from the FPGA during a memory test, A plurality of memory access switching circuits for switching a path of an access signal between a memory test and an external connection switching circuit for switching a connection to an external terminal between a normal operation and a memory test; the memory access switching circuit and the external connection switching A mode signal generation circuit for generating a mode signal for controlling the circuit. The semiconductor integrated circuit, characterized in that. 8. The semiconductor integrated circuit includes a storage element for holding circuit information relating to the memory test circuit for the plurality of memories, and at the time of a memory test, the external connection switching circuit is configured to store the information from the storage element to the FPGA.
8. A path for loading the circuit for memory test is switched to a path for loading the circuit for memory test, and the storage element sequentially loads the circuit for memory test into the FPGA based on the circuit information for each of the plurality of memories. A semiconductor integrated circuit as described in the above.