CN102288870A - Testing method for FPGA (field programmable gate array) single long wire and directly connected switch - Google Patents
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Abstract
The invention relates to a testing method for FPGA (field programmable gate array) single long wires and directly connected switches based on a Virtex structure, which comprises four configuration steps. The invention has the advantages that: the shift register chain mode is adopted to test 24 single long wires of an FPGA circuit, and bridging faults between signals of any two of the 24 wires in one group can be tested; the single long wires and directly connected switches of all CLBs (configurable logic blocks) can be tested only with four configuration codes; the testing process is simplified and the user operation is facilitated through initial configuration of the Blockram; the faults can be accurately positioned, four configuration steps are included, and when the deviation of the CLB positions in the last two configuration step is 4, the faults can be accurately positioned for the directly connected switches or single long wires of four CLBs; and when the fault positioning requirements are extremely accurate, the deviation of the CLB positions can be defined as 1, two configuration steps in total are adopted, and the fault can be accurately positioned for the directly connected switch or single long wire corresponding to one specific and unique CLB.
Description
Technical field
The present invention relates to a kind of FPGA method of testing based on the Virtex framework, specifically is the method for testing of single long line of a kind of FPGA and direct-connected switch thereof.
Background technology
But the FPGA based on the Virtex framework is the VLSI (very large scale integrated circuit) chip of the huge miscellaneous overprogram of a kind of interconnection resource quantity.Therefore, in the practical application of FPGA, fault betides the probability of interconnect resource much larger than the probability that betides other logic function.
At present, domestic and international known FPGA wiring switch testing technology generally all is conceived to small-scale cloth wiretaps such as 3x3,4x4; And present commercial FPGA adopts the cloth wiretap of 24x24 more, in addition because in the test job of FPGA product, the quantity of configuration code is the key parameter that influences test period, so how to use the least possible configuration code to finish the single long line wiring of above-mentioned FPGA product and the test of switch thereof, significant for the application of FPGA product with test.
Though have so-called four times, six times configurations to finish the method for FPGA interconnect resource test both at home and abroad, said method is all realized based on interconnect resources model simple in structure on the one hand; Owing to do not introduce flop signal in the test process, cause interconnection resource interconnection progression long, and be unfavorable for localization of fault on the other hand; And clear and definite available detection means is not proposed yet for contingent bridge joint class fault model between the wiring path.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, develop the least possible method of testing of a kind of configured number based on single long line of 24 * 24 scale FPGA of Virtex framework and direct-connected switch thereof, only just finish with four configurations, fault coverage reaches 100% and accurately fault location position and type.
According to technical scheme provided by the invention, the method for testing of single long line of described FPGA and direct-connected switch thereof is finished based on the single long line of FPGA of Virtex framework and the test of direct-connected switch thereof by four configurations; Configuration for the first time comprises the steps:
11) by two Blockram of left side top with a reading mode, export 24 DO signals according to the result of address counter, be connected among first group of CLB; Described first group of CLB is meant 4 CLB of preceding four row of FPGA first row;
12) among the described first group of CLB of step 11), sequence number is that the DO signal of odd number is connected into trigger, and sequence number is that the DO signal of even number is connected into combinational logic, and final 24 signals are respectively via the OMUX output of 4 CLB correspondences of first group, 6 signals of each OMUX output;
13) with the direct-connected switching gate of level between the single long line of 24 levels of the described first group of CLB output of step 11) and the second group of CLB; Described second group of CLB is meant 4 CLB on the described first group of CLB of step 11) the right;
14) when 24 signals enter the IMUX of the described second group of CLB correspondence of step 13), with the signal and the even bit exchange of odd bits;
15) according to step 12), 13), 14) circulation carries out finishing until first row, changes next line then over to, the employing serpentine pathway is carried out between row and the row;
16) initial value of Blockram need be set by following requirement, under the situation of guaranteeing to increase progressively continuously in the address, 24 transmission signals waveform unanimities, but clock period at interval between the adjacent signals, and all occur successively between any two among these 24 signals 00,01,11, four kinds of relations of 10};
The direct-connected switch of level is meant level direct-connected switch from left to right in the described step 13);
Cascade mode in the described step 15) between row and the row is end to end, and its snakelike test access covers all the single long line of all levels and direct-connected switches thereof except that the CLB that drives as single long line in order;
Configuration for the second time comprises the steps:
21) by two Blockram of left side top with a reading mode, export 24 DO signals according to the result of address counter, be connected among first group of CLB; This time described first group of CLB is 4 CLB of four lines before FPGA first is listed as;
22) step 21) among described first group of CLB, sequence number is that the DO signal of odd number is connected into trigger, and sequence number is that the DO signal of even number is connected into combinational logic, and final 24 signals are respectively via the OMUX output of 4 CLB correspondences of first group, 6 signals of each OMUX output;
23) with step 21) vertical direct-connected switching gate between 24 vertical single long lines of described first group of CLB output and the second group of CLB; This time described second group of CLB is meant step 21) 4 CLB of described first group of CLB below;
24) enter step 23 at 24 signals) during the IMUX of described second group of CLB correspondence, the signal and the even bit of odd bits exchanged;
25) according to step 22), 23), 24) circulation carries out finishing until first row, changes next column then over to, the employing serpentine pathway is carried out between row and the row;
26) initial value of Blockram need be set by following requirement, under the situation of guaranteeing to increase progressively continuously in the address, 24 transmission signals waveform unanimities, but clock period of interval between the adjacent signals; And all occur successively between any two among these 24 signals 00,01,11, four kinds of relations of 10};
Configuration for the third time, with 4 row that move right successively of the CLB position in the configuration for the first time, all the other steps are constant;
The 4th configuration, successively to moving down 4 row, all the other steps are constant with the CLB position in the configuration for the second time.
The step 11) of described first time of configuration and the step 21 of configuration for the second time) in Blockram with a reading mode, export 24 DO signals according to the result of address counter, be connected among first group of CLB.
The step 12), 14 of described first time of configuration) and the step 22 that disposes for the second time), 24) in DO signal odd even characteristic in regular turn number, be divided into two groups, be connected into the trigger of first group of CLB inside and the trigger of second group of inside separately respectively, and with this take turns change enter trigger the form continuity until last group CLB.
Advantage of the present invention is:
1) with 24 single long lines of shift register chain pattern test FPGA circuit, can test 24 is bridging fault between any 2 signals of singly long line of one group;
2) only can test single long line and the direct-connected switch thereof of all CLB with four sections configuration codes;
3) by the initial configuration of Blockram, simplify testing process, be convenient to user's operation;
4) localization of fault is accurate, in fact adopts four configurations, and back twice configuration CLB positional offset amount is that localization of fault can be accurate to direct-connected switch or the single long line of four CLB under 4 the situation; Require under the extreme accurate situation (for example need carry out fault analysis) in localization of fault certain batch failure chip, the CLB positional offset amount can be defined as 1, amount to and adopt ten configurations, localization of fault can be accurate to direct-connected switch or single long line of concrete well-determined CLB correspondence.
Description of drawings
Fig. 1 is the single long line test one-piece construction synoptic diagram of level.
Fig. 2 is that the single long line of level is tested the concrete structure synoptic diagram from left to right.
Fig. 3 is a CLB internal circuit schematic diagram.
Fig. 4 is test circuit gate leve simulation waveform figure.
Embodiment
The invention will be further described below in conjunction with drawings and Examples.The objective for implementation of this method of testing is based on the Virtex of Xilinx company
TMAny FPGA of system architecture.FPGA based on this framework generally includes: embedded block storage (Blockram), input-output unit able to programme (Input/Output Block, IOB), a large amount of programmable logic cells (Configurable Logic Block, CLB) and the programmable interconnect resource, the FPGA interconnect resource of classical symmetrical expression comprises interconnection switches box (Switch Box, SB), input switch box (Input Mux, IMUX), output switch enclosure (Output Mux, OMUX), IOB module switch box, and interconnect line segment (specifically comprises single long line, six long lines, long line, resources such as tristate bus line).
Fig. 1,2 are depicted as the Virtex based on Xilinx company
TMThe fpga logic structural representation of system architecture, comprise among the figure: IOB 1, the input switch box 2 of IOB, the interconnection switches box 3 of IOB, CLB 4, the input switch box (IMUX) 5 of CLB, the output switch enclosure (OMUX) 6 of CLB, the Slice0 7 of CLB, the Slice1 8 of CLB, the interconnection box box (SB) 9 of CLB.Based on the FPGA of above-mentioned framework, the physical location of IOB is distinguished called after TCi, BCi, RRi, LRi according to top layer, bottom, right side, left side, i=1, and 2,3 ...Wherein C represents row, and R represents row.Corresponding 2 IOB of each switch enclosure of top layer, bottom, corresponding 3 IOB of each switch enclosure in right side, left side.The cloth wiretap of each CLB module correspondence is labeled as CLB_RxCy by the capable y row of x among the figure.
The present invention finishes based on the single long line of FPGA of Virtex framework and the test of direct-connected switch thereof by four configurations.Adopt the topology layout of crawling between single long line test line of level and the row, i.e. odd-numbered line test wiring even number line test from left to right is from the single long line wiring of right-to-left.Every row is inner to be one group with 4 cloth wiretaps, and 6 single long lines of each cloth wiretap output are exported 24 single long lines altogether.Realize the unidirectional test of the single long lines of all levels (24) of corresponding row cloth wiretap.The test of considering cloth wiretap inner horizontal point able to programme can't be tested in 4 CLB of the single long line of output, make and move 4 row behind the layout constraint of this group cloth wiretap admittedly need additionally add a segment encode, thereby guarantee test 100% covering of the single long line and the corresponding transversal switch thereof of horizontal direction.
Concrete steps are as follows.
Configuration for the first time comprises the steps:
11) by two Blockram of left side top with a reading mode, export 24 DO signals according to the result of address counter, be connected among first group of CLB; Described first group of CLB is meant 4 CLB of preceding four row of FPGA first row, i.e. CLB_R1C1, CLB_R1C2, CLB_R1C3, CLB_R1C4;
12) among the described first group of CLB of step 11), sequence number is that the DO signal of odd number is connected into trigger, and sequence number is that the DO signal of even number is connected into combinational logic, and final 24 signals are respectively via the OMUX output of 4 CLB correspondences of first group, 6 signals of each OMUX output;
13) with the direct-connected switching gate of level between the single long line of 24 levels of the described first group of CLB output of step 11) and the second group of CLB; Described second group of CLB is meant 4 CLB on the described first group of CLB of step 11) the right;
14) when 24 signals enter the IMUX of the described second group of CLB correspondence of step 13), with signal and even bit exchange, i.e. CLB_R1C5, CLB_R1C6, CLB_R1C7, the CLB_R1C8 of odd bits;
15) according to step 12), 13), 14) circulation carries out finishing until first row, changes next line then over to, the employing serpentine pathway is carried out between row and the row;
16) initial value of Blockram need be set by following requirement, under the situation of guaranteeing to increase progressively continuously in the address, 24 transmission signals waveform unanimities, but clock period at interval between the adjacent signals, and all occur successively between any two among these 24 signals 00,01,11, four kinds of relations of 10};
The direct-connected switch of level is meant level direct-connected switch from left to right in the described step 13);
Cascade mode in the described step 15) between row and the row is end to end, and its snakelike test access covers all the single long line of all levels and direct-connected switches thereof except that the CLB that drives as single long line in order;
Configuration for the second time comprises the steps:
21) by two Blockram of left side top with a reading mode, export 24 DO signals according to the result of address counter, be connected among first group of CLB; This time described first group of CLB is 4 CLB of four lines before FPGA first is listed as, i.e. CLB_R1C1, CLB_R2C1, CLB_R3C1, CLB_R4C1;
22) step 21) among described first group of CLB, sequence number is that the DO signal of odd number is connected into trigger, and sequence number is that the DO signal of even number is connected into combinational logic, and final 24 signals are respectively via the OMUX output of 4 CLB correspondences of first group, 6 signals of each OMUX output;
23) with step 21) vertical direct-connected switching gate between 24 vertical single long lines of described first group of CLB output and the second group of CLB; This time described second group of CLB is meant step 21) 4 CLB of described first group of CLB below, i.e. CLB_R5C1, CLB_R6C1, CLB_R7C1, CLB_R8C1;
24) enter step 23 at 24 signals) during the IMUX of described second group of CLB correspondence, the signal and the even bit of odd bits exchanged;
25) according to step 22), 23), 24) circulation carries out finishing until first row, changes next column then over to, the employing serpentine pathway is carried out between row and the row;
26) initial value of Blockram need be set by following requirement, under the situation of guaranteeing to increase progressively continuously in the address, 24 transmission signals waveform unanimities, but clock period of interval between the adjacent signals; And all occur successively between any two among these 24 signals 00,01,11, four kinds of relations of 10};
Configuration for the third time, with 4 row that move right successively of the CLB position in the configuration for the first time, all the other steps are constant;
The 4th configuration, successively to moving down 4 row, all the other steps are constant with the CLB position in the configuration for the second time.
The single long line of the level that Figure 2 shows that is tested the concrete structure synoptic diagram from left to right, direct-connected switch 10(Programmable Interconnect Points, PIP) be the programmable interconnect point of direct-connected usefulness, direct-connected switch 10 (particularly just being meant the W0 to E0 in 24 direct-connected switches from left to right) between single long line is made of the SRAM of 2bits, thereby the better driving ability can be provided.Among Fig. 2, Slice1 exports 4 signals, is respectively { S1_Y/S1_YQ/S1_X/S1_XQ} from left to right; Slice0 exports 2 signals, is respectively { S0_X/S0_XQ} from left to right; 6 signals of above-mentioned total export the OMUX of CLB to, change the interconnection switches box of CLB correspondence then over to, reach colleague's next column CLB through single long line.Input signal is { S1_G_B1/S1_BY/S1_F_B1/S1_BX/S0_F_B1/S0_BX } from left to right.
In Fig. 3,6 signals of each CLB output are divided into three groups of (S1_Y/S1_YQ, S0_Y/S0_YQ, S0_X/S0_XQ), show among the figure for two groups of (S0_Y/S0_YQ of Slice0, S0_X/S0_XQ) signal, S0_X and the S0_XQ of CLB wherein, in the process of input right side CLB, adopt the pattern that X connects with XQ rather than X connects with X, thereby cause that output signal is every then accepts trigger actuation once through 2 CLB, generally speaking on macroscopic view, output signal is the result that BRAM output test patterns is exported behind n/2 level shift register.
Figure 4 shows that: the test circuit gate leve simulation waveform figure that with XCV1000 is example, 11, the 15 first section interval that is respectively Blockram output signal DO and test circuit output signal dout among the figure, having the two value of one-period at least between any two signals in this interval is 01; 12,16 is the high cycle of signal among the figure, and all 24 signal values in this clock period are height; 13,17 are the low cycle of signal among the figure, and all 24 signal values in this clock period are low; 14, the 18 second section interval that is respectively DO and dout among the figure, having the two value of one-period at least between any two signals in this interval is 10; 19 is the transmission delay interval among the figure, and this interval size is 96 * 5/2 clock period.Wherein BRAM output data DO imports dout into after 96 * 5/2 grades of chain of registers.As mentioned before, because of chain progression is even number, and the pattern that adopts X to connect with XQ (or Y and YQ), compare dout[0 admittedly export the value of dout with DATA] and DO[1] be one-to-one relationship, and dout[1] and DO[0] be one-to-one relationship, all the other corresponding relation contrast Fig. 4 all can release according to above-mentioned rule.
This test of heuristics resource controllability strong (guarantee the line of every single long line and direct-connected switch is all tested arrive), reusability strong (being applicable to all FPGA) based on the Virtex framework, accurate positioning when breaking down, and can to cover inner 24 of same CLB be one group all fault types (open circuit of stuck-at fault and short circuit and bridge joint class fault) of single long line.
Claims (3)
1. the method for testing of single long line of FPGA and direct-connected switch thereof is characterized in that finishing based on the single long line of FPGA of Virtex framework and the test of direct-connected switch thereof by four configurations; Configuration for the first time comprises the steps:
11) by two Blockram of left side top with a reading mode, export 24 DO signals according to the result of address counter, be connected among first group of CLB; Described first group of CLB is meant 4 CLB of preceding four row of FPGA first row;
12) among the described first group of CLB of step 11), sequence number is that the DO signal of odd number is connected into trigger, and sequence number is that the DO signal of even number is connected into combinational logic, and final 24 signals are respectively via the OMUX output of 4 CLB correspondences of first group, 6 signals of each OMUX output;
13) with the direct-connected switching gate of level between the single long line of 24 levels of the described first group of CLB output of step 11) and the second group of CLB; Described second group of CLB is meant 4 CLB on the described first group of CLB of step 11) the right;
14) when 24 signals enter the IMUX of the described second group of CLB correspondence of step 13), with the signal and the even bit exchange of odd bits;
15) according to step 12), 13), 14) circulation carries out finishing until first row, changes next line then over to, the employing serpentine pathway is carried out between row and the row;
16) initial value of Blockram need be set by following requirement, under the situation of guaranteeing to increase progressively continuously in the address, 24 transmission signals waveform unanimities, but clock period at interval between the adjacent signals, and all occur successively between any two among these 24 signals 00,01,11, four kinds of relations of 10};
The direct-connected switch of level is meant level direct-connected switch from left to right in the described step 13);
Cascade mode in the described step 15) between row and the row is end to end, and its snakelike test access covers all the single long line of all levels and direct-connected switches thereof except that the CLB that drives as single long line in order;
Configuration for the second time comprises the steps:
21) by two Blockram of left side top with a reading mode, export 24 DO signals according to the result of address counter, be connected among first group of CLB; This time described first group of CLB is 4 CLB of four lines before FPGA first is listed as;
22) step 21) among described first group of CLB, sequence number is that the DO signal of odd number is connected into trigger, and sequence number is that the DO signal of even number is connected into combinational logic, and final 24 signals are respectively via the OMUX output of 4 CLB correspondences of first group, 6 signals of each OMUX output;
23) with step 21) vertical direct-connected switching gate between 24 vertical single long lines of described first group of CLB output and the second group of CLB; This time described second group of CLB is meant step 21) 4 CLB of described first group of CLB below;
24) enter step 23 at 24 signals) during the IMUX of described second group of CLB correspondence, the signal and the even bit of odd bits exchanged;
25) according to step 22), 23), 24) circulation carries out finishing until first row, changes next column then over to, the employing serpentine pathway is carried out between row and the row;
26) initial value of Blockram need be set by following requirement, under the situation of guaranteeing to increase progressively continuously in the address, 24 transmission signals waveform unanimities, but clock period of interval between the adjacent signals; And all occur successively between any two among these 24 signals 00,01,11, four kinds of relations of 10};
Configuration for the third time, with 4 row that move right successively of the CLB position in the configuration for the first time, all the other steps are constant;
The 4th configuration, successively to moving down 4 row, all the other steps are constant with the CLB position in the configuration for the second time.
2. the method for testing of single long line of FPGA and direct-connected switch thereof according to claim 1, it is characterized in that the step 11) of described first time of configuration and the step 21 of configuration for the second time) in Blockram with a reading mode, result according to address counter exports 24 DO signals, is connected among first group of CLB.
3. the method for testing of single long line of FPGA and direct-connected switch thereof according to claim 1, the step 12), 14 that it is characterized in that described first time of configuration) and the step 22 that disposes for the second time), 24) in DO signal odd even characteristic in regular turn number, be divided into two groups, be connected into the trigger of first group of CLB inside and the trigger of second group of inside separately respectively, and with this take turns change enter trigger the form continuity until last group CLB.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109444630A (en) * | 2018-11-05 | 2019-03-08 | 西安智多晶微电子有限公司 | FPGA routing cell tests structure and method |
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