CN102323538A - Design method of scanning unit based on partial scanning of improved test vector set - Google Patents
Design method of scanning unit based on partial scanning of improved test vector set Download PDFInfo
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Abstract
The invention discloses a design method of a scanning unit based on partial scanning of an improved test vector set, relating to the technical field of SOC (system-on-a-chip) test of digital integrated circuits, and solving the problems of delayed test, hardware redundancy and large required capacity of a memory in the conventional online test method. The method comprises the following steps of: firstly, obtaining an important equivalent output pin which is important to fault detection by stimulating a fault of an equivalent output pin in a combined part of a sequence circuit; secondly, obtaining the improved test vector set by stimulating a fault of an equivalent input pin in the combined part of the sequence circuit; and finally, according to the improved test vector set and an equivalent output pin which is unimportant to the fault detection, dividing triggers into fixed-input triggers and important triggers, and serially connecting the important triggers to form a partial scanning chain. By the method, the obtained scanning unit has a relatively high fault coverage rate and can reduce the hardware redundancy of a test circuit, the digit of bits of the test vector and the memory space.
Description
Technical field
The present invention relates to digital integrated circuit SOC technical field of measurement and test, be specifically related to the SOC technical field of measurement and test of reusable IP (Intellectual Property) core.
Background technology
Along with the raising of integrated circuit technology, the complication system that is made up of a plurality of chips can be integrated on the chip, and System on Chip/SoC SoC arises at the historic moment.Along with the raising to the chip reliability demand, the SoC measuring technology has obtained extensive studies.
The SoC test can be divided into off-line test and on-line testing.On-line testing is meant that when circuit moves, carrying out physical fault detects.On-line testing seem all the more important reasons mainly contain following some:
At first, in the very high key area of security requirements such as space flight, military affairs, need in work, accomplish test;
The second, on-line testing can ensure the maximum working time of circuit, avoids the work that is interrupted of circuit;
The 3rd, on-line testing is convenient to find the incipient fault of inside circuit, handles as early as possible, reduces economic loss;
The 4th, on-line testing is the basis of follow-up selfreparing work.
According to the difference of logic function, digital circuit is divided into combinational circuit and sequential circuit.Widely used in the system of relative complex is sequential circuit.The feasible on-line testing method of combinational circuit that is applicable to of its distinctive memory function is no longer proved effective.Therefore, sequential circuit on-line testing technical research has crucial meaning.
On-line testing is divided into concurrent test and non-concurrent test.Concurrent test refers to the test process of tested module and the test that system works is carried out simultaneously.Non-concurrent test is meant that total system is in line states, tests to the subsystem of an off-line.
To some problems that run in the on-line testing, the scientific research personnel has carried out positive research work.Scan Design can well realize the ornamental of sequential circuit internal state; (BIST is through improving the on-line testing method that realizes on off-line BIST basis Build-in-Self-Test) to online built-in self-test; Zhang Zhaobo is at document Z.B.Zhang; Z.L.Wang; X.L.Gu, and K.Chakrabarty, " Physical defect model ing for fault insertion in system reliability test; " (system reliability fault inject physical detection model) Proceedings of IEEE International Test Conference.Austin; TX, 2009, proposed a kind of part output pin among the pp.1-10. and reduced redundant on-line testing method through testing circuit; Hussain Al-Asaad is at document A.Hussain and M.Paolo, " Non-concurrent on-line testing via scan chains, " (based on the non-concurrent on-line testing method of scan chain) Proceedings of the IEEE Autotestcon Conference.Anaheim; CA; Sep, 2006, a kind of new scan chain cell has been proposed among the pp.656-662.; Use this unit circuit is carried out Scan Design, can realize the non-concurrent test of sequential circuit.
But the meeting that said method has causes bigger test to postpone, and what have has a bigger hardware redundancy, and test vectors a large amount of in the employed BIST structure also can have certain requirement to the capacity of storer.
Summary of the invention
For test delay, hardware redundancy and the bigger problem of needed memory span that exists in the method that solves existing on-line testing, the present invention proposes a kind of method for designing of scanning element of the part scanning based on the retrofit testing vector set.
The method for designing of the scanning element of the part scanning based on the retrofit testing vector set of the present invention
At first, the method that adopts equivalent output pin to the sequential circuit built-up section to carry out fault simulation is obtained the important equivalent output pin important to fault detect;
Then, adopt the method acquisition retrofit testing vector set that the equivalent input pin of sequential circuit built-up section is carried out fault simulation;
At last, according to the retrofit testing vector set with to the unessential equivalent output pin of fault detect, trigger is divided into decides two types on input trigger and important trigger, and important trigger series connection is formed portion of scan chain.
Said important equivalent output pin is for unessential equivalent output pin; Said unessential equivalent output pin is meant at fault coverage and slightly reduces but still under the satisfactory situation; The equivalent output pin that in fault detect, needn't pay close attention to; The equivalent output pin of this type is defined as unessential equivalent output pin, and then all the other equivalent output pins are died a martyr surely and are important equivalent output pin.
It is said that to decide input trigger be irrelevant trigger, 0 irrelevant trigger and 1 irrelevant trigger.
The notion of described equivalent input pin and equivalent output pin is:
The output of the functional input of circuit and trigger is defined as the equivalence input of built-up section, and the equivalence that the input of the functional output of circuit and trigger is defined as built-up section is exported.In conjunction with the fault simulation technology; Circuit-under-test is analyzed, analyzed the significance level of the corresponding equivalent I/O pin of each trigger respectively, in conjunction with corresponding optimized Algorithm for fault detect; Search out the trigger little to tests affect; The bigger trigger of all the other influences is connected into portion of scan chain, just can effectively reduce the hardware redundancy of on-line testing satisfying under the prerequisite of certain fault coverage.
Said employing is confirmed the unessential equivalent output pin of fault detect the method that the equivalent output pin of sequential circuit built-up section carries out fault simulation; Be meant fault simulation result according to ifq circuit and fault injection back circuit; Obtain the important equivalent output pin important to fault detect, detailed process is:
The first step: in the built-up section circuit of sequential circuit, inject a fault in order;
Second step: to the faulty circuit after this fault of process injection; All test vector input circuits in the existing test set are tested; Detect the state of each equivalent output pin one by one, and the corresponding failure zone bit of this equivalence output pin done following the processing according to the state of each equivalent output pin:
If can detect this fault, corresponding Reflector position 1 that then should the equivalence output pin;
If can't detect this fault, corresponding Reflector position 0 that then should the equivalence output pin;
The 3rd step: the circulation first step and second step, finish up to all faults injections;
The 4th step: all fault flags of each equivalent output pin are done add up, the fault flag that obtains this equivalence output pin add up with;
The 5th step: fault flag is added up and ordering from big to small; The fault flag of maximum is added up and pairing equivalent output pin is elected important equivalent output pin as; Simultaneously, all fault flags that write down this equivalence output pin are 1 fault, and equal zero clearing of fault flag of this fault of expression of all equivalent output pins with other; Then, fault flag that this equivalence output pin is corresponding adds up and puts 0;
The 6th step: the number of faults that fault flag covered of calculating acquired all important equivalent output pins; And according to the corresponding fault coverage of said number of faults calculating acquisition; If said fault coverage meets the requirements of the minimum value of fault coverage, then accomplish obtaining of all important equivalent output pins; Otherwise, return execution in step four.
The process that the method that said employing is carried out fault simulation to the equivalent input pin of sequential circuit built-up section obtains the retrofit testing vector set is:
Adopt original test vector collection to carry out emulation, and be according to the process of simulation result acquisition retrofit testing vector set:
The first step: in order,, calculate then and can survey number of faults with certain position 0 in the original test set;
Second step:, calculate then and can survey number of faults with same position 1;
The 3rd step: calculate certain position 0 that obtains in the above-mentioned test set respectively and put 1 o'clock detected fault coverage of ability;
If be 100%, then the equivalent input pin of this correspondence is irrelevant input, and it is don't-care bit X that test vector is concentrated the data of this position; Execution in step five;
If only putting at 0 o'clock is 100%, then the equivalent input pin of this correspondence is 0 irrelevant input, and it is 0 that test vector is concentrated the state of this position; Execution in step five;
If only putting at 1 o'clock is 100%, then the equivalent input pin of this correspondence is 1 irrelevant input, and it is 1 that test vector is concentrated the state of this position; Execution in step five;
If be not 100% all, carry out next step;
The 4th step: put 0 with put in 1 fault coverage select bigger one,
If this fault coverage is to put 0 o'clock fault coverage, and greater than the significance level quantization scale, it is 0 that test vector is concentrated the state of this position; Execution in step five;
If this fault coverage is to put 1 o'clock fault coverage, and greater than the significance level quantization scale, it is 1 that test vector is concentrated the state of this position; Execution in step five;
The 5th step: circulation is carried out above four steps, and all positions in the original test set of traversal promptly test all equivalent input pins, obtain the retrofit testing vector set.
The significance level quantization scale is when input pin is changed to definite value in a certain position, circuit test system the minimum value of receptible fault coverage.
Select and connect decide input trigger and important trigger according to the retrofit testing vector set, and the important trigger scanning element that ingredient scans that is connected in series.Wherein decide input trigger and comprise irrelevant trigger, 0 irrelevant trigger and 1 irrelevant trigger; Wherein, concentrated don't-care bit, 0 don't-care bit and the pairing trigger of 1 don't-care bit of test vector selected irrelevant trigger, 0 irrelevant trigger and 1 irrelevant trigger respectively for use.
The present invention is divided into d type flip flop and decides input trigger and important trigger; When certain d type flip flop during as equivalence input or equivalent output pin; The corresponding test data that inputs or outputs has played the effect of outbalance to the detection of fault; The present invention is referred to as important trigger with these d type flip flops; Said important trigger adopts SFF to realize also being connected into scan chain, realizes the input of test vector and the output of test response through scanning on the one hand, on the other hand latch cicuit duty in test again.If the equivalent input pin that certain d type flip flop is corresponding is changed to definite value; And do not pay close attention to the state of corresponding equivalent output pin; All can not cause the obvious reduction of fault coverage, the present invention is called this d type flip flop and decides the input d type flip flop, imports d type flip flop surely and only is applied to the circuit operate as normal; Irrelevant with test, therefore needn't be connected into scan chain.
The present invention uses the method for part output pin testing circuit fault specifically to realize; Proposed simultaneously the circuit test vector set is carried out improved method; And the thought of utilization part scanning; Consider the difference of test set, designed the scan chain cell of the part scanning of sequential circuit, and then realized the on-line testing of sequential circuit.
The method for designing of scanning element of the present invention; Can be when reaching than high fault coverage; Reduce test circuit hardware redundancy, shorten test vector figure place, reduce storage space, and make things convenient for test compression and vector to generate, be with a wide range of applications.
Description of drawings
Fig. 1 is for adopting the block diagram of sequential circuit;
Fig. 2 is the sequential circuit block diagram that adopts important trigger according to the invention;
Fig. 3 is an important trigger structure synoptic diagram according to the invention;
Fig. 4 is the important trigger process synoptic diagram when function selector is tested;
Fig. 5 is the important trigger process synoptic diagram when test selector is tested;
Process synoptic diagram when Fig. 6 is important trigger operate as normal;
Fig. 7 is the process synoptic diagram of important trigger when the sequential circuit built-up section is tested;
Fig. 8 is that important trigger carries out the process synoptic diagram of data when moving into or shifting out;
Fig. 9 is the CCL synoptic diagram of sequential circuit;
Clock selecting schematic diagram of mechanism when Figure 10 is non-concurrent test;
Clock selecting schematic diagram of mechanism when Figure 11 is concurrent test.
Figure 12 is the structural representation of embodiment three described irrelevant triggers.
Figure 13 is the structural representation of embodiment four described 1 irrelevant triggers.
Figure 14 is the structural representation of embodiment five described 0 irrelevant triggers.
Figure 15 is the structural representation of the original test circuit described in the embodiment one.
Figure 16 is Figure 15 process embodiment one described method, confirms to simplify the test circuit structure synoptic diagram that obtains afterwards after the important equivalent output pin.
Embodiment
Embodiment one: in the method for designing of the scanning element of the described part scanning based on the retrofit testing vector set of this embodiment,
At first, the method that adopts equivalent output pin to the sequential circuit built-up section to carry out fault simulation is obtained the important equivalent output pin important to fault detect;
Then, adopt the method acquisition retrofit testing vector set that the equivalent input pin of sequential circuit built-up section is carried out fault simulation;
At last, according to the retrofit testing vector set with to the unessential equivalent output pin of fault detect, trigger is divided into decides two types on input trigger and important trigger, and important trigger series connection is formed portion of scan chain.
It is said that to decide input trigger be irrelevant trigger, 0 irrelevant trigger and 1 irrelevant trigger.
Said employing is confirmed the unessential equivalent output pin of fault detect the method that the equivalent output pin of sequential circuit built-up section carries out fault simulation; Be meant fault simulation result according to ifq circuit and fault injection back circuit; Obtain the important equivalent output pin important to fault detect, detailed process is:
The first step: in the built-up section circuit of sequential circuit, inject a fault in order;
Second step: to the faulty circuit after this fault of process injection; All test vector input circuits in the existing test set are tested; Detect the state of each equivalent output pin one by one, and the corresponding failure zone bit of this equivalence output pin done following the processing according to the state of each equivalent output pin:
If can detect this fault, corresponding Reflector position 1 that then should the equivalence output pin;
If can't detect this fault, corresponding Reflector position 0 that then should the equivalence output pin;
The 3rd step: the circulation first step and second step, finish up to all faults injections;
The 4th step: all fault flags of each equivalent output pin are done add up, the fault flag that obtains this equivalence output pin add up with;
The 5th step: fault flag is added up and ordering from big to small; The fault flag of maximum is added up and pairing equivalent output pin is elected important equivalent output pin as; Simultaneously, all fault flags that write down this equivalence output pin are 1 fault, and equal zero clearing of fault flag of this fault of expression of all equivalent output pins with other; Then, fault flag that this equivalence output pin is corresponding adds up and puts 0;
The 6th step: the number of faults that fault flag covered of calculating acquired all important equivalent output pins; And according to the corresponding fault coverage of said number of faults calculating acquisition; If said fault coverage meets the requirements of the minimum value of fault coverage, then accomplish obtaining of all important equivalent output pins; Otherwise, return execution in step four.
The number of faults that fault flag covered that said all that choose detect output pins can meet the requirements of fault coverage, is meant that all that choose detect the fault coverage that number of faults that output pins can detect output reaches system requirements.
The principle that the screening of the described employing method of emulation of this embodiment detects the method for output pin is: to each output pin, calculating it can detected number of faults, by how much sorting of quantity.It is worthy of note that the method for directly getting former outputs of ranking results can not reach best effect.But the result who obtains like this is not necessarily optimum, much is repetition because the detected fault of pin institute ability of former of ranks has.Therefore, after ordering finishes each time, get and to detect the maximum pin of number number of faults; Simultaneously can detected fault will no longer participate in later ordering; In remaining fault, sort next time, so move in circles, till fault coverage reaches requirement.
Adopt the existing method of described method of this embodiment and employing to choose the detection output pin and compare, when choosing the output pin of same number, can obtain higher fault coverage.Detect the minimizing of output pin quantity, can well realize optimization, the time redundancy that reduces to test and the hardware redundancy of response analysis part.
The process that the method that said employing is carried out fault simulation to the equivalent input pin of sequential circuit built-up section obtains the retrofit testing vector set is:
Adopt original test vector collection to carry out emulation, and be according to the process of simulation result acquisition retrofit testing vector set:
The first step: in order,, calculate then and can survey number of faults with certain position 0 in the original test set;
Second step:, calculate then and can survey number of faults with same position 1;
The 3rd step: calculate certain position 0 that obtains in the above-mentioned test set respectively and put 1 o'clock detected fault coverage of ability;
If be 100%, then the equivalent input pin of this correspondence is irrelevant input, and it is don't-care bit X that test vector is concentrated the data of this position; Execution in step five;
If only putting at 0 o'clock is 100%, then the equivalent input pin of this correspondence is 0 irrelevant input, and it is 0 that test vector is concentrated the state of this position; Execution in step five;
If only putting at 1 o'clock is 100%, then the equivalent input pin of this correspondence is 1 irrelevant input, and it is 1 that test vector is concentrated the state of this position; Execution in step five;
If be not 100% all, carry out next step;
The 4th step: put 0 with put in 1 fault coverage select bigger one,
If this fault coverage is to put 0 o'clock fault coverage, and greater than the significance level quantization scale, it is 0 that test vector is concentrated the state of this position; Execution in step five;
If this fault coverage is to put 1 o'clock fault coverage, and greater than the significance level quantization scale, it is 1 that test vector is concentrated the state of this position; Execution in step five;
The 5th step: circulation is carried out above four steps, and all positions in the original test set of traversal promptly test all equivalent input pins, obtain the retrofit testing vector set.
Angle from the test vector collection; If certain state has been changed to definite value; Then from the angle of hardware; The corresponding d type flip flop in this position needn't be connected into scan chain, but only with its with decide input trigger both realize can, that is: adopt 1 irrelevant trigger, 0 irrelevant trigger or the trigger that has nothing to do to replace and get final product.
In this embodiment, the 4th step is similar with the process in the 3rd step, and the 4th to go on foot be to guarantee that fault coverage is under 100% the situation; Cause fault coverage that reduction is arranged slightly; Put 0 with put 1 and all can reduce under the situation of fault coverage, get the highest situation of fault coverage, and if this fault coverage less than the significance level quantization scale; Then the fault input pin of this correspondence is important pin, and test adapts to preserves its duty.
From the characteristics of test vector collection, good multidigit is don't-care bit X in the test set of mintest, and can it doesn't matter with detecting fault for the value of these don't-care bits.Several kinds of the tests that generates by mental ATPG software, though each all is decided to be fixing value, change the value of a certain position in the test vector, can not cause very big influence to fault coverage yet.This part discusses the optimization that how to realize the test vector collection.
In the desirable test set,, so no matter to be from hardware spending if each in several test vectors can be got identical value, testing power consumption, or the angle of the storage of test vector and compression says that very big advantage is all arranged.Therefore, this embodiment carries out corresponding transformation with test set, and test set is applied to the circuit that injects through fault carries out fault simulation, according to simulation result, strives in the situation that does not influence fault coverage, realizes test efficiently.Wherein, after the significance level quantization scale refers to change a certain position in the test set, the minimum value of the fault coverage that can accept.
Using the described method of this embodiment can find some is not very important pin to circuit test; Realize the optimization of test set; Test vector collection after the improvement that obtains carries out fault test; Avoided the frequent saltus step of pin status on the one hand, reduced testing power consumption, laid a good foundation for the follow-up hardware redundancy that reduces on the other hand.
Select and connect decide input trigger and important trigger according to the retrofit testing vector set, and the important trigger scanning element that ingredient scans that is connected in series.Wherein decide input trigger and comprise irrelevant trigger, 0 irrelevant trigger and 1 irrelevant trigger; Wherein, concentrated don't-care bit, 0 don't-care bit and the pairing trigger of 1 don't-care bit of test vector selected irrelevant trigger, 0 irrelevant trigger and 1 irrelevant trigger respectively for use.
So-called part scanning, its basic thought are the part scanning element to be connected into scan chain be used for test.Though this thinking has reduced hardware redundancy, also reduced the controllability and the ornamental of circuit simultaneously, must influence to some extent fault coverage.In order to reduce this influence, in this embodiment, d type flip flop is divided into decides input trigger and important trigger; The scanning d type flip flop is during as equivalence input or equivalent output pin, and the test data that inputs or outputs has played the effect of outbalance to the detection of fault, and these d type flip flops are referred to as important trigger; Said important trigger adopts SFF to realize and be connected into scan chain; Realize on the one hand the input and the output of test response of test vector through scanning, latch cicuit duty in test again on the other hand is if the equivalent input pin of certain d type flip flop correspondence is changed to definite value; And do not pay close attention to the state of corresponding equivalent output pin; All can not cause the obvious reduction of fault coverage, this d type flip flop is called decides the input d type flip flop, imports d type flip flop surely and only is applied to the circuit operate as normal; Irrelevant with test, needn't be connected into scan chain.The structure of the part scanning element that this embodiment obtains is referring to shown in Figure 1; This kind scanning element compare with the scanning element of existing full scan (referring to shown in Figure 2); The scanning element of this embodiment only is connected into scan chain with the part d type flip flop with the SFF replacement, realizes the controllability and the ornamental of location mode through scan_in and scan_out.
According to Figure 15 and Figure 16 the described principle of work of this embodiment is described below, Figure 15 is original test circuit, confirms important equivalent output pin through the fault simulation method of equivalence output; And unessential equivalent output pin is marked at the output terminal of circuit with round dot in Figure 15, and comprising DFF1, DFF2; DFF4, DFF5 concentrates the corresponding equivalent input pin of these four DFF to be changed to corresponding 0 or 1 respectively test vector; Other each equivalent input pin all uses the concentrated data of original test vector, carries out the fault simulation of equivalent input pin, if simulation result shows; DFF1 input was changed to 1 o'clock, and the DFF2 input was changed to 0 o'clock, and the DFF5 input is changed to 1 or at 0 o'clock; Influence to the fault coverage of circuit is little, then can circuit reduction be become form shown in Figure 16, among the figure; DFF1, DFF2 and DFF5 replace with 1 irrelevant trigger, 0 irrelevant trigger and irrelevant trigger respectively, and need not to be connected into scan chain, and the structure that remaining DFF is replaced to important trigger is carried out the part Scan Design.
Embodiment two: this embodiment is to the further specifying of the important trigger described in the embodiment one, and below in conjunction with Fig. 3 and Fig. 9 this embodiment is described.
The said important trigger 1 of this embodiment comprises first selector 1-1, second selector 1-2, third selector 1-3, the 4th selector switch 1-4, test trigger 1-5 and function trigger 1-6,
The Enable Pin input signal of first selector 1-1 is mode [1], and the Enable Pin input signal of second selector 1-2 is mode [0], and the Enable Pin input signal of third selector 1-3 is mode [0], and the Enable Pin input signal of the 4th selector switch 1-4 is mode [1];
0 input end of first selector 1-1 is as the test cell scan data input terminal of said important trigger 1; Input test scan-data SI; 1 input end of first selector 1-1 links to each other with 0 input end of second selector 1-2, and 0 input end of second selector 1-2 is as the performance data input end of said important trigger 1, input function data FI; 1 input end of second selector 1-2 links to each other with 0 input end of first selector 1-1
The output terminal of first selector 1-1 links to each other with the D signal input part of test trigger 1-5; The Q signal output terminal of test trigger 1-5 links to each other with 0 input end of third selector 1-3; The Q signal output terminal of test trigger 1-5 also links to each other with 1 input end of the 4th selector switch 1-4; The clock signal of test trigger 1-5 is TCLK, and the output terminal of third selector 1-3 is the scan-data output terminal, output scanning data SO;
The output terminal of second selector 1-2 links to each other with the D signal input part of function trigger 1-6; The Q signal output terminal of function trigger 1-6 links to each other with 0 input end of the 4th selector switch 1-4; The Q signal output terminal of function trigger 1-6 also links to each other with 1 input end of third selector 1-3; The clock signal of function trigger 1-6 is FCLK, and the output terminal of the 4th selector switch 1-4 is the performance data output terminal, output function data FO.
At first traditional Scan Design method is described referring to Fig. 1:
Testability Design becomes chip and tests easily through in the chip original design, inserting the various hardware logics that are used to improve the chip testability, thereby reduces the testing cost of chip significantly.Scan Design is one of main method of adopting of current design for Measurability.
Sequential circuit is made up of built-up section and the trigger with memory function, and the input of trigger links to each other with the output of built-up section, and the output while of trigger is as the input of built-up section.Scan Design is meant and converts the timing unit in the circuit-under-test into can scan trigger, connects into scan chain, makes test and excitation can serial move into scan chain and test response can serial shift out scan chain.Thus, complicated timing sequence test generation problem has become simple combination and has generated problem, has reduced the complexity that test generates, and has improved fault coverage simultaneously.Each scanning element just has two inputs and two output ports.FI, FO represent the function input and output of scanning element respectively, are equivalent to the D and the Q of former trigger, and SI, SO represent to scan input and output respectively, are used to accomplish scan function.
So-called on-line testing require test and circuit working to accomplish simultaneously, and test process can not influence the duty of circuit.In the sequential circuit; Because trigger can write down the duty of previous moment circuit; Carry out on-line testing if still continue to use traditional Scan Design; Will owing to test vector on sweep trigger immigration and shift out the state that changes sweep trigger, and then the work of circuit caused be difficult to imagination influence.
Important trigger has solved this problem well.Its structure is as shown in Figure 3, each scan chain cell except four IO ports, also have one two control signal mode and two clock signals (FCLK, TCLK).The control signal of each unit links together, and is produced by control circuit jointly, can reduce the expense that wiring brings, and clock control circuit is as shown in Figure 9.FCLK and TCLK are respectively functional clock and test clock, and the clock signal with each unit connects together equally, is produced in the lump by clock selecting mechanism.Two triggers are arranged: function d type flip flop and test d type flip flop in the element circuit.Also have four be used for control data flow to the alternative selector switch.
This scan chain cell has increased a trigger and a plurality of selector switch than elementary cell, is combined into the alternative selector switch with two transmission gates (TG) and a not gate, can reduce the hardware spending of circuit to a certain extent.Except can be implemented in the line test, another advantage of this unit is that two d type flip flops structurally are symmetrical fully, can exchange use.One of them just can be regarded as another redundancy backup like this.If one fault has taken place, can control another through switch-over control signal and work on, improved the fault-tolerant ability of Circuits System greatly.
CCL shown in Figure 9: the test control of system be unable to do without correct sequential logic.Clock selecting mechanism is produced by control circuit, comprises two clock signals: system works clock FCLK and test clock TCLK, FCLK are as the clock of function trigger 1-6, and TCLK is as the clock of test trigger 1-5.The frequency of clock has determined the travelling speed of circuit, simultaneously also can be through clock stop to realize latching of data.Two clocks are produced respectively, and such clock selecting mechanism makes test process more flexible.Clock selecting mechanism and control signal mode realize the switching of circuit working and test mode jointly.Its truth table is:
| Sequence number | ?Mode[1] | ?Mode[0] | FCLK | TCLK | Test mode | Work is not |
| 1 | ?1 | ?0 | 0 | CLK1 | The test of sequential circuit built-up section | Do not work |
| 2 | ?1 | ?1 | |
0 | Function trigger is tested | Do not work |
| 3 | ?0 | ?0 | 0 | CLK1 | Scanning moves into or shifts out; To the test of test trigger | Do not work |
| 4 | ?0 | ?0 | |
0 | Operate as normal | Work |
| 5 | ?0 | ?0 | CLK2 | CLK1 | Scanning moves into or shifts out; Function trigger is tested | Work |
Below in conjunction with Figure 10 the clock signal of important trigger is further specified: the clock signal TCLK of test trigger 1-5 and the independent clock of clock signal FCLK of function trigger 1-6 for producing respectively; Clock signal TCLK is square wave CLK1 or puts 0; Clock signal FCLK is square wave CLK2 or puts 0, and the frequency of square wave CLK1 and square wave CLK2 is identical or different.
When the frequency of two clock signals was identical, this set mode was the clock when being used for non-concurrent test, and when FCLK was in square wave CLK2 state, sequential circuit was in normal operating conditions, simultaneously, test data was moved into operation; When FCLK puts 0, the sequential circuit built-up section is tested; Behind the EOT, test data is shifted out operation.This immigration operation of shifting out operation and next time is carried out simultaneously.
When the frequency of two clock signals was inequality, referring to shown in Figure 11, the frequency of CLK1 was 2～10 times of frequency of CLK2.
Clock when this set mode is used for concurrent test; FCLK is in square wave CLK2 state always; Be that the sequential circuit is in normal operating conditions always, after test data is moved into completion, utilize the one-period of FCLK to accomplish test the sequential circuit built-up section; Behind the EOT, test data is shifted out operation.This immigration operation of shifting out operation and next time is carried out simultaneously.
Below, the application of the described important trigger of this embodiment is further specified.
Adopt the said wire testing method that is implemented in of this embodiment may further comprise the steps:
When mode [1]=0, mode [0]=0, FCLK are square wave CLK2, and TCLK put 0 o'clock, and scan chain cell is in normal operating conditions, and the performance data of input is via second selector 1-2, function trigger 1-6 and the 4th selector switch 1-4 output; As shown in Figure 6.
When mode [1]=0; Mode [0]=0, FCLK puts 0, when TCLK is square wave CLK1; Scan chain cell is in the state that test trigger 1-5 is tested, and the test data of input is via first selector 1-1, test trigger 1-5 and third selector 1-3 output; As shown in Figure 5.
When mode [1]=1; Mode [0]=1, FCLK are square wave CLK2, and TCLK put 0 o'clock; Scan chain cell is in the state that function trigger 1-6 is tested, and the performance data of input is via second selector 1-2, function trigger 1-6 and the 4th selector switch 1-4 output; As shown in Figure 4.
When mode [1]=0, mode [0]=0, FCLK are square wave CLK2, and when TCLK was square wave CLK1, scan chain cell was in data and moves into state; As shown in Figure 8.
When mode [1]=1; Mode [0]=0; FCLK puts 0, and when TCLK was square wave CLK1, scan chain cell was in the state that the sequential circuit built-up section is tested; The performance data of input realizes the non-concurrent test to the sequential circuit built-up section via first selector 1-1, test trigger 1-5 and the 4th selector switch 1-4 output.As shown in Figure 7.
When mode [1]=0, mode [0]=0, FCLK are square wave CLK2, and when TCLK was square wave CLK1, scan chain cell was in data and shifts out state;
When mode [1]=0, mode [0]=0, FCLK are square wave CLK2, and TCLK put 0 o'clock, and scan chain cell is in normal operating conditions once more, and the performance data of input is via second selector 1-2, function trigger 1-6 and the 4th selector switch 1-4 output.
The process of non-concurrent test is: operate as normal, and---------scanning moves into, and---test---scanning is shifted out---recovers normal operating conditions in function trigger 1-6 self check in test trigger 1-5 self check.
During the described non-concurrent test of this embodiment, the frequency of FCLK and TCLK is identical, in circuit, uses the non-concurrent test that important trigger can be realized sequential circuit.Its sequential control situation is shown in figure 10.Before the test, test trigger 1-5 realizes the immigration of scan chain data under the effect of TCLK, and behind the EOT, each data serial of testing on the trigger 1-5 shifts out, and this operation of shifting out is operated and can be carried out simultaneously with immigration next time.This process can be carried out with the work of circuit simultaneously.When test trigger 1-5 was used for circuit test, for the data among the assurance function trigger 1-6 are not destroyed, FCLK need remain unchanged to realize the data latching function.If test process continues a plurality of TCLK cycles, can realize the repeatedly follow-on test under one group of test vector effect.If test process only continues a TCLK cycle, then non-concurrent test process is only brought the time redundancy of one-period.
Explain below in conjunction with Fig. 6, Fig. 7, Fig. 8 and Figure 11 and to adopt the described important trigger of this embodiment to realize online concurrent test method, this method may further comprise the steps:
When mode [1]=0, mode [0]=0, FCLK are square wave CLK2, and TCLK put 0 o'clock, and scan chain cell is in normal operating conditions, and the performance data of input is via second selector 1-2, function trigger 1-6 and the 4th selector switch 1-4 output; As shown in Figure 6.
When mode [1]=0, mode [0]=0, FCLK are square wave CLK2; When TCLK was square wave CLK1, scan chain cell was in normal operating conditions, and each cycle of square wave CLK2 comprises n square wave CLK1 cycle; N=2～10 to the time program process of the test of sequential circuit built-up section are:
At first test data is scanned and move into operation; As shown in Figure 8
After the completion test data scans immigration or shifts out operation, accomplish the sequential circuit built-up section in the cycle at an ensuing FCLK and test, as shown in Figure 7.
Then, test data is scanned shift out operation;
Repeat aforesaid operations, accomplish concurrent test the sequential circuit built-up section.
The said FCLK cycle is meant between first rising edge to the second rising edge that captures square wave CLK2.
Test makes mode [1]=0 after accomplishing, and mode [0]=0, FCLK are square wave CLK2, and TCLK put 0 o'clock, and scan chain cell is in normal operating conditions once more, and the performance data of input is via second selector 1-2, function trigger 1-6 and the 4th selector switch 1-4 output.
The process of concurrent test is: operate as normal, and---scanning moves into, and---test---scanning is shifted out---recovers normal operating conditions.
Through rational design, when the frequency of the frequency ratio FCLK of TCLK in the chip was fast, this scan chain cell also can be used for concurrent test.Be that the situation of former working clock frequency twice is that example is explained with the frequency of TCLK among Figure 11, the work of circuit is that rising edge clock triggers.Before and after the test, the scanning of data moves into and shifts out the duty that process can not influence circuit.But because the frequency of TCLK is fast than FCLK, in the one-period of FCLK, function trigger only has a rising edge, and two rising edges can appear in TCLK.Function trigger is through behind the rising edge, and its state remained unchanged in this cycle.In the later half cycle of this clock period, the test trigger is accomplished test at second rising edge place of TCLK.On the whole, the work of primary circuit is not affected before and after the test, and the increase of TCLK frequency can reduce to scan the time that moves in and out.If the frequency of TCLK can also realize the test to the continuous multicycle working condition of same test vector greater than more than the FCLK twice.This operation of shifting out is operated and can be carried out simultaneously with immigration next time.
Accomplishing the process that the sequential circuit built-up section tests below in conjunction with Figure 11 explanation in cycle at an ensuing FCLK is:
In cycle, when n-i the rising edge of square wave CLK1 arrived, true value was set at a FCLK: mode [1]=1, and mode [0]=0 tests the sequential circuit built-up section, and i is test period,
When the rising edge of first square wave CLK2 after accomplishing test arrives, true value is recovered to be set to again: mode [1]=0, mode [0]=0 carries out scan-data and moves into or shift out operation.
Test period i can confirm according to actual conditions, if the TCLK frequency is 2 times of the FCLK frequency, then comprises two TCLK cycles in the one-period of FCLK, and the 2nd TCLK cycle is used for test, i.e. test period i=1 in the FCLK cycle that promptly is used to test.
If the TCLK frequency is 10 times of the FCLK frequency, then comprise 10 TCLK cycles in the one-period of FCLK, test period i=1,2,3,4,5,6,7,8 or 9, the 2nd～10 TCLK cycle is used for test in the FCLK cycle that promptly is used to test; Or the 3rd～10 TCLK cycle is used for test; Or the 4th～10 TCLK cycle is used for test; Or the 5th～10 TCLK cycle is used for test ..., or the 10th TCLK cycle be used for test, formulate concrete scheme according to actual needs.
Embodiment three, this embodiment are further specifying the irrelevant trigger described in the embodiment one; Referring to shown in Figure 12; The described irrelevant trigger of this embodiment is made up of selector switch and d type flip flop; 0 input end of said selector switch connects the data output end of d type flip flop, and the data output end of said selector switch connects the data input pin of d type flip flop, and the data output end of said d type flip flop is the data output end of irrelevant trigger.
Embodiment four, this embodiment are further specifying the irrelevant trigger of 1 described in the embodiment one; Referring to shown in Figure 13; This embodiment described 1 irrelevant trigger comprises input selector, outlet selector and d type flip flop; 0 input end of said input selector connects the data output end of d type flip flop, and the data output end of said input selector connects the data input pin of d type flip flop, and the data output end of said d type flip flop connects 1 input end of outlet selector; 0 input end of said outlet selector puts 1, and the data output end of this outlet selector is the data output end of 1 irrelevant trigger.
Embodiment five, this embodiment are further specifying the irrelevant trigger described in the embodiment one; Referring to shown in Figure 14; This embodiment described 0 irrelevant trigger is made up of input selector, outlet selector and d type flip flop; 0 input end of said input selector connects the data output end of d type flip flop, and the data output end of said input selector connects the data input pin of d type flip flop, and the data output end of said d type flip flop connects 1 input end of outlet selector; 0 input end of said outlet selector puts 0, and the data output end of this outlet selector is the data output end of 0 irrelevant trigger.
Embodiment six, this embodiment are that one described employing method of emulation screening detects illustrating of output pin process to embodiment.
In this embodiment, equivalent output pin fault simulation result is referring to table 1-a) shown in.P
iI output pin of indication circuit, f
iJ fault in the indication circuit, g
IjBe fault flag.If P
iCan check out f
iFault, then g
Ij=1, otherwise g
Ij=0.With P
iThe detectable failure number scale is g
i,
Then the set that can detect number of faults of each pin can be expressed as G={g
i.Choose equivalent output pin with greedy algorithm, choose the maximal value max{g of each element among the G at every turn
i, then i pin is exactly the equivalent output pin that needs concern.It much is repetition that the characteristics of CUT have determined to have in the detectable fault of each equivalent output pin, for the pin that guarantees to choose each time all is a locally optimal solution.After choosing a pin, only consider nd fault, in the residue pin, continue to choose.If the i pin of choosing can detect fault j, then order:
g
ij＝0，i＝1，2，...，m，
Continue to choose new max{g
i, till fault coverage reaches requirement.For example the result of certain fault emulation is like table 1-b) shown in, have 8 faults in the circuit, 5 equivalent output pins.Can find out P
4Can detect 5 in 8 faults, fault 1,2,3,5,7.Therefore at first select No. 4 equivalent output pin.With fault 1,2, the Reflector position 0 of all pins of 3,5,7 correspondences is only considered to remain faults with 4 output pins detections of residue, still chooses and can survey a maximum pin of fault simultaneously.Table 1-c) be depicted as pin 5, choose 4,5 two pins this moment altogether, and fault coverage has reached 100%.Can find out the 2nd pin using that greedy algorithm obtains and table 1-b) to come deputy pin be different to middle number of faults, this algorithm can detect more fault through detecting less equivalent output pin.
The equivalent output pin of table 1 is chosen algorithm and is given an example
Table 1-a) equivalent output pin is chosen algorithm
| f 1 | f 2 | f 3 | … | f j | … | f n | sum | ||
| P 1 | g 11 | g 12 | g 13 | … | g 1j | … | g 1n | g 1 | |
| P 2 | g 21 | g 22 | g 23 | … | g 2j | … | g 2n | g 2 | |
| … | … | … | … | … | |||||
| P i | g i1 | g i2 | g i3 | … | g ij | … | g in | g i | |
| … | … | … | … | … | |||||
| P m | g m1 | g m2 | g m3 | … | g mj | … | g mn | g m |
Table 1-b) equivalent output pin is chosen algorithm for example
| f 1 | f 2 | f 3 | f 4 | f 5 | f 6 | f 7 | f 8 | sum | |
| P 1 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 4 |
| |
1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 4 |
| |
1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 3 |
| |
1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 5 |
| |
0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 3 |
Table 1-c) equivalent output pin is chosen algorithm for example, step 2
Claims (8)
1. based on the method for designing of the scanning element of the part of retrofit testing vector set scanning, it is characterized in that,
At first, the method that adopts equivalent output pin to the sequential circuit built-up section to carry out fault simulation is obtained the important equivalent output pin important to fault detect;
Then, adopt the method acquisition retrofit testing vector set that the equivalent input pin of sequential circuit built-up section is carried out fault simulation;
At last, according to the retrofit testing vector set with to the unessential equivalent output pin of fault detect, trigger is divided into decides two types on input trigger and important trigger, and important trigger series connection is formed portion of scan chain.
2. the method for designing of the scanning element of the part scanning based on the retrofit testing vector set according to claim 1 is characterized in that, said decide input trigger be irrelevant trigger, 0 irrelevant trigger and 1 trigger that has nothing to do.
3. the method for designing of the scanning element of the part scanning based on the retrofit testing vector set according to claim 1; It is characterized in that; Said employing is confirmed the unessential equivalent output pin of fault detect the method that the equivalent output pin of sequential circuit built-up section carries out fault simulation; Be meant that according to the fault simulation result of ifq circuit and fault injection back circuit obtain the important equivalent output pin important to fault detect, detailed process is:
The first step: in the built-up section circuit of sequential circuit, inject a fault in order;
Second step: to the faulty circuit after this fault of process injection; All test vector input circuits in the existing test set are tested; Detect the state of each equivalent output pin one by one, and the corresponding failure zone bit of this equivalence output pin done following the processing according to the state of each equivalent output pin:
If can detect this fault, corresponding Reflector position 1 that then should the equivalence output pin;
If can't detect this fault, corresponding Reflector position 0 that then should the equivalence output pin;
The 3rd step: the circulation first step and second step, finish up to all faults injections;
The 4th step: all fault flags of each equivalent output pin are done add up, the fault flag that obtains this equivalence output pin add up with;
The 5th step: fault flag is added up and ordering from big to small; The fault flag of maximum is added up and pairing equivalent output pin is elected important equivalent output pin as; Simultaneously, all fault flags that write down this equivalence output pin are 1 fault, and equal zero clearing of fault flag of this fault of expression of all equivalent output pins with other; Then, fault flag that this equivalence output pin is corresponding adds up and puts 0;
The 6th step: the number of faults that fault flag covered of calculating acquired all important equivalent output pins; And according to the corresponding fault coverage of said number of faults calculating acquisition; If said fault coverage meets the requirements of the minimum value of fault coverage, then accomplish obtaining of all important equivalent output pins; Otherwise, return execution in step four.
4. the method for designing of the scanning element of the part scanning based on the retrofit testing vector set according to claim 1; It is characterized in that the process that the method that said employing is carried out fault simulation to the equivalent input pin of sequential circuit built-up section obtains the retrofit testing vector set is:
Adopt original test vector collection to carry out emulation, and be according to the process of simulation result acquisition retrofit testing vector set:
The first step: in order,, calculate then and can survey number of faults with certain position 0 in the original test set;
Second step:, calculate then and can survey number of faults with same position 1;
The 3rd step: calculate certain position 0 that obtains in the above-mentioned test set respectively and put 1 o'clock detected fault coverage of ability;
If be 100%, then the equivalent input pin of this correspondence is irrelevant input, and it is don't-care bit X that test vector is concentrated the data of this position; Execution in step five;
If only putting at 0 o'clock is 100%, then the equivalent input pin of this correspondence is 0 irrelevant input, and it is 0 that test vector is concentrated the state of this position; Execution in step five;
If only putting at 1 o'clock is 100%, then the equivalent input pin of this correspondence is 1 irrelevant input, and it is 1 that test vector is concentrated the state of this position; Execution in step five;
If be not 100% all, carry out next step;
The 4th step: put 0 with put in 1 fault coverage select bigger one,
If this fault coverage is to put 0 o'clock fault coverage, and greater than the significance level quantization scale, it is 0 that test vector is concentrated the state of this position; Execution in step five;
If this fault coverage is to put 1 o'clock fault coverage, and greater than the significance level quantization scale, it is 1 that test vector is concentrated the state of this position; Execution in step five;
The 5th step: circulation is carried out above four steps, and all positions in the original test set of traversal promptly test all equivalent input pins, obtain the retrofit testing vector set.
5. the method for designing of the scanning element of the part scanning based on the retrofit testing vector set according to claim 1; It is characterized in that; Said important trigger 1 comprises first selector 1-1, second selector 1-2, third selector 1-3, the 4th selector switch 1-4, test trigger 1-5 and function trigger 1-6
The Enable Pin input signal of first selector 1-1 is mode [1], and the Enable Pin input signal of second selector 1-2 is mode [0], and the Enable Pin input signal of third selector 1-3 is mode [0], and the Enable Pin input signal of the 4th selector switch 1-4 is mode [1];
0 input end of first selector 1-1 is as the test cell scan data input terminal of said important trigger 1; Input test scan-data SI; 1 input end of first selector 1-1 links to each other with 0 input end of second selector 1-2, and 0 input end of second selector 1-2 is as the performance data input end of said important trigger 1, input function data FI; 1 input end of second selector 1-2 links to each other with 0 input end of first selector 1-1
The output terminal of first selector 1-1 links to each other with the D signal input part of test trigger 1-5; The Q signal output terminal of test trigger 1-5 links to each other with 0 input end of third selector 1-3; The Q signal output terminal of test trigger 1-5 also links to each other with 1 input end of the 4th selector switch 1-4; The clock signal of test trigger 1-5 is TCLK, and the output terminal of third selector 1-3 is the scan-data output terminal, output scanning data SO;
The output terminal of second selector 1-2 links to each other with the D signal input part of function trigger 1-6; The Q signal output terminal of function trigger 1-6 links to each other with 0 input end of the 4th selector switch 1-4; The Q signal output terminal of function trigger 1-6 also links to each other with 1 input end of third selector 1-3; The clock signal of function trigger 1-6 is FCLK, and the output terminal of the 4th selector switch 1-4 is the performance data output terminal, output function data FO.
6. the method for designing of the scanning element of the part scanning based on the retrofit testing vector set according to claim 2; It is characterized in that; Described irrelevant trigger is made up of selector switch and d type flip flop; 0 input end of said selector switch connects the data output end of d type flip flop, and the data output end of said selector switch connects the data input pin of d type flip flop, and the data output end of said d type flip flop is the data output end of irrelevant trigger.
7. the method for designing of the scanning element of the part scanning based on the retrofit testing vector set according to claim 2; It is characterized in that; Said 1 irrelevant trigger is made up of input selector, outlet selector and d type flip flop; 0 input end of said input selector connects the data output end of d type flip flop, and the data output end of said input selector connects the data input pin of d type flip flop, and the data output end of said d type flip flop connects 1 input end of outlet selector; 0 input end of said outlet selector puts 1, and the data output end of this outlet selector is the data output end of 1 irrelevant trigger.
8. the method for designing of the scanning element of the part scanning based on the retrofit testing vector set according to claim 2; It is characterized in that; Said 0 irrelevant trigger is made up of input selector, outlet selector and d type flip flop; 0 input end of said input selector connects the data output end of d type flip flop, and the data output end of said input selector connects the data input pin of d type flip flop, and the data output end of said d type flip flop connects 1 input end of outlet selector; 0 input end of said outlet selector puts 0, and the data output end of this outlet selector is the data output end of 0 irrelevant trigger.
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