CN104375078B - A kind of sweep test latch macroelement and scan testing methods - Google Patents
A kind of sweep test latch macroelement and scan testing methods Download PDFInfo
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Abstract
A kind of sweep test latch macroelement and scan testing methods, sweep test macroelement of the scan test design method of the present invention by customization, and with reference to special design cycle, the common scan test design method for d type flip flop can be utilized to produce the structure-based ATPG test vectors for latch unit, solve the existing Digital ASIC based on latch design to be difficult to carry out design for Measurability exploitation, test vector fault coverage is low, the complicated problem of Time-Series analyses, the fault coverage of chip testing is greatly improved, ensure that the effectiveness and completeness of chip testing, it is mainly used in the test vector exploitation of the Digital ASIC based on latch design.
Description
Technical field
The present invention relates to a kind of sweep test macroelement and scan testing methods, particularly a kind of sweep test latch is grand
Unit and scan testing methods, belong to quasiconductor Design of Digital Integrated Circuit and field tests, are mainly used in quasiconductor numeral
The structuring test process of integrated circuit.
Background technology
With the continuous development and progress of quasiconductor digital integrated electronic circuit, how under rational time and cost overhead,
The even more massive digital integrated electronic circuit of million gate leves growing to scale, ten million gate leve carries out abundant and effective
Test, is increasingly becoming one of most difficult and time-consuming design objective.When circuit scale is more than 100,000, hand-coding
The development time of (towards function) test vector will exceed the design time of practical devices itself.Therefore design for Measurability skill
Art (Design For Test, DFT) is gradually by the attention and application of engineer.
Scan testing methods are a very important methods in DFT technique, the method by the design process, by institute
There is sequential element (such as trigger) to replace with scanning sequence element, and all of scanning sequence element is connected in test
For one " scan chain ", make to be difficult to originally the spy that the sequence circuit tested shows the combination logic of easy test in test
Property, and be more convenient to complete structure using electric design automation (Electronic Design Automation, EDA) instrument
The automatic test vector generation (Automatic Test Pattern Generation, ATPG) changed.By in common numeral
In sequence circuit interleave scan chain and using atpg tool produce test vector, not only significantly reduce test development when
Between and manpower, and generate structurized test vector can be directed to specific fault type (such as persistent fault, Stuck-
At Fault) high fault coverage is reached, up to 95% or even more than 98%.This, when traditional test vector exploitation it is remote
Far it is beyond one's reach.
But the design for Measurability instrument of industry is when scan testing methods are realized at present, what is be mainly directed towards is along triggering class
Sequential element (d type flip flop), by the method for Mux-Scan, increase the choosing of Mux multichannels at the data input pin D ends of d type flip flop
Select device, controlled with outside port in function state and test state, the D ends of D triggers be normal prime logic output or
Output of the series connection for the prime d type flip flop in scan chain step by step.Industry develops shape for the sweep test of d type flip flop at present
Into highly developed flow process, not only EDA suppliers provide ripe scan chain integration tool, ATPG vector Core Generators and
Timing analysis tool, Ge great techniques manufacturer is also already in its standard block technology library there is provided the scanning d type flip flop for having customized
Unit.
And be then another situation for latch unit is adopted for the circuit of main sequential element.First,
In the Mux-Scan design methodologies of current main flow, the processing mode of latch unit is enabled by the test of control port
Signal causes latch unit " transparence ", and mitigating the erroneous transmissions caused by latch unit is affected, but this mode without
Method detects latch unit itself with the presence or absence of failure.Additionally, the premise of this processing mode consider be exactly in circuit when
Sequence element is that, based on d type flip flop, " transparence " of indivedual latch units will not cause too big to overall fault coverage
Affect.And when the overwhelming majority of a digital circuit, when even all of sequential element is made up of latch unit, this
Kind of processing mode cannot clearly be competent at task of Validity Test is carried out to circuit.
Secondly, the scan testing methods for latch unit that EDA suppliers propose at present, i.e., based on level-sensitive
The scan testing methods of Scan Design (Level Sensitive Scan Design, LSSD) method exist it is larger not
Foot, the method is by increasing by one from latch (slave latch) for latch, and increases the side of two independent clocks
Method, realizes the replacement to original latches, and forms scan chain.But of both party's science of law be present：First, insertion is swept
After retouching chain, function state and when order analysis become extremely complex, for the Time-Series analyses in subsequent design, placement-and-routing and
ATPG vectors are generated considerable influence；Second, current eda tool is very good for LSSD scan methods actually do not have
Support, technique manufacturer also seldom provides the LSSD latch unit of customization, implements difficulty larger.
Based on above-mentioned consideration, for based on latch unit Design of Digital Integrated Circuit (the timing unit overwhelming majority or
Person is all using the design of latch unit), need a kind of eda tool and technology library list that can either utilize existing Mux-Scan
Unit completes scan chain insertion, ensure that the design for Measurability method of the fault coverage of circuit again.
The content of the invention
The present invention technology solve problem be：The existing design for Measurability method based on latch is overcome to cover in failure
Deficiency in lid rate and design complexities, it is proposed that a kind of sweep test latch macroelement and scan testing methods, the invention
For the Mux-Scan sweep tests of latch unit, the existing sweep test side for d type flip flop unit can have both been utilized
The science of law and eda tool, simplify design cycle, can ensure that high fault coverage again.
The present invention technical solution be：A kind of sweep test latch macroelement, including：Two latch, one
Phase inverter and two MUX；
Described two latch are respectively test latch and function latch；Two MUX are respectively more than first
Road selector and the second MUX；
0 data-in port of the first MUX is connected with FPDP D, 1 data-in port and macroelement
Scan input end mouth SI connects, and selects input port S1 to be connected with the scanning enable port SE of macroelement, data-out port Y1
It is connected with the input port D1 of test latch；
The input port of phase inverter is connected with the input end of clock mouth CK of macroelement, the lock of output port and test latch
Deposit control signal input mouth G1 connections；
The output port Q1 of test latch is connected with 1 input port of the second MUX, anti-phase output port QN1
Floating；
0 input port of the second MUX is connected with FPDP D, selects the test of input port S2 and macroelement
Mode control signal port TM connects, and data-out port Y2 is connected with the input port D2 of function latch；
The latch control signal input port G2 of function latch is connected with the input end of clock mouth CK of macroelement, outfan
Mouth Q2 is connected with the output port Q of macroelement, and anti-phase output port QN2 is connected with the anti-phase output port QN of macroelement；
If TM=0, the second MUX exports the data of 0 input port, and does not export the data of 1 input port, the
One MUX, phase inverter and test latch are to the output of sweep test latch macroelement without effect, function latch
, to the output of sweep test latch macroelement without effect, scanning is surveyed for work, scan input end mouth SI and scanning enable port SE
Examination latch macroelement is equivalent to single latch；
If TM=1, the second MUX exports the data of 1 input port, and does not export the data of 0 input port, surveys
The output port Q1 of examination latch is connected with the input D2 of function latch, the input clock of sweep test latch macroelement
When signal is low level, test latch is effectively exported；The input clock signal of sweep test latch macroelement is high level
When, function latch is effectively exported, and sweep test latch macroelement is equivalent to one and selects the scanning D at end to touch with data input
Send out device.
During the TM=0, the circuit comprising sweep test latch macroelement is in function state；During TM=1, comprising scanning
The circuit of test latch macroelement is in test state.
A kind of scan testing methods based on sweep test latch macroelement, it is characterised in that step is as follows：
(1) sweep test latch macroelement is mapped to the technology library of scan test circuit target process, i.e. db storehouses and
Automatically in test vector generation storehouse, i.e. dft storehouses；
(2) logic synthesis is carried out using the db storehouses comprising latch unit, obtains the scan test circuit after logic synthesis
Netlist；The logic synthesis is that scan test circuit source code is mapped as the scan test circuit net corresponding with db storehouses
Table；
(3) the scan test circuit netlist obtained in step (2) is carried out into text replacement, specially：By sweep test electricity
In road network table, all of latch unit replaces with d type flip flop unit；
(4) chain insertion is scanned using the scan test circuit netlist after the replacement of step (3) Chinese version, obtain scan chain
Scan test circuit netlist after insertion；
(5) the scan test circuit netlist after scan chain insertion in step (4) is carried out into text replacement, is obtained comprising scanning
The scan test circuit netlist of test latch macroelement；Specially：By the scanning d type flip flop produced in scan chain insertion process
Unit replaces with sweep test latch macroelement, and by the scanning enable port SE of sweep test latch macroelement and scans
The scanning of test circuit enables input port connection, by test pattern control signal TM of sweep test latch macroelement with sweep
Retouch the test pattern control signal connection of test circuit；
(6) using the scan test circuit netlist comprising sweep test latch macroelement in step (5), using step
(1) in, the db storehouses comprising sweep test latch macroelement are scanned the placement-and-routing of test circuit, Time-Series analyses, function and imitate
True and time stimulatiom, and automatic test vector is produced using the dft storehouses comprising sweep test latch macroelement in step (1),
That is ATPG test vectors；
(7) sweeping for test circuit is scanned using the scan test circuit and ATPG test vectors that obtain in step (6)
Retouch test.
The present invention is had the beneficial effect that compared with prior art：
(1) present invention in method on the basis of existing elementary cell, by by two latch, a phase inverter and
Two MUX are combined, and constitute a kind of special structure, i.e. sweep test latch macroelement.The macroelement
Input port includes：FPDP D, scans enable port SE, scan input end mouth SI, test pattern control signal port TM,
Input end of clock mouth CK；Output port includes：Output port Q, anti-phase output port QN.
(2) the sweep test latch macroelement constituted by the method in the present invention has two kinds of working conditions, in TM=0
When, the circuit comprising sweep test latch macroelement is in function state；During TM=1, comprising sweep test latch macroelement
Circuit in test state.In function state, macroelement is equivalent to latch, and circuit structure is tied with the circuit before interleave scan chain
Structure is completely the same；When state is tested, macroelement is equivalent to scan d type flip flop so that circuit is generated in scan chain insertion and ATPG
During be for d type flip flop carry out.
(3) present invention in method cause scan chain insertion and ATPG generating process in be for d type flip flop carry out,
Compared to the LSSD methods currently for latch, its design tool, design cycle are highly developed, high degree of automation, technique
More preferably, and the test state Time-Series analyses after placement-and-routing are more accurate for the support of manufacturer, and faster, and LSSD can be surveyed the speed of service
Property method for designing increased one times of latch unit in test state, the poor compatibility between different instruments, automaticity are low,
Time-Series analyses and placement-and-routing's difficulty are larger；
(4) present invention in method on testing efficiency compared to it is traditional based on latch design by functional simulation to
The method of amount exploitation test vector, or the design for Measurability method of Mux-Scan is directly based upon, its fault coverage is greatly improved,
Up to 95% or even more than 98%, test quality is significantly improved, test escapement ratio is reduced.
Description of the drawings
Fig. 1 is the design cycle that the present invention realizes the scan test design method based on latch；
Fig. 2 is the schematic diagram that the present invention completes macroelement equivalence replacement；
Fig. 3 is present invention customization macroelement equivalent circuit in different modes；
Fig. 4 is the whole process equivalence explanation of the present invention.
Specific embodiment
As shown in figure 1, the present invention's realizes that process is to define the equivalent sweep test of a common latch unit first
Macroelement model, it is characterised in that include：Two latch, a phase inverter and two MUX；
Described two latch are respectively test latch and function latch；Two MUX are respectively more than first
Road selector and the second MUX；
0 data-in port (i.e. the first data-in port) of the first MUX is connected with FPDP D, 1 number
Be connected with the scan input end mouth SI of macroelement according to input port (i.e. the second data-in port), select input port S1 with it is grand
The scanning enable port SE connections of unit, data-out port Y1 are connected with the input port D1 of test latch；
The input port of phase inverter is connected with the input end of clock mouth CK of macroelement, the lock of output port and test latch
Deposit control signal input mouth G1 connections；
The output port Q1 of test latch is connected with 1 input port of the second MUX, anti-phase output port QN1
Floating；
0 input port of the second MUX is connected with FPDP D, selects the test of input port S2 and macroelement
Mode control signal TM connects, and data-out port Y2 is connected with the input port D2 of function latch；
The latch control signal input port G2 of function latch is connected with the input end of clock mouth CK of macroelement, outfan
Mouth Q2 is connected with the output port Q of macroelement, and anti-phase output port QN2 is connected with the anti-phase output port QN of macroelement；
If TM=0, the second MUX exports the data of 0 input port, and does not export the data of 1 input port, the
One MUX, phase inverter and test latch are to the output of sweep test latch macroelement without effect, function latch
, to the output of sweep test latch macroelement without effect, scanning is surveyed for work, scan input end mouth SI and scanning enable port SE
Examination latch macroelement is equivalent to single latch；Circuit comprising sweep test latch macroelement is in function state；
If TM=1, the second MUX exports the data of 1 input port, and does not export the data of 0 input port, surveys
The output port Q1 of examination latch is connected with the input D2 of function latch, the input clock of sweep test latch macroelement
When signal is low level, test latch is effectively exported；The input clock signal of sweep test latch macroelement is high level
When, function latch is effectively exported, and sweep test latch macroelement is equivalent to one and selects the scanning D at end to touch with data input
Send out device；Circuit comprising sweep test latch macroelement is in test state.
As shown in Fig. 2 the present invention's realizes that process is that sweep test latch macroelement is mapped to sweep test electricity first
In the technology library of road target process, i.e. db storehouses and automatic test vector generation storehouse, i.e. dft storehouses；Secondly using comprising latch list
The db storehouses of unit carry out logic synthesis, obtain the scan test circuit netlist after logic synthesis；3rd, by Vim softwares by logic
Text replacement is carried out in scan test circuit netlist after synthesis, specially：By the scan test circuit netlist after logic synthesis
In latch unit replace with d type flip flop unit；4th, the electricity of the sweep test after d type flip flop will be replaced with using DFT instruments
Road network table be scanned test design, interleave scan chain structure, now all of d type flip flop unit have been replaced with scan D touch
Device unit is sent out, the scan test circuit netlist after scan chain insertion is obtained；5th, again by Vim softwares by interleave scan chain
Scan test circuit netlist afterwards carries out text replacement, obtains the scan test circuit net comprising sweep test latch macroelement
Table, specially：Scanning d type flip flop unit in scan test circuit netlist after interleave scan chain is replaced with into sweep test lock
Storage macroelement, and the scanning enable port SE of sweep test latch macroelement is enabled with the scanning of scan test circuit defeated
Inbound port connects, by test pattern control signal TM of sweep test latch macroelement and the test pattern of scan test circuit
Control signal connects；6th, using comprising sweep test latch macroelement db storehouses complete placement-and-routing, formal verification, when
Sequence analysis, functional simulation and time stimulatiom, and form the scan test circuit comprising sweep test latch macroelement；7th,
Using atpg tool and dft storehouses for the scan test circuit comprising sweep test latch macroelement, final structure is produced
Change ATPG test vectors, for the sweep test of high fault coverage.
As shown in figure 3, in whole design process, having carried out 2 texts altogether and having replaced and 1 interleave scan chain structure
Operation.After the completion of second text replacement operation, the i.e. replacement of sweep test latch macroelement is completed, can be by outside complete
Office's scan control signal control circuit-under-test still tests state in function state.When outside whole scan control signal port connects low
During level, macroelement realizes that the function of latch, i.e. function state design equivalent with original netlist；When outside whole scan control
When signal port processed connects high level, macroelement completes testing scanning chain function, and outside whole scan control as scanning d type flip flop
Signal port processed is multiplexed same pin with test mode signal during design for Measurability, does not affect generation ATPG vectorial completely.
As shown in figure 4, the sweep test latch macroelement of present invention equivalent substitution in scan test circuit can not enter
Latch in the circuit of row sweep test, but except input end of clock mouth G, data-in port D, data-out port Q
Outside oppisite phase data output port QN, increased three ports again, including scan input end mouth SI, scanning enable port SE and
Test pattern control signal port TM.The macroelement includes normal function latch, and test latch selects data path
Two-stage MUX, and a phase inverter for making two stage latch clock inversion.First MUX and the second multichannel
The selection end of selector connects scanning enable port SE and test pattern control signal port TM respectively.
As shown in table 1, the truth table of sweep test latch macroelement is divided into two parts, as TM=0, realizes common lock
The function of storage, when CK is high, latch is in " transparent " state, the state before latch keeps when CK is low；Work as TM
The function of scanning d type flip flop when=1, is realized, is now changed into along sensitive sequential element, when SE ends from level-sensitive sequential element
For 0 when, the value of sampled data input D export to outfan Q and QN in CK rising edges, when SE ends are 1, rise in CK
Along sampled scan input SI value and export to outfan Q and QN, the state before preserving when without CK rising edges.
1 sweep test latch macroelement truth table of table
TM=0 function states
| SE | SI | D | CK | Qn+1 | QNn+1 |
| X | X | 0 | 1 | 0 | 1 |
| X | X | 1 | 1 | 1 | 0 |
| X | X | X | 0 | Qn | QNn |
TM=1 tests state
| SE | SI | D | CK | Qn+1 | QNn+1 |
| 0 | X | 0 | 01 | 0 | 1 |
| 0 | X | 1 | 01 | 1 | 0 |
| 1 | 0 | X | 01 | 0 | 1 |
| 1 | 1 | X | 01 | 1 | 0 |
| X | X | X | 10 | Qn | QNn |
Present invention is mainly applied to all by latch unit, or most of sequential element is made up of latch unit
Digital ASIC design for Measurability, produce for latch unit structure-based ATPG test vectors, greatly
Amplitude improves the fault coverage of chip testing, reduces the test escapement ratio of chip, it is ensured that the effectiveness of chip testing.
The remarkable result of the present invention is embodied in the actual items for developing 8 8-digit microcontrollers.In 8 8-digit microcontrollers
Sequential element all adopt latch unit, if using the sweep test of LSSD methods, fault coverage is only 70.5%；
In the sweep test based on sweep test latch macroelement using the inventive method, fault coverage can be risen to
96.7%.
Unspecified part of the present invention belongs to general knowledge as well known to those skilled in the art.
Claims (3)
1. a kind of sweep test latch macroelement, it is characterised in that include：Two latch, a phase inverter and two multichannels
Selector；
Described two latch are respectively test latch and function latch；Two MUX are respectively the choosing of the first multichannel
Select device and the second MUX；
0 data-in port of the first MUX is connected with FPDP D, and 1 data-in port is latched with sweep test
The scan input end mouth SI connections of device macroelement, select the scanning Enable Pin of input port S1 and sweep test latch macroelement
Mouth SE connections, data-out port Y1 are connected with the input port D1 of test latch；
The input port of phase inverter is connected with the input end of clock mouth CK of sweep test latch macroelement, output port with test
The latch control signal input port G1 connections of latch；
The output port Q1 of test latch is connected with 1 input port of the second MUX, and anti-phase output port QN1 is floated
It is empty；
0 input port of the second MUX is connected with FPDP D, selects input port S2 grand with sweep test latch
The test pattern control signal port TM connections of unit, data-out port Y2 are connected with the input port D2 of function latch；
The latch control signal input port G2 of the function latch and input end of clock mouth CK of sweep test latch macroelement
Connection, output port Q2 are connected with the output port Q of sweep test latch macroelement, and anti-phase output port QN2 is surveyed with scanning
The anti-phase output port QN connections of examination latch macroelement；
If TM=0, the second MUX exports the data of 0 input port, and does not export the data of 1 input port, more than first
, to the output of sweep test latch macroelement without effect, function latch works for road selector, phase inverter and test latch,
Scan input end mouth SI and scanning enable port SE to the output of sweep test latch macroelement without effect, latch by sweep test
Device macroelement is equivalent to single latch；
If TM=1, the second MUX exports the data of 1 input port, and does not export the data of 0 input port, test lock
The output port Q1 of storage is connected with the input D2 of function latch, the input clock signal of sweep test latch macroelement
For low level when, test latch is effectively exported；When the input clock signal of sweep test latch macroelement is high level, work(
Energy latch is effectively exported, and sweep test latch macroelement is equivalent to a scanning d type flip flop that end is selected with data input.
2. a kind of sweep test latch macroelement according to claim 1, it is characterised in that：During the TM=0, comprising
The circuit of sweep test latch macroelement is in function state；During TM=1, at the circuit comprising sweep test latch macroelement
In test state.
3. a kind of scan testing methods based on sweep test latch macroelement in claim 1, it is characterised in that step is such as
Under：
(1) sweep test latch macroelement is mapped to the technology library of scan test circuit target process, i.e. db storehouses and automatically
In test vector generation storehouse, i.e. dft storehouses；
(2) logic synthesis is carried out using the db storehouses comprising latch unit, obtains the scan test circuit netlist after logic synthesis；
The logic synthesis is that scan test circuit source code is mapped as the scan test circuit netlist corresponding with db storehouses；
(3) the scan test circuit netlist obtained in step (2) is carried out into text replacement, specially：By scan test circuit net
In table, all of latch unit replaces with d type flip flop unit；
(4) chain insertion is scanned using the scan test circuit netlist after the replacement of step (3) Chinese version, obtain scan chain insertion
Scan test circuit netlist afterwards；
(5) the scan test circuit netlist after scan chain insertion in step (4) is carried out into text replacement, is obtained comprising sweep test
The scan test circuit netlist of latch macroelement；Specially：By the scanning d type flip flop unit produced in scan chain insertion process
Replace with sweep test latch macroelement, and by the scanning enable port SE of sweep test latch macroelement and sweep test
The scanning of circuit enables input port connection, by the test pattern control signal port TM of sweep test latch macroelement with sweep
Retouch the test pattern control signal connection of test circuit；
(6) using the scan test circuit netlist comprising sweep test latch macroelement in step (5), using in step (1)
Db storehouses comprising sweep test latch macroelement be scanned the placement-and-routing of test circuit, Time-Series analyses, functional simulation and
Time stimulatiom, and produce automatic test vector using the dft storehouses comprising sweep test latch macroelement in step (1), i.e.,
ATPG test vectors；
(7) scanning for being scanned test circuit using the scan test circuit and ATPG test vectors that obtain in step (6) is surveyed
Examination.
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| CN108414924B (en) * | 2018-05-14 | 2023-07-07 | 珠海一微半导体股份有限公司 | Circuit entering chip test mode and control method thereof |
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| CN112217498B (en) * | 2020-09-24 | 2023-04-14 | 联暻半导体(山东)有限公司 | Multi-bit pulse latch circuit |
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| CN103607196A (en) * | 2013-10-28 | 2014-02-26 | 江苏大学 | Universal logic block output logic macro cell circuit |
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