CN103116121A - Circuit ageing detection method based on self-oscillation circuit - Google Patents

Abstract

The invention discloses a circuit ageing detection method based on a self-oscillation circuit. The method includes choosing an ageing characteristic access collection T in a to-be-detected circuit according to static timing analysis and correlation among ways, remaining logical negation with odd power on each to-be-detected way in the ageing characteristic access collection T to form the self-oscillation circuit, producing a detection vector quantity to excite the self-oscillation circuit to produce a detection level signal by means of a detection production method of a fixed-type fault, and obtaining a circuit ageing characteristic value through the fact that a counter samples the self-oscillation circuit and measuring the ageing degree of the to-be-detected circuit. The method can precisely measure the ageing degree of the circuit at low power consumption, and provides precise bases for circuit ageing failure protection.

Description

Circuit ageing testing method based on the self-oscillation loop

Technical field

The present invention relates to ic test technique and reliability engineering, especially aspect the ageing predetermination and protection of VLSI (very large scale integrated circuit).

Background technology

Developing rapidly of semiconductor technology makes performance of integrated circuits be improved.But the process decrease of integrated circuit, also making aging effect become affects the main challenge in IC reliability and serviceable life.Under the nanoscale process conditions, it is the principal element that causes aging of integrated circuit that negative bias thermal instability (NBTI), hot carrier are injected (HCI), time breakdown (TDDB) and electromagnetism migration (EM).Aging of integrated circuit can cause the increase of circuit time delay and the reduction of circuit performance, and finally causes the inefficacy of circuit.According to existing statistics, aging meeting made the operating rate of integrated circuit reduce by 20% left and right in 10 years.

International semiconductor manufacturing technology industry alliance (SEMATECH) just points out in the report of 2003: the circuit that causes take NBTI, HCI, TDDB and EM as principal element is aging will become later one of subject matter of electronic product reliability that affects in 2010.International semiconductor Technology Roadmap (ITRS) emphasizes in the annual report of 2011, and between 2011 to 2018, semiconductor product will still be faced with the severe challenge that NBTI, HCI, TDDB and EM effect are brought.

Burn-in test is by a test long-time continuous or periodic, the serviceability after analysis device is aging, thus guarantee the reliability of circuit working.Many internationally famous companies such as Intel, IBM have carried out research to the aging of integrated circuit test problem at present.Existing solution about this problem mainly contains: based on the on-line testing of aging Sensor with based on two kinds of the burn-in tests of pre-megacell.

Be that privileged site at integrated circuit inserts aging Sensor based on the on-line testing of aging Sensor, the logical signal of circuit or the electric current and voltage situation of change of device are carried out on-line monitoring.When the variation of various parameters meets the condition that presets, with regard to the aging generation that causes fault of decision circuitry.The major defect of these class methods is: aging Sensor can only the aging generation that whether has caused fault of decision circuitry, can not measure the actual degree of aging of circuit, can't submit necessary information for the anti-aging maintenance of circuit; Self in use will be subject to aging impact aging Sensor, and its reliability is difficult to guarantee; A large amount of uses of aging Sensor can increase circuit load, the increasing circuit power consumption.

It is the non-functional test path of two isomorphisms of insertion extra in circuit based on the ageing testing method of pre-megacell.Allow wherein a test path be subject to the impact of aging effect, become and be subjected to volt circuit; Another test path is not subject to the impact of aging effect, becomes with reference to the path.In the burn-in test process, the method measurement be subjected to volt circuit with reference to the frequency of operation of circuit, and weigh the ageing state of functional circuit self by variation relation more between the two.Supposed premise based on the ageing testing method of pre-megacell is that pre-megacell and functional circuit are in synchronous ageing state.But due to the ageing process of circuit and the real work load of circuit, temperature and frequency have close relationship.Therefore, in side circuit, pre-megacell and functional circuit do not keep synchronous aging state, and its test result is inaccurate.In addition, increase by two extra test paths in circuit, can cause larger circuit power consumption problem.

Summary of the invention

Testing power consumption is high in order to overcome in existing ageing testing method, the inaccurate problem of measuring accuracy, the invention provides the circuit ageing testing method based on the self-oscillation loop, utilization is tested circuit is aging by the self-oscillation loop of circuit self device configuration, and quantize der alterungs-kennwert by the aging character counter, weigh the actual ageing process of circuit.

The present invention is that the technical solution problem adopts following technical scheme:

A kind of circuit ageing testing method based on the self-oscillation loop of the present invention is characterized in carrying out as follows:

Step 1, according to correlativity between static timing analysis and path, choose the aging character way set T in circuit under test:

(1) adopt static timing tool, analyze the sequential situation of circuit under test, the selection time sequence allowance forms set of paths G to be measured lower than 20% path;

(2) analyze the aging compatibility relation between each path to be measured in described set of paths G to be measured, described set of paths G to be measured is approximately subtracted by the aging rule that approximately subtracts, the described aging rule that approximately subtracts is: for path A to be measured and path B to be measured, if the logical device of path A to be measured is the subset of path to be measured B logical device, claiming that path A to be measured is aging is contained in path B to be measured, described path A to be measured is deleted from described set of paths G to be measured, and remaining path to be measured forms aging character way set T;

Step 2, keep having odd number time logic NOT in aging character way set T on each path to be measured, form the self-oscillation loop:

The logical device that (1) will form path to be measured is summarized as three classes, is respectively: logic NOT device, maskable logical device and indefinite form logical device;

(2) logical device in every path to be measured in the aging character way set T that is produced by step 1 is analyzed, if a. have odd number logic NOT device on this bar path to be measured, it is joined end to end, if b. have even number logic NOT device on this bar path to be measured, select an indefinite form logical device, it is set to the logic NOT function, then path to be measured is joined end to end, if c. have even number logic NOT device on this bar path to be measured, and there is not the indefinite form logical device, additionally increase a phase inverter in path to be measured, again path to be measured is joined end to end,

(3) input value of Logical gate making pin on path to be measured is set in aging character way set T, forms the self-oscillation loop;

Step 3, adopt the test method of generationing of stuck-at fault, generate test vector, excite self-oscillation loop, generation test level signal:

For each self-oscillation loop that is produced by step 2 structure, adopt the test method of generationing of stuck-at fault, generates corresponding burn-in test vector, assurance self-oscillation loop can be worth X with

Form propagate into the path tail end; Scanning element in multiplexing built-in self-test mechanism is applied to the burn-in test vector in the self-oscillation loop and goes, and excites the self-oscillation loop, produces the test level signal;

Step 4, by sample self-oscillation loop of counter, obtain the der alterungs-kennwert of circuit under test, tolerance circuit under test degree of aging:

(1) the test level signal that produces in the employing step 3 is as the trigger pip of aging character sampling; Output terminal in path to be measured, by counter, sampled in the self-oscillation loop, when the every generation in self-oscillation loop once by the saltus step of low level to high level, the value of counter adds 1, test duration is compared with the value of described counter obtained self-oscillating frequency, record described self-oscillating frequency as the der alterungs-kennwert T of circuit _Aging

(2) pass through above-mentioned der alterungs-kennwert T _AgingWith the standard value T that stores on sheet _FreshCompare, according to the degree of aging C of formula (1) counting circuit _Aging:

$C_{\mathrm{Aging}}=\frac{T_{\mathrm{Fresh}}-T_{\mathrm{Aging}}}{T_{\mathrm{Aging}}}---\left(1\right)$

Compared with the prior art, beneficial effect of the present invention is embodied in:

1, the test structure that adopts in the present invention " self-oscillation loop " is comprised of circuit inherent logic device, avoided extraneous factor and the process deviation interference to the circuit burn-in test in testing scheme in the past, make it possible to reflect accurately the actual degree of aging of circuit, have very strong authenticity;

2, the present invention adopts counter to come the sample circuit aging character, accurately the degree of aging of counting circuit; Improved in existing testing scheme can not precisive circuit degree of aging defective, for the protection of circuit ageing failure provides foundation accurately;

3, storage organization on the sweep test in built-in self-test (BIST) mechanism that the present invention is multiplexing and sheet, the cost with 20% has realized the test process aging to circuit, greatly reduces the test cost of circuit.

Description of drawings

Fig. 1 is specific embodiments figure of the present invention;

Fig. 2 is the path to be measured collection of S27 circuit;

Fig. 3 is the self-oscillation loop of P2 and P3 in S27 set of paths to be measured;

Fig. 4 is applying of burn-in test vector;

Fig. 5 is the quantification of circuit degree of aging;

Fig. 6 is a kind of aging character counter structure.

Embodiment

In conjunction with the S27 practical circuit in ISCAS ' 89benchmark, referring to Fig. 1, the present invention adopts burn-in test scheme as described below:

Step 1, according to correlativity between static timing analysis and path, the aging character way set T in selecting circuit:

(1) adopt static timing tool, analyze the sequential situation of circuit under test, the selection time sequence allowance forms set of paths G to be measured lower than 20% path.In integrated circuit, the data routing of different structure, its degree of aging are not identical yet.This programme is the every data paths in separation circuit at first, namely seeks every sequential path to be measured; According to the concrete structure of data routing, adopt static timing tool to analyze the sequential situation of every paths, choose time sequence allowance and form set of paths G to be measured lower than 20% data routing.

(2) analyze the aging compatibility relation between each path to be measured in set of paths G to be measured, set of paths G to be measured is approximately subtracted by the aging rule that approximately subtracts, the described aging rule that approximately subtracts is: for path A to be measured and path B to be measured, if the logical device of path A to be measured is the subset of path to be measured B logical device, claiming that path A to be measured is aging is contained in path B to be measured, path A to be measured is deleted from set of paths G to be measured, and remaining path to be measured has formed aging character way set T.In this rule, therefore the degree of aging that reflects path A to be measured due to can be complete to the burn-in test of path B to be measured, can omit path A burn-in test process to be measured.

Take the S27 circuit as example, Fig. 2 is for after peace treaty subtracts by analysis, the set of paths to be measured of S27 circuit, and this set has 6 aging sensitive features paths, i.e. P1 ~ P6.

Have odd number time logic NOT on each path to be measured in step 2, maintenance aging character way set T, form free-running loop:

The logical device that (1) will form path to be measured is summarized as three classes, is respectively: logic NOT device, maskable logical device and indefinite form logical device.The logic NOT device comprises phase inverter (NOT), Sheffer stroke gate (NAND), rejection gate (NOR); Such device has the function of logic NOT, can be translated into phase inverter by specific input pin setting; For example: an input pin of Sheffer stroke gate is fixed as at 1 o'clock, and the output valve of Sheffer stroke gate and the input value of another pin keep inverse state.Maskable patrol device comprised with door (AND) and or the door (OR); Can shield the normal logic function of such device by specific input pin setting, become transmission gate; For example: will be fixed as at 1 o'clock with an input pin of door, identical with the input value of the output valve of door and another pin, its logical and function conductively-closed.Indefinite form is patrolled device and is comprised XOR gate (XOR) and same or door (XNOR); Namely such device can be converted into the logic NOT device by specific input pin design, can be translated into transmission gate again; For example, if an input pin of XOR gate is fixed as 1, it becomes phase inverter, if an one input pin is fixed as 0, it becomes transmission gate.

(2) logical device in every path to be measured in the aging character way set T that is produced by step 1 is analyzed, guaranteed to have on path to be measured odd number time logic NOT.Only have when the number of times of logic NOT on a path to be measured is odd number, just can make input signal X with

Form propagate into output terminal.Concrete analytic process is: if having odd number logic NOT device on this bar of a. path to be measured, it is joined end to end, if b. have even number logic NOT device on this bar path to be measured, select an indefinite form logical device, it is set to the logic NOT function, then path to be measured is joined end to end, if c. have even number logic NOT device on this bar path to be measured, and there is not the indefinite form logical device, additionally increase a phase inverter in path to be measured, then path to be measured is joined end to end;

(3) input value of Logical gate making pin on path to be measured is set in aging character way set T, according to the transformation rule of three class devices described in step 2 (1), the input value of Logical gate making pin is set, form the self-oscillation loop.

Fig. 3 has showed in S27 circuit set of paths to be measured (Fig. 2), the self-oscillation loop that feature path P2 and P3 form after processing through structure.

Step 3, adopt the test method of generationing of stuck-at fault, generate test vector, excite self-oscillation loop, generation test level signal:

For each self-oscillation loop that is produced by step 2 structure, adopt the test method of generationing of stuck-at fault, generates corresponding burn-in test vector, assurance self-oscillation loop can be worth X with Form propagate into the path tail end; Scanning element in multiplexing built-in self-test mechanism is applied to the burn-in test vector in the self-oscillation loop and goes, and excites the self-oscillation loop, produces the test level signal;

Because every self-oscillation loop all can sensitization, therefore, can directly adopt the test method of generationing in the stuck-at fault test, generate corresponding burn-in test vectorial.For example, after in Fig. 3, two paths to be measured generated through test, the test vector of generation was: P2 (1XX10X0), P3 (0XX001X).Fig. 4 is the schematic diagram that the burn-in test vector applies.Different being of the burn-in test of integrated circuit and stuck-at fault test, burn-in test need to keep a path to be measured to be in the self-oscillation state in a regular length test duration section, namely keeps the test vector in scan chain constant.Therefore, need to adopt clock controller, the vector of gated sweep unit applies process.

Step 4, by sample self-oscillation loop of counter, obtain the der alterungs-kennwert of circuit under test, tolerance circuit under test degree of aging:

(1) the test level signal that produces in the employing step 3 is as the trigger pip of aging character sampling; Output terminal in path to be measured, by counter, sampled in the self-oscillation loop, when the every generation in self-oscillation loop once by the saltus step of low level to high level, the value of counter adds 1, test duration is compared with the value of described counter obtained self-oscillating frequency, record described self-oscillating frequency as the der alterungs-kennwert T of circuit _AgingShow as the increase of circuit time delay in the circuit level due to aging character.In order to quantize aging character, the present invention adopts counter that the self-oscillating frequency in path to be measured is sampled, as shown in Figure 5.This counter is connected to the output terminal in path to be measured.The level signal that produces on the self-oscillation loop is as the trigger pip of aging character counter.Two cycles of the every operation in self-oscillation loop produce a signal saltus step, and the aging character counter also can once sampling.Fig. 6 is a kind of implementation structure of Counter of the present invention.This counter is to adopt reducible asynchronous counter mechanism to realize, the oscillator signal of self-oscillation loop generation is connected to the clock end of counter; Before the test beginning, reseting port (CLR) is logical one, carries out counter O reset, and after beginning, reseting port keeps logical one; In test process, data terminal (J and K) signal remains logical one, and after test finished, the input signal of this port remained 0.

(2) pass through above-mentioned der alterungs-kennwert T _AgingWith the standard value T that stores on sheet _FreshCompare, according to the degree of aging C of formula (1) counting circuit _Aging:

The present invention uses for reference the characteristics of built-in self-test (BIST), and the eigenwert in the aging front path to be measured of storage is as standard value on sheet.Test after finishing compares the standard value of storing on the der alterungs-kennwert in the aging character counter and sheet, the actual degree of aging of tolerance circuit.

Due to twice circulation of the every operation in self-oscillation loop, produce the pulsatile once saltus step, therefore, the end value of aging character counter is 1/2 of the self-oscillation loop cycle of operation.If T is the test duration, T _FreshThe standard value of storing on sheet, T _AgingThe der alterungs-kennwert of catching in the aging character counter, D _FreshBe the time delay in the aging front path to be measured of circuit, D _AgingBe the time delay in the aging rear path to be measured of circuit, C _AgingCircuit degree of aging after expression quantizes.Exist following equation to set up:

T=2×T _Aging×D _Aging=2×T _Fresh×D _Fresh (1)

Can release the aging tolerance formula of circuit by formula (1):

$C_{\mathrm{Aging}}=\frac{D_{\mathrm{Aging}}-D_{\mathrm{Fresh}}}{D_{\mathrm{Fresh}}}=\frac{T_{\mathrm{Fresh}}-T_{\mathrm{Aging}}}{T_{\mathrm{Aging}}}---\left(2\right)$ 。

Claims (1)

1. circuit ageing testing method based on the self-oscillation loop is characterized in that operating as follows:

Step 1, according to correlativity between static timing analysis and path, choose the aging character way set T in circuit under test:

(1) adopt static timing tool, analyze the sequential situation of circuit under test, the selection time sequence allowance forms set of paths G to be measured lower than 20% path;

(2) analyze the aging compatibility relation between each path to be measured in described set of paths G to be measured, described set of paths G to be measured is approximately subtracted by the aging rule that approximately subtracts, the described aging rule that approximately subtracts is: for path A to be measured and path B to be measured, if the logical device of path A to be measured is the subset of path to be measured B logical device, claiming that path A to be measured is aging is contained in path B to be measured, described path A to be measured is deleted from described set of paths G to be measured, and remaining path to be measured forms aging character way set T;

Step 2, keep having odd number time logic NOT in aging character way set T on each path to be measured, form the self-oscillation loop:

The logical device that (1) will form path to be measured is summarized as three classes, is respectively: logic NOT device, maskable logical device and indefinite form logical device;

(2) logical device in every path to be measured in the aging character way set T that is produced by step 1 is analyzed, if a. have odd number logic NOT device on this bar path to be measured, it is joined end to end, if b. have even number logic NOT device on this bar path to be measured, select an indefinite form logical device, it is set to the logic NOT function, then path to be measured is joined end to end, if c. have even number logic NOT device on this bar path to be measured, and there is not the indefinite form logical device, additionally increase a phase inverter in path to be measured, again path to be measured is joined end to end,

(3) input value of Logical gate making pin on path to be measured is set in aging character way set T, forms the self-oscillation loop;

Step 3, adopt the test method of generationing of stuck-at fault, generate test vector, excite self-oscillation loop, generation test level signal:

For each self-oscillation loop that is produced by step 2 structure, adopt the test method of generationing of stuck-at fault, generates corresponding burn-in test vector, assurance self-oscillation loop can be worth X with

Form propagate into the path tail end; Scanning element in multiplexing built-in self-test mechanism is applied to the burn-in test vector in the self-oscillation loop and goes, and excites the self-oscillation loop, produces the test level signal;

Step 4, by sample self-oscillation loop of counter, obtain the der alterungs-kennwert of circuit under test, tolerance circuit under test degree of aging:

(1) the test level signal that produces in the employing step 3 is as the trigger pip of aging character sampling; Output terminal in path to be measured, by counter, sampled in the self-oscillation loop, when the every generation in self-oscillation loop once by the saltus step of low level to high level, the value of counter adds 1, test duration is compared with the value of described counter obtained self-oscillating frequency, record described self-oscillating frequency as the der alterungs-kennwert T of circuit _Aging

(2) pass through above-mentioned der alterungs-kennwert T _AgingWith the standard value T that stores on sheet _FreshCompare, according to the degree of aging C of formula (1) counting circuit _Aging:

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