CN102288903A - Test structure and method for interconnect resources in field programmable gate array (FPGA) - Google Patents
Test structure and method for interconnect resources in field programmable gate array (FPGA) Download PDFInfo
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Abstract
The invention relates to a test structure for interconnect resources in a field programmable gate array (FPGA). The test structure is a built-in self test structure; a test pattern generator (TPG), an output response analyser (ORA) and a circuit under test (CUT) are composed of internal resources of the FPGA; and the whole test structure is realized by writing a test configuration program for configuring the FPGA. A test method for the interconnect resources in the FPGA comprises the following six steps of: 1, arranging configuration logic blocks (CLBs); 2, configuring the TPG; 3, configuring the ORA; 4, configuring the CUT; 5, establishing a readback file by using an FPGA development platform, running the FPGA, reading analysis result data saved in a trigger in the ORA, and detecting and positioning a fault; and 6, repeating the steps 1-5, and completing four-time configuration of dual-long-line resources with CLB rank, intelligent long-line resources, dual-long-line resources without CLB rank and intelligent long-line resources and a final test according to the distribution of the CLBs and the type of the CUT.
Description
Technical field
The present invention relates to the test structure and the method for a kind of FPGA (Field Programmable Gate Array, field programmable gate array) intraconnections resource, belong to FPGA intraconnections technical field of measurement and test.
Background technology
The FPGA device inside has abundant interconnection resource.Spartan 3 series with Xilinx company are example, and its interconnection resource comprises long line resource, intelligent long line resource, two long line resource and direct interconnection line resource.
Long line resource comprises 24 long lines of horizontal direction and 24 long lines of vertical direction.These long line resources are two-way and run through entire device, and as shown in Figure 1, the output of per six interconnect block all links to each other with this interconnection resource.
Intelligent long line resource respectively has eight in the East, West, South, North direction, and is identical with the length of long line.Output every three interconnect block links to each other with this interconnection resource, and its structure as shown in Figure 2.Intelligent long line can only be driven by an end points, and the intelligent long line between the interconnect block of any one appointment all has 32.
Two long line resources respectively have eight on the East, West, South, North direction, on four direction, the output of per two interconnect block all links to each other with this interconnection resource, and its structure as shown in Figure 3.Compare with intelligent long line resource with long line resource, two long lines are convenient flexibly.
The direct interconnection resource be used for and adjacent interconnect block level, vertical and to the angular direction between connect, its structure is as shown in Figure 4.The direct interconnection resource is called " segmentation interconnection " structure again, is the consistent patented technology that adopts of the FPGA of Xilinx company family device.
The test of these interconnection resource middle or long line resources and direct interconnection line resource is relatively easy, and therefore, the emphasis of FPGA intraconnections resource testing and difficult point are two long lines and intelligent long line resource.
When the programmable links resource of FPGA device was tested, the fault type of consideration generally comprised following several: the line segment persistent fault; The line segment open fault; The line segment short trouble; Bridging fault between line segment.In addition, for bridging fault also supposition usually: have only between adjacent line segment bridging fault can take place; If between two non-conterminous line segments bridging fault takes place, then bridging fault all takes place in all adjacent segments between these two line segments (comprising this two line segments itself).For detecting test, allow multiple faults usually, and, adopt the single fault model usually for diagnostic test.
The programmable features of FPGA device makes when its internal resource is tested, within it portion at the tested logic of difference make up the built-in self-test structure (Built-in Self Test, BIST).Another benefit of utilizing BIST that the FPGA device is tested is, the test resource of built-in self-test is based upon on the identical architecture basics with the inner tested resource of FPGA, thereby can guarantee that test source and tested logic speed are synchronous, thereby realize the high precision performance test.In addition, utilize the built-in self-test technology that chip is tested the intellecture property that helps to protect kernel, so this method is used widely.The BIST test macro generally comprise test graph builder (Test Pattern Generation, TPG), circuit-under-test (Circuit Under Test, CUT), also comprise sometimes output response analyzer (Output Response Analysis, ORA).
The current FPGA intraconnections test modes that adopt the segmentation excitation realize test with the BIST structure more, and structure as shown in Figure 5.Each CLB 11 (configuration logic block, programmed logical module) is configured to the TPG and the ORA of specific quantity.TPG is from the starting point input stimulus of every line line segment to be measured, and ORA receives output signal from the mid point and the terminal point of line line segment to be measured, and analytic signal draws judged result.Because FPGA internal wiring resource extent is huge, so the mode of segmentation excitation will take a large amount of CLB 11 resources.When CLB 11 resources are not enough, the complete test of just having to repeatedly be configured to realize.Current approach needs tens of times even up to a hundred times more than mostly.Because the test duration of FPGA is almost completely depended on configured number, therefore, the test duration of this method is long, is unfavorable for practical application.
Summary of the invention
1, purpose: the object of the present invention is to provide a kind of test structure and method of FPGA intraconnections resource, it can detect and locate bridging fault between line segment persistent fault, line segment open fault, line segment short trouble and line segment in two long lines and the intelligent long line.
2, technical scheme:
1) test structure of a kind of FPGA intraconnections of the present invention resource, it is a kind of built-in self-test structure BIST, its test graph builder TPG, output response analyzer ORA and circuit-under-test CUT are made of the FPGA internal resource.This whole test structure will be realized by writing test configurations application configuration FPGA.The each row and column of FPGA respectively have several groups of TPG and ORA, and CUT is the interconnection resources that connects TPG and ORA.TPG is used to provide low level and high level pumping signal, and ORA is used to analyze the output response through these signals behind the circuit-under-test CUT.Every group of TPG and ORA are positioned at same programmed logical module CLB, and its quantity is determined by line number to be measured.For some row and column (as input/output port IOB) that does not have CLB, will in extra configuration, utilize the CLB resource of other row and column to test.Clock signal is provided by external clock.
Described test graph builder TPG is: be formed by connecting by 1 look-up table LUT and 1 trigger.Relation is therebetween: look-up table LUT and trigger are connected in series, and the output of trigger feeds back to look-up table LUT on the one hand as input, are transferred to tested line line segment on the other hand, are transferred to ORA simultaneously and import as it.
Described output response analyzer ORA is: be formed by connecting by 1 look-up table LUT and 1 trigger.Relation is therebetween: look-up table LUT and trigger are connected in series, and input end links to each other with the terminal point of CUT and the output of TPG.
Described circuit-under-test CUT is: the line line segment by same type is in series by switch matrix and revolution matrix.
2) method of testing of a kind of FPGA intraconnections of the present invention resource, this method will be tested the two long line resource of the ranks of the two long line resource of ranks that programmed logical module CLB is arranged in the on-site programmable gate array FPGA, the intelligent long line resource that the ranks of programmed logical module CLB are arranged, no programmed logical module CLB and the intelligent long line resource of not having the ranks of programmed logical module CLB respectively by four configurations.These method concrete steps are as follows:
Step 1: programmed logical module CLB layout.Get the CLB of equal number in each each column selection of row, its quantity is determined by line number to be measured.Do not conflict between each row of each row.
Step 2: configuration testing graphic generator TPG.The TPG of configuration equal number is with the excitation as each line resource and alignment resource in the CLB of each each row of row.Look-up table LUT in the TPG is configured to a not gate.The initial value of TPG internal trigger is set.One group is set to low level, and another group is set to high level, is respectively applied for adjacent two of excitation and treats profile section, makes all adjacent pumping signal differences for the treatment of profile section.
Step 3: configuration output response analyzer ORA.Dispose the output response of the ORA of equal number with each line resource of analysis and judgement and alignment resource at the CLB of each each row of row.Look-up table LUT in the ORA is configured to an XOR gate.The initial value that the ORA internal trigger is set is a low level.Signal behind the output process circuit-under-test CUT that is input as TPG of ORA and the direct output signal of TPG.Be that ORA will carry out the XOR processing to these two kinds of signals.When CUT broke down, the output of TPG will be inconsistent through the direct output signal of signal behind the CUT and TPG, then can obtain high level through behind the XOR, and transfer to flip/flops latch.
Step 4: configuration circuit-under-test CUT.By deploy switch matrix and revolution matrix, the line line segment of each each row same type of row is together in series, starting point connects TPG, and terminal point connects ORA.Separate between each row of each row.
Step 5: create the retaking of a year or grade file with the FPGA development platform, the operation FPGA that powers on reads the analysis result data of trigger storage among the ORA, detects and fault location.
Step 6: repeating step one is to step 5, adjust CLB position distribution and CUT type according to the survey resource, finish the two long line resource of ranks of the two long line resource of the ranks of CLB, the intelligent long line resource that the ranks of CLB are arranged, no CLB and four times of intelligent long line resource testing of not having the ranks of CLB and dispose and final test.
3, advantage and effect: the present invention can detect and locate bridging fault between line segment persistent fault, line segment open fault, line segment short trouble and line segment in two long lines and the intelligent long line.The present invention also greatly reduces the test configurations number of times in addition, has shortened the test duration.
Description of drawings
Fig. 1 is long line resource synoptic diagram;
Fig. 2 is intelligent long line synoptic diagram;
Fig. 3 is two long line resource synoptic diagram;
Fig. 4 is direct interconnection resources synoptic diagram;
Fig. 5 is a segmentation exciting test structural drawing;
Fig. 6 is an alignment section test b IST structural drawing;
Fig. 7 is a line section test b IST structural drawing;
Fig. 8 is the method for testing process flow diagram.
Symbol description is as follows among the figure:
1 test graph builder TPG; 2 output response analyzer ORA; 3 look-up table LUT; 4 triggers; 5 switch matrix; 6 south revolution matrixes; 7 north revolution matrixes; 8 west revolution matrixes; 9 east revolution matrixes; 10 circuit under test CUT; 11 programmed logical module CLB; The TPG test graph builder; ORA exports response analyzer; The CLB programmed logical module; The LUT look-up table.
Embodiment
XC3S400 type FPGA with Spartan 3 series of Xilinx company is an example.This type FPGA has 34 row, 32 row, and the input/output port IOB and the two row block RAMs (random access memory) of two row, two row are wherein arranged.In four corners of the world direction eight two long lines and intelligent long line are arranged respectively.Wherein, eastern line and the interlaced distribution of western line, southern line and the interlaced distribution of northern line.Alignment section test b IST structure as shown in Figure 6, line section test b IST structure is as shown in Figure 7.
1) test structure of a kind of FPGA intraconnections of the present invention resource, it is a kind of built-in self-test structure, its test graph builder TPG 1, output response analyzer ORA 2 and circuit-under-test CUT 10 are made of the FPGA internal resource.Whole test structure will be realized by writing test configurations application configuration FPGA.The each row and column of FPGA respectively have two groups of TPG 1 and ORA 2.CUT is the interconnection resources that connects TPG 1 and ORA 2.TPG 1 is used to provide low level and high level pumping signal, and ORA 2 is used to analyze the output response through circuit-under-test CUT 10 these signals of back.Two long lines and intelligent long line are separately tested, and during then each test configurations, every row and every row have 16 lines to be measured.Each TPG 1 is two with the line that ORA 2 can encourage and analyze, and each needs eight TPG 1 and ORA 2 then every row and every row.For some row and column (as input/output port IOB) that does not have CLB 11, will in extra configuration, utilize CLB 11 resources of other row and column to test.Clock signal is provided by external clock.
Described test graph builder TPG 1 is: be formed by connecting by 1 look-up table LUT 3 and 1 trigger 4.Relation is therebetween: look-up table LUT 3 is connected in series with trigger 4, and the output of trigger 4 feeds back to look-up table LUT 3 on the one hand as input, is transferred to circuit under test CUT 10 on the other hand, is transferred to ORA 2 simultaneously as its input.
Described output response analyzer ORA 2 is: be formed by connecting by 1 look-up table LUT 3 and 1 trigger 4.Relation is therebetween: look-up table LUT 3 is connected in series with trigger 4, and input end links to each other with the terminal point of CUT 10 and the output of TPG 1.
Described circuit-under-test CUT is: the line line segment by same type is in series for 7 gusts by switch matrix 5 and east revolution matrix 9, west revolution matrix 8, south revolution matrix 6 and north revolution square.
2) method of testing of a kind of FPGA intraconnections of the present invention resource, this method will be tested two long line resource that CLB 11 ranks are arranged among the FPGA, the intelligent long line resource that the two long line resource of the intelligent long line resource of CLB 11 ranks, no CLB 11 ranks arranged and do not have CLB 11 ranks respectively by four configurations.These method concrete steps are as follows:
Step 1: CLB 11 layouts.For the two long line resource that CLB 11 ranks are arranged, choose the 1st row (except the input and output IOB and two row block RAMs of two row, two row, be 32 row 28 row) the two long line resources (being the two long line resource of south orientation and north orientation) of row that are used to test 1 to 28 row to 3,4 liang of capable CLB 11 of 1,2 liang of row of the 26th row and 27,28 row, the 3rd 27, the 28 row CLB 11 that walk to 1,2 liangs of row of 32 row and 1,2 liang of row be used to test 1 to 32 row the two long line resources of row (be east orientation with western to two long line resource); For the intelligent long line resource that CLB 11 ranks are arranged, choose the intelligent long line resource of row that the 1st row are used to test 1 to 28 row to 3,4 liang of capable CLB 11 of 1,2 liang of row of the 26th row and 27,28 row, the 3rd walks to 1,2 liangs of row of 32 row and 27,28 row CLB 11 of 1,2 liang of row are used to test 1 to the 32 intelligent long line resource of row of going; Two long line resource for no CLB 11 ranks, 3,4 liang of capable CLB 11 that choose the 1st row, 3 row, 27 row and 28 row are used to test the two long line resources of row of two row IOB and two row block RAMs, and 1,2 liang of row CLB 11 of the 1st row and 32 row is used to test the two long line resources of row of two row IOB; Two long line resource for no CLB 11 ranks, 1, the 2 liang of capable CLB 11 that chooses the 2nd row, 5 row, 24 row and 27 row are used to test the intelligent long line resource of row of two row IOB and two row block RAMs, and 1,2 liangs of row CLB 11 of the 3rd row and 30 row are used to test the two intelligent long line resources of row of going IOB;
Step 2: configuration TPG 1.Two groups of TPG 1 of configuration in CLB 11 of each each row of row, four every group, respectively as the excitation of each line resource and alignment resource.Every group of TPG 1 is arranged in same CLB 11, and the LUT 3 in the TPG 1 is configured to a not gate.The initial value of TPG 1 internal trigger 4 is set.One group is set to low level, and another group is set to high level, is respectively applied for adjacent two of excitation and treats profile section.Two groups of TPG 1 are arranged in adjacent CLB 11, make all adjacent pumping signal differences for the treatment of profile section.
Step 3: configuration ORA 2.Two groups of ORA 2 of configuration in the CLB 11 of each each row of row, four every group, with the output response of each line resource of analysis and judgement and alignment resource.LUT 3 in the ORA 2 is configured to an XOR gate.The initial value that ORA 2 internal triggers 4 are set is a low level.The output that is input as TPG 1 of ORA 2 is through signal behind the CUT 10 and the direct output signal of TPG 1.Be that ORA 2 will carry out the XOR processing to these two kinds of signals.When CUT 10 broke down, the output of TPG 1 will be inconsistent through the direct output signal of signal behind the CUT 10 and TPG 1, then can obtain high level through behind the XOR, and transfer to trigger 4 and latch.
Step 4: configuration CUT 10.Turn round 7 gusts of squares by deploy switch matrix 5 and east revolution matrix 9, western revolution matrix 8, south revolution matrix 6 and north, the line line segment of each each row same type of row (two long line resources and intelligent long line resource) is together in series, starting point connects TPG 1, and terminal point connects ORA 2.Separate between each row of each row.
Step 5: create the retaking of a year or grade file with the FPGA development platform, the operation FPGA that powers on reads the analysis result data of trigger 4 storages among the ORA 2, detects and fault location.
Step 6: repeating step one is to step 5, adjust CLB 11 position distribution and CUT 10 types according to the survey resource, finish the two long line resource of ranks of the two long line resource of the ranks of CLB 11, the intelligent long line resource that the ranks of CLB 11 are arranged, no CLB 11 and four times of intelligent long line resource testing of not having the ranks of CLB 11 and dispose and final test.
Claims (2)
1. the test structure of a FPGA intraconnections resource, it is characterized in that: it is a kind of built-in self-test structure BIST, its test graph builder TPG, output response analyzer ORA and circuit-under-test CUT are made of the on-site programmable gate array FPGA internal resource, and this whole test structure will be realized by writing test configurations application configuration FPGA; The each row and column of FPGA respectively have several groups of TPG and ORA, and CUT is the interconnection resources that connects TPG and ORA; TPG is used to provide low level and high level pumping signal, and ORA is used to analyze the output response through these signals behind the circuit-under-test CUT; Every group of TPG and ORA are positioned at same programmed logical module CLB, and its quantity is determined by line number to be measured; For the row and column that does not have CLB, will in extra configuration, utilize the CLB resource of other row and column to test, clock signal is provided by external clock;
Described test graph builder TPG is: be formed by connecting by 1 look-up table LUT and 1 trigger, look-up table LUT and trigger are connected in series, the output of trigger feeds back to look-up table LUT on the one hand as input, be transferred to tested line line segment on the other hand, be transferred to ORA simultaneously and import as it;
Described output response analyzer ORA is: be formed by connecting by 1 look-up table LUT and 1 trigger, look-up table LUT and trigger are connected in series, and input end links to each other with the terminal point of circuit-under-test CUT and the output of test graph builder TPG;
Described circuit-under-test CUT is: the line line segment by same type is in series by switch matrix and revolution matrix.
2. the method for testing of a FPGA intraconnections resource is characterized in that: this method will be tested the two long line resource of the ranks of the two long line resource of ranks that programmed logical module CLB is arranged in the on-site programmable gate array FPGA, the intelligent long line resource that the ranks of programmed logical module CLB are arranged, no programmed logical module CLB and the intelligent long line resource of not having the ranks of programmed logical module CLB respectively by four configurations; These method concrete steps are as follows:
Step 1: programmed logical module CLB layout: get the programmed logical module CLB of equal number in each each column selection of row, its quantity determine by line number to be measured, and each does not conflict each row between being listed as;
Step 2: configuration testing graphic generator TPG: the test graph builder TPG of configuration equal number is with the excitation as each line resource and alignment resource in the programmed logical module CLB of each each row of row; Look-up table LUT in the test graph builder TPG is configured to a not gate; The initial of test graph builder TPG internal trigger is set, and one group is set to low level, and another group is set to high level, is respectively applied for adjacent two of excitation and treats profile section, makes all adjacent pumping signal differences for the treatment of profile section;
Step 3: dispose output response analyzer ORA: dispose the output response of the output response analyzer ORA of equal number at the programmed logical module CLB of each each row of row with each line resource of analysis and judgement and alignment resource; Look-up table LUT in the output response analyzer ORA is configured to an XOR gate; The initial value that output response analyzer ORA internal trigger is set is a low level, signal behind the output process circuit-under-test CUT that is input as test graph builder TPG of output response analyzer ORA and the direct output signal of test graph builder TPG are promptly exported response analyzer ORA and will be carried out the XOR processing to these two kinds of signals; When circuit-under-test CUT broke down, signal behind the output of the test graph builder TPG process circuit-under-test CUT and the direct output signal of test graph builder TPG will be inconsistent, then can obtain high level through behind the XOR, and transfer to flip/flops latch;
Step 4: configuration circuit-under-test CUT: by deploy switch matrix and revolution matrix, the line line segment of each each row same type of row is together in series, starting point connects test graph builder TPG, and terminal point connects output response analyzer ORA, and is separate between each row of each row;
Step 5: create the retaking of a year or grade file with the on-site programmable gate array FPGA development platform, the operation FPGA that powers on reads the analysis result data of trigger storage among the output response analyzer ORA, detects and fault location;
Step 6: repeating step one is to step 5, adjust programmed logical module CLB position distribution and circuit-under-test CUT type according to the survey resource, finish the two long line resource of ranks of the two long line resource of the ranks of programmed logical module CLB, the intelligent long line resource that the ranks of programmed logical module CLB are arranged, no programmed logical module CLB and four times of intelligent long line resource testing of not having the ranks of programmed logical module CLB and dispose and final test.
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| CN109444630A (en) * | 2018-11-05 | 2019-03-08 | 西安智多晶微电子有限公司 | FPGA routing cell tests structure and method |
| CN109815583A (en) * | 2018-02-27 | 2019-05-28 | 上海安路信息科技有限公司 | The wiring method and test method of the interconnection resource of FPGA |
| CN110308381A (en) * | 2019-05-29 | 2019-10-08 | 深圳市紫光同创电子有限公司 | A kind of built-in self-test method and system of FPGA input and output logic module |
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| CN104281508A (en) * | 2013-07-11 | 2015-01-14 | 京微雅格（北京）科技有限公司 | Test method of interconnected wire stuck-at fault of field-programmable gate array (FPGA) |
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| CN109444630B (en) * | 2018-11-05 | 2020-12-01 | 西安智多晶微电子有限公司 | FPGA wiring unit test structure and method |
| CN111812490A (en) * | 2019-04-12 | 2020-10-23 | 上海复旦微电子集团股份有限公司 | Method for testing signal transmission delay in FPGA chip |
| CN110308381A (en) * | 2019-05-29 | 2019-10-08 | 深圳市紫光同创电子有限公司 | A kind of built-in self-test method and system of FPGA input and output logic module |
| CN111722097A (en) * | 2020-07-01 | 2020-09-29 | 无锡中微亿芯有限公司 | Multi-die FPGA with interconnection test function |
| CN111722097B (en) * | 2020-07-01 | 2022-02-18 | 无锡中微亿芯有限公司 | Multi-die FPGA with interconnection test function |
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