CN109445366A - A kind of screening test method of FPGA programmable logic resource - Google Patents
A kind of screening test method of FPGA programmable logic resource Download PDFInfo
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- CN109445366A CN109445366A CN201811616300.7A CN201811616300A CN109445366A CN 109445366 A CN109445366 A CN 109445366A CN 201811616300 A CN201811616300 A CN 201811616300A CN 109445366 A CN109445366 A CN 109445366A
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0428—Safety, monitoring
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- G—PHYSICS
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
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Abstract
The present invention relates to a kind of screening test methods of FPGA programmable logic resource, include the following steps: (1) programmable logic resource Functional Design；(2) look-up table test input vector design；(3) rtl code emulates；(4) test result analysis circuit design；(5) module duplication and output logical design.The screening test method of FPGA programmable logic resource provided by the invention solves the disadvantage that ATE testing expense is high, measuring technology difficulty is big using the test method based on BIST.Whole LUT module and DFF module can be covered by only needing two to assemble code, improve testing efficiency.This method takes full advantage of the programmable feature of fpga chip and chip interior channel resource abundant and embedded memory cell (Block Random Access Memory, BRAM).This method implementation steps are simple, portable strong, have certain engineering application value.
Description
Technical field
The present invention relates to a kind of screening test methods of FPGA programmable logic resource, belong to technical field of integrated circuits.
Background technique
Programmable logic resource is field programmable gate array (Field Programmable Gate Arrays, FPGA)
A kind of internal most important, most basic stone, major function is that most basic logical operation sum number is provided for digital display circuit
According to store function.A programmed logical modules hundreds of or even up to ten thousand, programmable logic resource quantity are generally integrated in FPGA
Huge, the limitation of tested person time and testing cost, FPGA manufacturer will not generally carry out general commercial fpga chip comprehensive
Functional test.In highly reliable application field, user needs to carry out the additional screening test to the commercial chip of buying, whole to meet
Use reliability requirement of the machine to component.
Researchers once designed various structures: based on transfer tube, NAND gate, variable connector (multiplexer, MUX),
Look-up table (Look-Up Table, LUT) and multi input gate array etc..Comprehensively consider function, chip area, speed and power consumption etc.
Factor, what is generallyd use in FPGA at present is the logic module based on LUT structure.
Look-up table (LUT) can be considered as the memory array with 1 output end, and the address wire of memory is exactly
The input signal cable of LUT, a LUT with n input just correspond to the memory of 2n storage unit.In FPGA, LUT is usual
It is realized by SRAM memory cell, the truth table of logic function is written in LUT user by way of programming, it can be achieved that any n
The combination logic function of input.
Currently, programmed logical module mainly passes through ATE(Automatic Test Equipment, auto testing instrument) it surveys
Commissioning stage carries out functional test, and ATE equipment is analyzed by exporting result to test to fpga chip input test vector sum,
To diagnose FPGA internal fault.There are two main problems for ATE test method:
(1) it incurs great expense and purchases or rent ATE equipment, and need to develop the specific ATE test program of design and specially
Test circuit board, while also chip testing socket (socket) is used, this increases user to a certain extent and needs
The cost to be born.
(2) being continuously increased with FPGA integrated level, chip-scale is increasing, and encapsulates I/O port number and be limited, benefit
The difficulty for carrying out spreadability test to whole programmable logic resources with ATE equipment is increasing.
Summary of the invention
The invention solves technical problems to be: the shortcomings that overcoming above-mentioned technology, provides a kind of based on built-in self-test
The FPGA programmable logic resource screening test method of (Built-in Self Test, BIST).
In order to solve the above-mentioned technical problem, technical solution proposed by the present invention is: a kind of FPGA programmable logic resource
Screening test method, includes the following steps:
(1) programmable logic resource Functional Design；Configure following two groups of functional circuits: 1) by whole look-up tables of tested chip
It is configured to the XOR logic door of n input；2) whole look-up tables of tested chip are configured to the same or logic gate of n input
Structure；
(2) look-up table test input vector design；Look-up table test input vector design passes through counter by clock, reset signal
It generates；
(3) rtl code emulates；Expected correct output is obtained as a result, generation FPGA is embedding by ModelSim behavioral scaling
Initialization ROM file needed for entering formula memory module；By the corresponding BRAM IP kernel module of exampleization, complete to correct result
Storage；
(4) test result analysis circuit design；After test starts, believed by clock address corresponding with reset signal generation
Number, and then read the storing data of appropriate address in BRAM module；By the comparison with programmable logic resource calculated result, sentence
Whether disconnected function is correct；
(5) module duplication and output logical design；Example Verilog function code is repeated, while to each programmable logic mould
The output result of block carries out xor operation, once so that mistake occurs in certain tested module, output signal is got higher by low, and is lighted
Status indicator lamp reminds user.
Above scheme further improvement is that in the step (1), LUT's inside each programmed logical module
Output is all deposited by programmable trigger device, and the output after deposit is cascaded to next stage LUT's by inner passage
On the port lut_a, the output of the last one programmable trigger device is connected to module-external.
The screening test method of FPGA programmable logic resource provided by the invention, using the test side based on BIST
Method solves the disadvantage that ATE testing expense is high, measuring technology difficulty is big.Whole LUT modules can be covered by only needing two to assemble code
With DFF module, testing efficiency is improved.This method takes full advantage of the programmable feature of fpga chip and chip interior is rich
Rich channel resource and embedded memory cell (Block Random Access Memory, BRAM).This method implements step
It is rapid simple, it is portable strong, there is certain engineering application value.
Detailed description of the invention
The present invention will be further explained below with reference to the attached drawings.
Fig. 1 is a preferred embodiment screening test implementing procedure of the invention.
Fig. 2 is the structural schematic diagram of BLE.
Fig. 3 is test schematic block circuit diagram.
Fig. 4 is programmable logic resource Functional Design block diagram.
Specific embodiment
Embodiment
The screening test method of the FPGA programmable logic resource of the present embodiment is as shown in Figure 1, include the following steps:
(1) programmable logic resource Functional Design；
(2) look-up table test input vector design；
(3) rtl code emulates；
(4) test result analysis circuit design；
(5) module duplication and output logical design.
Traversal test is the survey for inputting all possible test and excitation to circuit-under-test, and observing circuit-under-test output result
Method for testing.If circuit-under-test is combinational logic circuit, it is assumed that share n data in pin, then test vector has 2n kind.If
The unit time for testing and completing observation every time is t, then completing the total time that test needs is 2nt.And for sequence circuit,
Then testing total time can also be longer.Therefore, traversal test applies in general to the less circuit of input terminal.Programmable logic is provided
For source, which needs to consume a large amount of testing time, and testing cost is high.
Have the characteristics that reconfigurability in view of fpga chip, can be used built-in self-test (Built-in Self Test,
BIST method) detects the failure of FPGA, is diagnosed.By programming by a part of logical resource of FPGA be used as test to
It measures generator (Test Pattern Generation, TPG), TPG can be tested module (Block Under Test, BUT)
There is provided excitation input, another part logical resource be used as output response analyzer (Output Response Analyzer,
ORA), ORA can the output result to BUT analyse and compare, and then judge BUT with the presence or absence of failure.Therefore, the present invention draws
The test thinking based on BIST is entered.
Basic logic unit (Basic Logic Element, BLE) is the minimum programmable unit in FPGA, Mei Geke
Programmed logic module includes multiple BLE.The basic structure schematic diagram of BLE is as shown in Figure 2.
Each BLE includes n input look-up table, one by the programmable trigger device of clock control, carry chain etc..With four
It inputs for look-up table, can realize that any combination of 4 input signals (lut_a, lut_b, lut_c, lut_d) or timing are patrolled
Collect circuit function.Look-up table logical function truth table is stored in 16 sram cells, and the combination of any four input may be implemented
Logic function.For depositing logic, the output of look-up table is exported by the deposit of programmable trigger device, and for combinational logic function
Can, the output of look-up table bypasses the output end that BLE is directly output to after programmable trigger device.
Programmable trigger device in BLE is d type flip flop (D-type Flip Flop, DFF), with data input pin
(in), clock end (clk), asynchronous resetting end (nclr), output end (out).Wherein, clock signal, asynchronous resetting signal can be with
From global clock network, ICR interconnection resource；Data input signal then derives from ICR interconnection resource.The output of programmable trigger device is also
The input terminal of the look-up table of BLE where it can directly be fed back to.
Since a n input LUT is equivalent to the memory with 2n storage unit, in order to cover whole LUT
Module and DFF module need to configure following two groups of functional circuits:
(1) whole look-up tables of tested chip are configured to the XOR logic door of n input, is with four output look-up tables
The initialization value of example, 24 storage units is 16'b0110_1001_1001_0110, and 16 systems are expressed as 16'h6996.
(2) whole look-up tables of tested chip are configured to the same or logic gate structure of n input, with four output look-up tables
For, the initialization value of 24 storage units is 16'b1001_0110_0110_1001, and 16 systems are expressed as 16'h9669.
As shown in figure 3, look-up table test input vector design is generated by clock, reset signal by counter, thus
Number of pins needed for test can be substantially reduced.
For programmable logic resource Functional Design block diagram as shown in figure 4, inside each programmed logical module, LUT's is defeated
It is all deposited out by programmable trigger device, the output after deposit is cascaded to the lut_a of next stage LUT by inner passage
On port, the output of the last one programmable trigger device is connected to module-external.
After the operating mode and test input vector of programmable logic resource determine, so that it may pass through ModelSim behavior
Grade emulation obtains expected correct output as a result, initialization ROM file needed for generating FPGA embedded memory module in turn.
By the corresponding BRAM IP kernel module of exampleization, the storage to correct result can be completed.
After test starts, by clock address signal corresponding with reset signal generation, and then read in BRAM module
The storing data of appropriate address.Pass through the comparison with programmable logic resource calculated result, it can be determined that whether function is correct, into
And state (correct/error) is exported.Once there is mistake, shape in the calculated result of programmable logic resource in a certain period
State marking signal is got higher by low.
By repeating example Verilog function code, the resource utilization of programmed logical module can be made to reach or connect
Nearly 100%, while xor operation is carried out to the output result of each programmed logical module, once so that certain test module occurs
Mistake, output signal are got higher by low, and illuminating state indicator light reminds user.
The present invention is not limited to the above embodiment.All technical solutions formed using equivalent replacement, are all fallen within the present invention and wanted
The protection scope asked.
Claims (2)
1. a kind of screening test method of FPGA programmable logic resource, it is characterised in that include the following steps:
(1) programmable logic resource Functional Design；Configure following two groups of functional circuits: 1) by whole look-up tables of tested chip
It is configured to the XOR logic door of n input；2) whole look-up tables of tested chip are configured to the same or logic gate of n input
Structure；
(2) look-up table test input vector design；Look-up table test input vector design passes through counter by clock, reset signal
It generates；
(3) rtl code emulates；Expected correct output is obtained as a result, generation FPGA is embedding by ModelSim behavioral scaling
Initialization ROM file needed for entering formula memory module；By the corresponding BRAM IP kernel module of exampleization, complete to correct result
Storage；
(4) test result analysis circuit design；After test starts, believed by clock address corresponding with reset signal generation
Number, and then read the storing data of appropriate address in BRAM module；By the comparison with programmable logic resource calculated result, sentence
Whether disconnected function is correct；
(5) module duplication and output logical design；Example Verilog function code is repeated, while to each programmable logic mould
The output result of block carries out xor operation, once so that mistake occurs in certain tested module, output signal is got higher by low, and is lighted
Status indicator lamp reminds user.
2. the screening test method of FPGA programmable logic resource according to claim 1, it is characterised in that: the step
(1) in, the output of the LUT inside each programmed logical module all passes through programmable trigger device and is deposited, after deposit
Output is cascaded on the port lut_a of next stage LUT by inner passage, and the output of the last one programmable trigger device is connected to
Module-external.
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| CN110674608A (en) * | 2019-06-13 | 2020-01-10 | 深圳市芯天下技术有限公司 | Modeling method and system for NAND flash memory storage unit |
| CN111812490A (en) * | 2019-04-12 | 2020-10-23 | 上海复旦微电子集团股份有限公司 | Method for testing signal transmission delay in FPGA chip |
| CN112858892A (en) * | 2021-01-15 | 2021-05-28 | 胜达克半导体科技(上海)有限公司 | Method for realizing customized module on digital test channel based on FPGA |
| CN113985256A (en) * | 2021-11-01 | 2022-01-28 | 北京中科胜芯科技有限公司 | FPGA life test method |
| CN113985262A (en) * | 2021-11-01 | 2022-01-28 | 山东芯慧微电子科技有限公司 | Programming test method of LUT6 in FPGA |
| CN114117981A (en) * | 2022-01-26 | 2022-03-01 | 湖南泛联新安信息科技有限公司 | RTL (real time language) level logic partitioning method based on prior information |
| CN117033112A (en) * | 2023-08-07 | 2023-11-10 | 西安微电子技术研究所 | System-level DFT implementation method, system, equipment and medium |
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| CN114117981A (en) * | 2022-01-26 | 2022-03-01 | 湖南泛联新安信息科技有限公司 | RTL (real time language) level logic partitioning method based on prior information |
| CN117033112A (en) * | 2023-08-07 | 2023-11-10 | 西安微电子技术研究所 | System-level DFT implementation method, system, equipment and medium |
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