CN100549712C

CN100549712C - The method of testing of FPGA configurable logic block is finished in five configurations

Info

Publication number: CN100549712C
Application number: CNB2007100638883A
Authority: CN
Inventors: 文治平; 周涛; 杜忠; 陈雷; 李学武; 张帆; 刘增容; 张彦龙; 储鹏
Original assignee: China Aerospace Modern Electronic Co 772nd Institute; Mxtronics Corp
Current assignee: Beijing times people core technology Co., Ltd.; China Aerospace Modern Electronic Company 772nd Institute
Priority date: 2007-02-14
Filing date: 2007-02-14
Publication date: 2009-10-14
Anticipated expiration: 2027-02-14
Also published as: CN101038323A

Abstract

The method of testing of FPGA configurable logic block is finished in a kind of five configurations, its characteristics are: the sequential logical circuit and the combinational logic circuit of FPGA configurable logic block are combined test, arrange test resource by optimizing, intersect to use with or, the test vector of function such as XOR and the method for exhaustion, reduced the test configurations number of times; Used the technology of the snakelike one-dimensional array of cascade among the present invention, with all configurable logic blocks to be measured by satisfying test controllability and the observable requirement of the test test that is together in series, both simplified the design complexity, reduced the test input/output port again, and reached 100% test coverage, effectively reduced testing cost.

Description

The method of testing of FPGA configurable logic block is finished in five configurations

Technical field

The present invention relates to a kind of method of testing of fpga chip, particularly only just finish the method for testing of FPGA configurable logic block with five configurations.

Background technology

The prerequisite that FPGA is tested is that it is configured, and designs multiple test circuit and could realize Validity Test to FPGA through the process of repeatedly configuration-test.And the time cost of disposing a FPGA is more much more than applying a test vector, is to reduce configured number under the prerequisite that guarantees test coverage so improve the key of FPGA testing efficiency as far as possible.

Configurable logic block is basic functions unit among the FPGA, and the full test of configurable logic block is in crucial status in the FPGA measuring technology.At present, abroad the test of FPGA configurable logic block is studied, proposed configurable logic block is divided into the theory that sequential logic and combinational logic are tested respectively, this method configured number is more, used eight test configurations just to reach higher test coverage altogether, design realizes complicated, and test resource has been wasted in the measure that the division module is tested respectively.Domestic research in this field also is in the starting stage, and relevant achievement seldom.

Summary of the invention

The problem that the present invention solves is: reduce configured number as far as possible, a kind of method of testing of finishing the FPGA configurable logic block by five configurations is provided, this method intersects the test of combinational logic and sequential logic in conjunction with carrying out, guaranteed the requirement of test controllability and test observability when having saved configuration several times, overcome in the past test configurations often, test circuit structure complexity, inefficient shortcoming.

Technical solution of the present invention is: the method for testing of FPGA configurable logic block is finished in five configurations, comprises five configurations and test, wherein:

Configuration and testing procedure are as follows for the first time:

(1) configurable logic block is configured, the G look-up table is configured to XOR; The F look-up table is configured to XOR; The H look-up table is configured to equate logic that its input is introduced from the H1 Port Multiplier; The value of YQ trigger output H look-up table, the value of XQ trigger output DIN Port Multiplier;

(2) connect all configurable logic blocks, make it become an end to end snakelike one dimension matrix;

(3) matrix that has connected is applied test vector;

Configuration and testing procedure are as follows for the second time:

(4) configurable logic block is configured, the G look-up table is configured to together or logic; The F look-up table is configured to together or logic; The H look-up table is configured to equate logic that its input is introduced from the H1 Port Multiplier; The value of XQ trigger output H look-up table, the value of YQ trigger output DIN Port Multiplier;

(5) connect all configurable logic blocks, make it become an end to end snakelike one dimension matrix;

(6) matrix that has connected is applied test vector;

Configuration and testing procedure are as follows for the third time:

(7) configurable logic block is configured, the G look-up table is configured to equate logic, and input is introduced by the G1 end; The F look-up table is configured to equate logic, and its input is introduced by the F1 end; The G look-up table is configured to XOR, and its input is introduced from G look-up table, F look-up table (32), H1 Port Multiplier respectively; The value of YQ trigger output G look-up table, the value of XQ trigger output DIN Port Multiplier;

(8) connect all configurable logic blocks, make it become an end to end snakelike one dimension matrix;

(9) matrix that has connected is applied test vector;

The 4th configuration and testing procedure are as follows:

(10) configurable logic block is configured, the G look-up table is configured to equate logic, and input is introduced by the G1 end; The F look-up table is configured to equate logic, and input is introduced by the F1 end; The H look-up table is configured to together or logic, and its input is introduced from G look-up table, F look-up table, H1 Port Multiplier respectively; The value of YQ trigger output F look-up table, the value of XQ trigger output DIN Port Multiplier;

(11) connect all configurable logic blocks, make it become an end to end snakelike one dimension matrix;

(12) matrix that has connected is applied test vector;

The 5th configuration and testing procedure are as follows:

(13) configurable logic block is configured, the G look-up table is configured to equate logic, and input is introduced by the G1 end; The F look-up table is configured to equate logic, and input is introduced by the F1 end; The H look-up table is configured to equate logic that its input is introduced from the H1 Port Multiplier; The value of YQ trigger output G look-up table, the value of XQ trigger output F look-up table;

(14) connect all configurable logic blocks, make it become an end to end snakelike one dimension matrix;

(15) matrix that has connected is applied test vector.

In the described step (1), the result of G look-up table is through the output of Y Port Multiplier, the result of F look-up table is through the output of X Port Multiplier, the H look-up table is exported the value of H1 Port Multiplier through DY Port Multiplier and YQ trigger, H1 Port Multiplier gating C2, DIN Port Multiplier gating C1, the value of DIN Port Multiplier is through DX Port Multiplier and the output of XQ trigger, SR Port Multiplier gating C4, the value of SR Port Multiplier links to each other with the reset terminal reset of XQ trigger and YQ trigger, EC Port Multiplier gating C3, the value of EC Port Multiplier links to each other with the Enable Pin of XQ trigger with the YQ trigger.

In the described step (2), input end C3, the C4 of each configurable logic block, G2, G3, G4, F2, F3, F4 are connected in parallel as controlled public input end respectively, output terminal Y connects the G1 end of next stage configurable logic block, output terminal X connects the F1 end of next stage configurable logic block, output terminal YQ connects the C2 end of next stage configurable logic block, and output terminal XQ connects the C1 end of next stage configurable logic block.

In the described step (3), use the method for exhaustion to add test vector at the F of first order configurable logic block look-up table input end F1, F2, F3, F4, promptly input end F1, F2, every kind of possible logical combination of F3, F4 all occur once at least; Use the method for exhaustion to add test vector at G look-up table input end G1, G2, G3, G4; Need guarantee each once variation and once variation of from 1 to 0 of from 0 to 1 of experience of C1, C2 at input end C1, when C2 adds test vector, C3 is that the enable signal of XQ trigger and YQ trigger the time need be remained valid in test, C4 be reset signal when test with XQ trigger and YQ trigger reset.

In the described step (4), the result of G look-up table is through the output of Y Port Multiplier, the result of F look-up table is through the output of X Port Multiplier, the H look-up table is exported H1 Port Multiplier gating C3, DIN Port Multiplier gating C4 with the value of DIN Port Multiplier through DX Port Multiplier and XQ trigger, SR Port Multiplier gating C1, the value of SR Port Multiplier links to each other with the reset terminal reset of XQ trigger and YQ trigger, EC Port Multiplier gating C2, and the value of EC Port Multiplier links to each other with the Enable Pin of XQ trigger with the YQ trigger.

In the described step (5), input end C1, the C2 of each configurable logic block, G2, G3, G4, F2, F3, F4 are connected in parallel as controlled public input end respectively, output terminal Y connects the G1 end of next stage configurable logic block, output terminal X connects the F1 end of next stage configurable logic block, output terminal YQ connects the C4 end of next stage configurable logic block, and output terminal XQ connects the C3 end of next stage configurable logic block.

In the described step (6), use the method for exhaustion to add test vector at the F of first order configurable logic block look-up table input end F1, F2, F3, F4; Use the method for exhaustion to add test vector at G look-up table input end G1, G2, G3, G4; Need guarantee each once variation and once variation of from 1 to 0 of from 0 to 1 of experience of C3, C4 at input end C3, when C4 adds test vector, C2 is that the enable signal of XQ trigger and YQ trigger the time need be remained valid in test, C1 be reset signal when test with XQ trigger and YQ trigger reset.

In the described step (7), the result of G look-up table is through DX Port Multiplier and the output of XQ trigger, the result of F look-up table is through the output of X Port Multiplier, the H look-up table is exported Y Port Multiplier gating C1, DIN Port Multiplier gating C2 with the value of H1 Port Multiplier through the Y Port Multiplier, SR Port Multiplier gating C3, the value of SR Port Multiplier links to each other with the set set of XQ trigger and YQ trigger, EC Port Multiplier gating C4, and the value of EC Port Multiplier links to each other with the Enable Pin of XQ trigger with the YQ trigger.

In the described step (8), input end C3, the C4 of each configurable logic block is connected in parallel as controlled public input end respectively, output terminal Y connects the C1 end of next stage configurable logic block, output terminal X connects the F1 end of next stage configurable logic block, output terminal YQ connects the C2 end of next stage configurable logic block, and output terminal XQ connects the G1 end of next stage configurable logic block.

In the described step (9), the input end C1 of the input end F1 of the F look-up table of first order configurable logic block, the input end G1 of G look-up table and DIN Port Multiplier has constituted the test vector to the H look-up table jointly, adopts the method for exhaustion during test; At input end C2, test vector need be guaranteed once from 0 to 1 variation and once from 1 to 0 the variation of value experience of C2, C4 is that the enable signal of XQ trigger and YQ trigger the time need be remained valid in test, C3 be asserts signal when test with XQ trigger and the set of YQ trigger.

In the described step (10), the result of G look-up table is through the output of Y Port Multiplier, the result of F look-up table is through DY Port Multiplier and the output of YQ trigger, the result of H look-up table is through the output of X Port Multiplier, H1 Port Multiplier gating C4, DIN Port Multiplier gating C3, SR Port Multiplier gating C2, the value of SR Port Multiplier links to each other with the set end set of XQ trigger and YQ trigger, EC Port Multiplier gating C1, and the value of EC Port Multiplier links to each other with the Enable Pin of XQ trigger with the YQ trigger.

In the described step (11), input end C1, the C2 of each configurable logic block is connected in parallel as controlled public input end respectively, output terminal Y connects the G1 end of next stage configurable logic block, output terminal X connects the C4 end of next stage configurable logic block, output terminal YQ connects the F1 end of next stage configurable logic block, and output terminal XQ connects the C3 end of next stage configurable logic block.

In the described step (12), the input end C4 of the input end F1 of the F look-up table of first order configurable logic block, the input end G1 of G look-up table and H1 Port Multiplier has constituted the test vector to the H look-up table jointly, adopts the method for exhaustion during test; At input end C3, test vector need be guaranteed once from 0 to 1 variation and once from 1 to 0 the variation of value experience of C3, C1 is that the enable signal of XQ trigger and YQ trigger need be remained valid when test, and C2 is that asserts signal can be with XQ trigger and the set of YQ trigger when test.

In the described step (13), the result of G look-up table also exported from the Y Port Multiplier through the DY Port Multiplier output while, the result of F look-up table exports from the XQ trigger through the DX Port Multiplier, the H look-up table is exported the value of H1 Port Multiplier through the X Port Multiplier, H1 Port Multiplier gating C1, DIN Port Multiplier gating C2, SR Port Multiplier gating C3, the value of SR Port Multiplier (510) links to each other with the reset terminal reset end or the set end set of XQ trigger and YQ trigger, EC Port Multiplier gating C4, the value of EC Port Multiplier links to each other with the Enable Pin of XQ trigger with the YQ trigger.

In the described step (14), input end C3, the C4 of each configurable logic block is connected in parallel as controlled public input end respectively, output terminal X connects the C1 end of next stage configurable logic block, output terminal YQ connects the G1 end of next stage configurable logic block, and output terminal XQ connects the F1 end of next stage configurable logic block.

In the described step (15), at the F of first order configurable logic block look-up table input end F1, test vector need be guaranteed once from 0 to 1 variation and once from 1 to 0 the variation of value experience of F1; At G look-up table input end G1, test vector need be guaranteed once from 0 to 1 variation and once from 1 to 0 the variation of value experience of G1; When adding test vector, need guarantee input end C1 once from 0 to 1 variation and once from 1 to 0 the variation of C1 experience, C4 is that the enable signal of XQ trigger and YQ trigger the time need be remained valid in test, and C3 is that reset signal or asserts signal can be with XQ trigger and YQ trigger reset or set when test.

The present invention's advantage compared with prior art is: the method for existing configurable logic block test is that combinational logic and sequential logic are tested respectively, do not consider sequential logic during the test combinational logic, do not consider combinational logic during the test sequence logic, need eight kinds of configurations just can make the coverage rate of test reach 100% so at least.Among the present invention, the combinational logic of configurable logic block and the test of sequential logic are intersected in conjunction with carrying out, in same configuration, take into account the test of these two kinds of logics as far as possible.The number of times of configuration is compressed to five times, has improved testing efficiency.Secondly, configurable logic block is connected to an end to end snakelike one dimension matrix, each configurable logic block is accepted a local input from a last module, and be that next module produces a local output, simultaneously the input/output port amount of whole matrix significantly reduced in test controllability that has guaranteed each module and test observability ground.The present invention has reduced configured number, has simplified the design complexity, has saved the test input/output port again, has reached 100% test coverage, has effectively reduced testing cost.

Description of drawings

Fig. 1 is the basic structure synoptic diagram of FPGA;

Fig. 2 is the structural representation of configurable logic block;

Fig. 3 is the one-dimensional array cascade synoptic diagram of configurable logic block of the present invention;

Fig. 4 is the configuration schematic diagram first time of configurable logic block of the present invention;

Fig. 5 is the configuration schematic diagram second time of configurable logic block of the present invention;

Fig. 6 is the configuration schematic diagram for the third time of configurable logic block of the present invention;

Fig. 7 is the 4th configuration schematic diagram of configurable logic block of the present invention;

Fig. 8 is the 5th configuration schematic diagram of configurable logic block of the present invention.

Embodiment

The FPGA basic circuit structure as shown in Figure 1, wherein configurable logic block CLB61 is array distribution, interconnect line segment 62 and switch matrix SM63 are looped around around the configurable logic block, dispose by the user and realize various functions flexibly.As shown in Figure 2, configurable logic block 61 can be divided into combinational logic part combination logic and sequential logic part sequential logic according to its function, and combinational logic partly comprises four input (i.e. four input ends) look-up table G, four input look-up table F, four input Port Multiplier H1, three input look-up table H, two input Port Multiplier X, two input Port Multiplier Y; The sequential logic part mainly comprises four input Port Multiplier DIN, four input Port Multiplier SR, four input Port Multiplier EC, four input Port Multiplier DX, four input Port Multiplier DY, two input Port Multiplier KY, two input Port Multiplier EY, two input Port Multiplier KX, two input Port Multiplier EX, two output Port Multiplier SRX, two output Port Multiplier SRY, trigger XQ, trigger YQ.

Among the present invention the test of the test of the combinational logic of configurable logic block and sequential logic intersected and carry out, and flexible utilization switch matrix and interconnect line segment, be linked to be an end to end one dimension matrix as shown in Figure 3 with opening the configurable logic block level, form snakelike test channel and test.That each configurable logic block top is represented with the downward direction arrow among Fig. 3 is public input signal common signals, and these common signals are applied in each configurable logic block simultaneously; Series connection input signal series signals input imports from first configurable logic block CLB, and generation output is as the input signal of next stage configurable logic block CLB, the series connection signal sequence is delivered to last configurable logic block in the matrix, forms series connection output signal series signals output output.

The present invention divides and five times configurable logic block is configured, and concrete steps are as follows:

Configuration for the first time and test:

(1) configurable logic block is configured, G look-up table 11 is configured to XOR, and G look-up table 11 results are through 17 outputs of Y Port Multiplier; F look-up table 12 is configured to XOR, and F look-up table 12 results are through 15 outputs of X Port Multiplier; H look-up table 13 is configured to equate logic, the value of H1 Port Multiplier 14 is exported through DY Port Multiplier 18 and YQ trigger 113, H1 Port Multiplier 14 gating C2, DIN Port Multiplier 19 gating C1, the value of DIN Port Multiplier 19 is exported through DX Port Multiplier 16 and XQ trigger 112, SR Port Multiplier 110 gating C4, and the value of SR Port Multiplier 110 links to each other with the reset end of XQ trigger 112 and YQ trigger 113, EC Port Multiplier 111 gating C3, the value of EC Port Multiplier 111 links to each other with the Enable Pin of XQ trigger 112 with YQ trigger 113.

(2) connect all configurable logic blocks, make it become an end to end snakelike one dimension matrix.Input end C3, the C4 of each configurable logic block, G2, G3, G4, F2, F3, F4 are connected in parallel as controlled public input end respectively, output terminal Y connects the G1 end of next stage configurable logic block, output terminal X connects the F1 end of next stage configurable logic block, output terminal YQ connects the C2 end of next stage configurable logic block, and output terminal XQ connects the C1 end of next stage configurable logic block.

(3) matrix that has connected is applied test vector, use the method for exhaustion to add test vector at the F of first order configurable logic block look-up table 12 input end F1, F2, F3, F4, use the method for exhaustion to add test vector at G look-up table 11 input end G1, G2, G3, G4, need guarantee each once variation and once variation of from 1 to 0 of from 0 to 1 of experience of C1, C2 at input end C1, C2 test vector, C3 is that the enable signal of XQ trigger 112 and YQ trigger 113 need be remained valid when test, and C4 is that reset signal can reset XQ trigger 112 and YQ trigger 113 when test.

Configuration for the second time and test:

(4) configurable logic block is configured, G look-up table 21 is configured to together or logic, and G look-up table 21 results are through 27 outputs of Y Port Multiplier; F look-up table 22 is configured to together or logic, and the result of F look-up table 22 is through 25 outputs of X Port Multiplier; H look-up table 23 is configured to equate logic, and H look-up table 23 is exported the value of H1 Port Multiplier 24 through DX Port Multiplier 26 and XQ trigger 212; H1 Port Multiplier 24 gating C3, DI N Port Multiplier 29 gating C4, SR Port Multiplier 210 gating C1, the value of SR Port Multiplier 210 links to each other with the reset end of XQ trigger 212 and YQ trigger 213, EC Port Multiplier 211 gating C2, the value of EC Port Multiplier 211 links to each other with the Enable Pin of XQ trigger 212 with YQ trigger 213.

(5) connect all configurable logic blocks, make it become an end to end snakelike one dimension matrix.Input end C1, the C2 of each configurable logic block, G2, G3, G4, F2, F3, F4 are connected in parallel as controlled public input end respectively, output terminal Y connects the G1 end of next stage configurable logic block, output terminal X connects the F1 end of next stage configurable logic block, output terminal YQ connects the C4 end of next stage configurable logic block, and output terminal XQ connects the C3 end of next stage configurable logic block.

(6) matrix that has connected is applied test vector, at the look-up table F (22) of first order configurable logic block input end F1, F2, F3, F4 uses the method for exhaustion to add test vector, at look-up table G (21) input end G1, G2, G3, G4 uses the method for exhaustion to add test vector, at input end C3, the C4 test vector need be guaranteed C3, each once variation and once variation of from 1 to 0 of from 0 to 1 of experience of C4, C2 is that the enable signal of XQ trigger 212 and YQ trigger 213 need be remained valid when test, and C1 is that reset signal can reset XQ trigger 212 and YQ trigger 213 when test.

Dispose for the third time and test

(7) configurable logic block is configured, G look-up table 31 is configured to equate logic, and input is introduced by the G1 end, and the result of G look-up table 31 is through

DX Port Multiplier

36 and 312 outputs of XQ trigger; F look-up table 32 is configured to equate logic, and its input is introduced by the F1 end, and the result of F look-up table 32 is through 35 outputs of X Port Multiplier; G look-up table 33 is configured to XOR, H look-up table 33 is exported the value of H1 Port Multiplier 34 through Y Port Multiplier 37, H1 Port Multiplier 34 gating C1, DIN Port Multiplier 39 gating C2, SR Port Multiplier 310 gating C3, the value of SR Port Multiplier 310 links to each other with the set end of XQ trigger 312 and YQ trigger 313, EC Port Multiplier 311 gating C4, and the value of EC Port Multiplier 311 links to each other with the Enable Pin of XQ trigger 312 with YQ trigger 313.

(8) connect all configurable logic blocks, make it become an end to end snakelike one dimension matrix.Input end C3, the C4 of each configurable logic block is connected in parallel as controlled public input end respectively, output terminal Y connects the C1 end of next stage configurable logic block, output terminal X connects the F1 end of next stage configurable logic block, output terminal YQ connects the C2 end of next stage configurable logic block, and output terminal XQ connects the G1 end of next stage configurable logic block.

(9) matrix that has connected is applied test vector, the input end C1 of the input end F1 of the F look-up table 32 of first order configurable logic block, the input end G1 of G look-up table 31 and H1 Port Multiplier 34 has constituted the test vector at H look-up table 33 jointly, adopts the method for exhaustion during test; At input end C2, test vector need be guaranteed once from 0 to 1 variation and once from 1 to 0 the variation of value experience of C2, C4 is that the enable signal of XQ trigger 312 and YQ trigger 313 need be remained valid when test, and C3 is that asserts signal can be with

XQ trigger

312 and 313 set of YQ trigger when test.

The 4th configuration and test

(10) configurable logic block is configured, G look-up table 41 is configured to equate logic, and input is introduced by the G1 end, and the result of G look-up table 41 is through 47 outputs of Y Port Multiplier; F look-up table 42 is configured to equate logic, and input is introduced by the F1 end, and the result of F look-up table 42 is through

DY Port Multiplier

48 and 413 outputs of XQ trigger; H look-up table 43 is configured to together or logic, its input is introduced from G look-up table 41, F look-up table 42, H1 Port Multiplier 44 respectively, the result of H look-up table 43 is through 45 outputs of X Port Multiplier, H1 Port Multiplier 44 gating C4, DIN Port Multiplier 49 gating C3, SR Port Multiplier 410 gating C2, the value of SR Port Multiplier 410 links to each other with the set end of XQ trigger 412 and YQ trigger 413, EC Port Multiplier 411 gating C1, the value of EC Port Multiplier 411 links to each other with the Enable Pin of XQ trigger 412 with YQ trigger 413.

(11) connect all configurable logic blocks, make it become an end to end snakelike one dimension matrix.Input end C1, the C2 of each configurable logic block is connected in parallel as controlled public input end respectively, output terminal Y connects the G1 end of next stage configurable logic block, output terminal X connects the C4 end of next stage configurable logic block, output terminal YQ connects the F1 end of next stage configurable logic block, and output terminal XQ connects the C3 end of next stage configurable logic block.

(12) matrix that has connected is applied test vector, the input end C4 of the input end F1 of the F look-up table 42 of first order configurable logic block, the input end G1 of G look-up table 41 and H1 Port Multiplier 44 has constituted the test vector at H look-up table 43 jointly, adopts the method for exhaustion during test; At input end C3, test vector need be guaranteed once from 0 to 1 variation and once from 1 to 0 the variation of value experience of C3, C1 is that the enable signal of XQ trigger 412 and YQ trigger 413 need be remained valid when test, and C2 is that asserts signal can be with

XQ trigger

412 and 413 set of YQ trigger when test.

The 5th configuration and test

(13) configurable logic block is configured, G look-up table 51 is configured to equate logic, and input is introduced by the G1 end, and result's process DY Port Multiplier 58 outputs of G look-up table 51 are simultaneously also from 57 outputs of Y Port Multiplier; F look-up table 52 is configured to equate logic, and input is introduced by the F1 end, and result's process DX Port Multiplier 56 of F look-up table 52 is from 512 outputs of XQ trigger; H look-up table 53 is configured to equate logic, its input is introduced from H1 Port Multiplier 54, H look-up table 53 is exported the value of H1 Port Multiplier 54 through X Port Multiplier 55, H1 Port Multiplier 54 gating C1, DIN Port Multiplier 59 gating C2, SR Port Multiplier 510 gating C3, the value of SR Port Multiplier 510 links to each other with the reset end or the set of XQ trigger 512 and YQ trigger 513, EC Port Multiplier 511 gating C4, the value of EC Port Multiplier 511 links to each other with the Enable Pin of XQ trigger 512 with YQ trigger 513.

(14) connect all configurable logic blocks, make it become an end to end snakelike one dimension matrix.Input end C3, the C4 of each configurable logic block is connected in parallel as controlled public input end respectively, output terminal X connects the C1 end of next stage configurable logic block, output terminal YQ connects the G1 end of next stage configurable logic block, and output terminal XQ connects the F1 end of next stage configurable logic block.

(15) matrix that has connected is applied test vector, at the G of first order configurable logic block look-up table 52 input end F1, test vector need be guaranteed once from 0 to 1 variation and once from 1 to 0 the variation of value experience of F1; At G look-up table 51 input end G1, test vector need be guaranteed once from 0 to 1 variation and once from 1 to 0 the variation of value experience of G1; Need guarantee once from 0 to 1 variation and once from 1 to 0 the variation of C1 experience at input end C1 test vector; C4 is that the enable signal of XQ trigger 512 and YQ trigger 513 need be remained valid when test, and C3 is that reset signal or asserts signal can reset XQ trigger 512 and YQ trigger 513 or set when test.

Claims

1, the method for testing of FPGA configurable logic block is finished in five configurations, comprises five configurations and test, and wherein configuration and testing procedure are as follows for the first time:

Step 1 is configured configurable logic block, and G look-up table (11) is configured to XOR; F look-up table (12) is configured to XOR; H look-up table (13) is configured to equate logic that its input is introduced from H1 Port Multiplier (14); The value of YQ trigger (113) output H look-up table (13), the value of XQ trigger (112) output DIN Port Multiplier (19);

Step 2 connects all configurable logic blocks, makes it become an end to end snakelike one dimension matrix;

Step 3 applies test vector to the matrix that has connected;

Configuration and testing procedure are as follows for the second time:

Step 1 is configured configurable logic block, and G look-up table (21) is configured to together or logic; F look-up table (22) is configured to together or logic; H look-up table (23) is configured to equate logic that its input is introduced from H1 Port Multiplier (24); The value of XQ trigger (212) output H look-up table (23), the value of YQ trigger (213) output DIN Port Multiplier (29);

Step 3 applies test vector to the matrix that has connected;

Configuration and testing procedure are as follows for the third time:

Step 1 is configured configurable logic block, and G look-up table (31) is configured to equate logic, and input is introduced by the G1 end; F look-up table (32) is configured to equate logic, and its input is introduced by the F1 end; H look-up table (33) is configured to XOR, and its input is introduced from G look-up table (31), F look-up table (32) and H1 Port Multiplier (34) respectively; The value of XQ trigger (312) output G look-up table (31), the value of YQ trigger (313) output DIN Port Multiplier (39);

Step 3 applies test vector to the matrix that has connected;

The 4th configuration and testing procedure are as follows:

Step 1 is configured configurable logic block, and G look-up table (41) is configured to equate logic, and input is introduced by G1; F look-up table (42) is configured to equate logic, and input is introduced by the F1 end; H look-up table (43) is configured to together or logic, and its input is introduced from G look-up table (41), F look-up table (42) and H1 Port Multiplier (44) respectively; The value of YQ trigger (413) output F look-up table (42), the value of XQ trigger (412) output DIN Port Multiplier (49);

Step 3 applies test vector to the matrix that has connected;

The 5th configuration and testing procedure are as follows:

Step 1 is configured configurable logic block, and G look-up table (51) is configured to equate logic, and input is introduced by the G1 end; F look-up table (52) is configured to equate logic, and input is introduced by the F1 end; H look-up table (53) is configured to equate logic that its input is introduced from H1 Port Multiplier (54); The value of YQ trigger (513) output G look-up table (51), the value of XQ trigger (512) output F look-up table (52);

Step 3 applies test vector to the matrix that has connected.

2, the method of testing of FPGA configurable logic block is finished in five configurations according to claim 1, its feature exists: in the step 1 of the described configuration first time and testing procedure, the result of G look-up table (11) is through Y Port Multiplier (17) output, the result of F look-up table (12) is through X Port Multiplier (15) output, H look-up table (13) is exported the value of H1 Port Multiplier (14) through DY Port Multiplier (18) and YQ trigger (113), H1 Port Multiplier (14) gating C2, DIN Port Multiplier (19) gating C1, the value of DIN Port Multiplier (19) is through DX Port Multiplier (16) and XQ trigger (112) output, SR Port Multiplier (110) gating C4, the value of SR Port Multiplier (110) links to each other with the reset terminal reset of XQ trigger (112) with YQ trigger (113), EC Port Multiplier (111) gating C3, the value of EC Port Multiplier (111) links to each other with the Enable Pin of XQ trigger (112) with YQ trigger (113).

3, the method for testing of FPGA configurable logic block is finished in five configurations according to claim 1, its feature exists: in the step 2 of the described configuration first time and testing procedure, input end C3, the C4 of each configurable logic block, G2, G3, G4, F2, F3, F4 are connected in parallel as controlled public input end respectively, output terminal Y connects the G1 end of next stage configurable logic block, output terminal X connects the F1 end of next stage configurable logic block, output terminal YQ connects the C2 end of next stage configurable logic block, and output terminal XQ connects the C1 end of next stage configurable logic block.

4, the method for testing of FPGA configurable logic block is finished in five configurations according to claim 1, its feature exists: in the step 3 of the described configuration first time and testing procedure, use the method for exhaustion to add test vector at the F of first order configurable logic block look-up table (12) input end F1, F2, F3, F4, promptly input end F1, F2, every kind of possible logical combination of F3, F4 all occur once at least; Use the method for exhaustion to add test vector at G look-up table (11) input end G1, G2, G3, G4; Need guarantee each once variation and once variation of from 1 to 0 of from 0 to 1 of experience of C1, C2 at input end C1, when C2 adds test vector, C3 is that the enable signal of XQ trigger (112) and YQ trigger (113) need be remained valid when test, and C4 is that reset signal resets XQ trigger (112) and YQ trigger (113) when test.

5, the method of testing of FPGA configurable logic block is finished in five configurations according to claim 1, its feature exists: in the step 1 of the described configuration second time and testing procedure, the result of G look-up table (21) is through Y Port Multiplier (27) output, the result of F look-up table (22) is through X Port Multiplier (25) output, H look-up table (23) is exported the value of H1 Port Multiplier (24) through DX Port Multiplier (26) and XQ trigger (212), H1 Port Multiplier (24) gating C3, DIN Port Multiplier (29) gating C4, SR Port Multiplier (210) gating C1, the value of SR Port Multiplier (210) links to each other with the reset terminal reset of XQ trigger (212) with YQ trigger (213), EC Port Multiplier (211) gating C2, the value of EC Port Multiplier (211) links to each other with the Enable Pin of XQ trigger (212) with YQ trigger (213).

6, the method for testing of FPGA configurable logic block is finished in five configurations according to claim 1, its feature exists: in the step 2 of the described configuration second time and testing procedure, input end C1, the C2 of each configurable logic block, G2, G3, G4, F2, F3, F4 are connected in parallel as controlled public input end respectively, output terminal Y connects the G1 end of next stage configurable logic block, output terminal X connects the F1 end of next stage configurable logic block, output terminal YQ connects the C4 end of next stage configurable logic block, and output terminal XQ connects the C3 end of next stage configurable logic block.

7, the method for FPGA configurable logic block test is finished in five configurations according to claim 1, its feature exists: in the step 3 of the described configuration second time and testing procedure, use the method for exhaustion to add test vector at the F of first order configurable logic block look-up table (22) input end F1, F2, F3, F4; Use the method for exhaustion to add test vector at G look-up table (21) input end G1, G2, G3, G4; Need guarantee each once variation and once variation of from 1 to 0 of from 0 to 1 of experience of C3, C4 at input end C3, when C4 adds test vector, C2 is that the enable signal of XQ trigger (212) and YQ trigger (213) need be remained valid when test, and C1 is that reset signal resets XQ trigger (212) and YQ trigger (213) when test.

8, the method of testing of FPGA configurable logic block is finished in five configurations according to claim 1, its feature exists: in the step 1 of described configuration for the third time and testing procedure, the result of G look-up table (31) is through DX Port Multiplier (36) and XQ trigger (312) output, the result of F look-up table (32) is through X Port Multiplier (35) output, H look-up table (33) is exported the value of H1 Port Multiplier (34) through Y Port Multiplier (37), H1 Port Multiplier (34) gating C1, DIN Port Multiplier (39) gating C2, SR Port Multiplier (310) gating C3, the value of SR Port Multiplier (310) links to each other with the set set of XQ trigger (312) with YQ trigger (313), EC Port Multiplier (311) gating C4, the value of EC Port Multiplier (311) links to each other with the Enable Pin of XQ trigger (312) with YQ trigger (313).

9, the method for testing of FPGA configurable logic block is finished in five configurations according to claim 1, its feature exists: in the step 2 of described configuration for the third time and testing procedure, input end C3, the C4 of each configurable logic block is connected in parallel as controlled public input end respectively, output terminal Y connects the C1 end of next stage configurable logic block, output terminal X connects the F1 end of next stage configurable logic block, output terminal YQ connects the C2 end of next stage configurable logic block, and output terminal XQ connects the G1 end of next stage configurable logic block.

10, the method for testing of FPGA configurable logic block is finished in five configurations according to claim 1, its feature exists: in the step 3 of described configuration for the third time and testing procedure, the input end C1 of the input end F1 of the F look-up table (32) of first order configurable logic block, the input end G1 of G look-up table (31) and DIN Port Multiplier (34) has constituted the test vector to H look-up table (33) jointly, adopts the method for exhaustion during test; At input end C2, test vector need be guaranteed once from 0 to 1 variation and once from 1 to 0 the variation of value experience of C2, C4 is that the enable signal of XQ trigger (312) and YQ trigger (313) time need be remained valid in test, C3 be asserts signal when test with XQ trigger (312) and YQ trigger (313) set.

11, the method of testing of FPGA configurable logic block is finished in five configurations according to claim 1, its feature exists: in the step 1 of described the 4th configuration and testing procedure, the result of G look-up table (41) is through Y Port Multiplier (47) output, the result of F look-up table (42) is through DY Port Multiplier (48) and YQ trigger (413) output, the result of H look-up table (43) exports through X Port Multiplier (45), H1 Port Multiplier (44) gating C4, DIN Port Multiplier (49) gating C3, SR Port Multiplier (410) gating C2, the value of SR Port Multiplier (410) links to each other with the set end set of XQ trigger (412) and YQ trigger (413), EC Port Multiplier (411) gating C1, the value of EC Port Multiplier (411) links to each other with the Enable Pin of XQ trigger (412) with YQ trigger (413).

12, the method for testing of FPGA configurable logic block is finished in five configurations according to claim 1, its feature exists: in the step 2 of described the 4th configuration and testing procedure, input end C1, the C2 of each configurable logic block is connected in parallel as controlled public input end respectively, output terminal Y connects the G1 end of next stage configurable logic block, output terminal X connects the C4 end of next stage configurable logic block, output terminal YQ connects the F1 end of next stage configurable logic block, and output terminal XQ connects the C3 end of next stage configurable logic block.

13, the method for testing of FPGA configurable logic block is finished in five configurations according to claim 1, its feature exists: in the step 3 of described the 4th configuration and testing procedure, the input end C4 of the input end F1 of the F look-up table (42) of first order configurable logic block, the input end G1 of G look-up table (41) and H1 Port Multiplier (44) has constituted the test vector to H look-up table (43) jointly, adopts the method for exhaustion during test; At input end C3, test vector need be guaranteed once from 0 to 1 variation and once from 1 to 0 the variation of value experience of C3, C1 is that the enable signal of XQ trigger (412) and YQ trigger (413) need be remained valid when test, and C2 is that asserts signal can be with XQ trigger (412) and YQ trigger (413) set when test.

14, the method of testing of FPGA configurable logic block is finished in five configurations according to claim 1, its feature exists: in the step 1 of described the 5th configuration and testing procedure, the result of G look-up table (51) also exported from Y Port Multiplier (57) through DY Port Multiplier (58) the output while, the result of F look-up table (52) exports from XQ trigger (512) through DX Port Multiplier (56), H look-up table (53) is exported the value of H1 Port Multiplier (54) through X Port Multiplier (55), H1 Port Multiplier (54) gating C1, DIN Port Multiplier (59) gating C2, SR Port Multiplier (510) gating C3, the value of SR Port Multiplier (510) links to each other with the set end set of XQ trigger (512) and YQ trigger (513) respectively, EC Port Multiplier (511) gating C4, the value of EC Port Multiplier (511) links to each other with the Enable Pin of XQ trigger (512) with YQ trigger (513).

15, the method for testing of FPGA configurable logic block is finished in five configurations according to claim 1, its feature exists: in the step 2 of described the 5th configuration and testing procedure, input end C3, the C4 of each configurable logic block is connected in parallel as controlled public input end respectively, output terminal X connects the C1 end of next stage configurable logic block, output terminal YQ connects the G1 end of next stage configurable logic block, and output terminal XQ connects the F1 end of next stage configurable logic block.

16, the method for testing of FPGA configurable logic block is finished in five configurations according to claim 1, its feature exists: in the step 3 of described the 5th configuration and testing procedure, at the F of first order configurable logic block look-up table (52) input end F1, test vector need be guaranteed once from 0 to 1 variation and once from 1 to 0 the variation of value experience of F1; At G look-up table (51) input end G1, test vector need be guaranteed once from 0 to 1 variation and once from 1 to 0 the variation of value experience of G1; When adding test vector, need guarantee input end C1 once from 0 to 1 variation and once from 1 to 0 the variation of C1 experience, C4 is that the enable signal of XQ trigger (512) and YQ trigger (513) need be remained valid when test, and C3 is that reset signal or asserts signal reset XQ trigger (512) and YQ trigger (513) or set when test.