CN101682329B

CN101682329B - An integrated circuit with improved logic cells

Info

Publication number: CN101682329B
Application number: CN2008800000822A
Authority: CN
Inventors: 李枫峰; 周文
Original assignee: Agate Logic Beijing Inc
Current assignee: Agate Logic Beijing Inc
Priority date: 2008-01-30
Filing date: 2008-01-30
Publication date: 2012-06-27
Anticipated expiration: 2028-01-30
Also published as: WO2009100564A1; CN101682329A

Abstract

Integrated circuits with improved logic cells are provided. In one embodiment, an integrated circuit having a plurality of logic cells LC) (200) is provided, each LC (200) comprising: a lookup table (202) having a LUT output terminal; and, a first multiplexer (204): wherein, a first multiplexer input terminal is connected to a first input terminal (wlutin) of the LC (200), a second multiplexer input :erminal is connected to the LUT output terminal, a multiplexer output terminal is connected to a first output terminal (wlutout) of the LC (200), and a multiplexer select terminal is connected to a second input terminal (tsel) of the LC (200) so as to select which of the signals appearing at the first and second multiplexer input terminal to pass through; wherein, by coupling in chain the first input terminal of one C to the first output terminal of another LC, a WLUT chain is formed.

Description

A kind of integrated circuit with improved logical block

Technical field

The present invention relates to a kind of integrated circuit, relate in particular to field programmable gate array (FieldProgrammable Gate Array is called for short FPGA) logical block.

Background technology

FPGA is a kind of integrated circuit of being specified its function by FPGA user.FPGA generally includes a large amount of logical blocks.

Fig. 1 shows a kind of basic fpga logic unit (logic cell calls LC in the following text), and it comprises look-up table (look-up table, i.e. LUT) 102 and d type flip flop (DFF) 108.4 input LUT102 are shown having a configuration set storage unit, and totally 16, it can be configured or programme to be used to calculate the combination logic function of any 4 inputs.The details and the type of the present invention that note that this type programmed circuit are irrelevant, so not shown in Fig. 1.The output of LUT 102 not only is directly connected to the output of LC, but also sends into the D input end of d type flip flop 108, and the Q output of d type flip flop 108 can be used as another LC output.Trigger 108 can also have clock enable (enable) end, set (set) is held and/or reset (reset) end, these do not illustrate in the drawings yet.In this logical block, MUX (multiplexer, i.e. MUX) and other logic can be provided so that allow the Q output terminal of trigger is connected to some input end of LUT.In addition, the output signal of logical block can be routed to the input end of logical block via some general interconnection network, so that make up any given DLC(digital logic circuit).

This basic logic unit logically is complete.Yet, need a kind of for area and sequential is more efficient and/or layout is more friendly logical block and integrated circuit thereof.

Summary of the invention

Therefore, the purpose of this invention is to provide a kind of new LC, its can by the interconnection and the programming realize function, and area with the time is more efficient and/or layout more close friend.

According to first aspect, the invention provides a kind of integrated circuit with a plurality of logical blocks, each in said a plurality of logical blocks all comprises:

First input end, second input end, a plurality of the 3rd input end and first output terminal;

Look-up table with a plurality of LUT input ends, a plurality of LUT input ends are connected respectively to said a plurality of the 3rd input ends of said logical block; And, the LUT output terminal;

First MUX, it has the first MUX input end, the second MUX input end, selecting side and MUX output terminal; Wherein, The first MUX input end of first MUX is connected to first input end; The second MUX input end of first MUX is connected to the LUT output terminal; The MUX output terminal of first MUX is connected to first output terminal, and the selecting side is connected to second input end and can be used for being chosen in the first MUX input end and which signal of second MUX input end appearance passes through first MUX;

Wherein, form a WLUT (Wide LUT) chain through another first output terminal that is coupled to one first input end chain type in a plurality of logical blocks in a plurality of logical blocks.

According to second aspect, the invention provides a kind of integrated circuit with at least one first logical block and one second logical block,

First logical block comprises: has the LUT of LUT output terminal, has the circuit of first circuit input end and second circuit input end, and first input end; Wherein, the LUT output terminal of LUT is connected to first circuit input end, and first input end is connected to the second circuit input end;

Second logical block comprises: have the LUT and first output terminal of LUT output terminal, first output terminal is connected to the LUT output terminal;

First output terminal of second logical block is connected to the first input end of first logical block, has formed partner's logic thus.

According to the third aspect, a kind of integrated circuit with a plurality of logical blocks is provided.In said a plurality of logical block each all comprises:

First input end, second input end, the 3rd input end, a plurality of four-input terminal, first output terminal and second output terminal;

LUT has a plurality of LUT input ends that are connected respectively to a plurality of four-input terminals; And LUT output terminal;

First MUX, it has the first MUX input end, the second MUX input end, MUX selecting side and MUX output terminal; Wherein, The first MUX input end of first MUX is connected to first input end; The second MUX input end of first MUX is connected to the 3rd input end, and the MUX selecting side can be programmed any one in two signals that the first MUX input end that lets first MUX be delivered in first MUX and the second MUX input end occur;

Second MUX, it has the first MUX input end, the second MUX input end, MUX selecting side and MUX output terminal; Wherein, The first MUX input end of second MUX is connected to the MUX output terminal of first MUX; The second MUX input end of second MUX is connected to the LUT output terminal; The MUX selecting side of second MUX is connected to second input end, and the MUX output terminal of second MUX is connected to first output terminal;

Circuit, it has first circuit input end, second circuit input end and circuit output end; Wherein, first circuit input end is connected to the LUT output terminal, and the second circuit input end is connected to the 3rd input end;

The 3rd MUX, it has the first MUX input end, the second MUX input end, the 3rd MUX input end, MUX selecting side and MUX output terminal; Wherein, The first MUX input end of the 3rd MUX is connected to the LUT output terminal; The second MUX input end of the 3rd MUX is connected to the MUX output terminal of second MUX; The 3rd MUX input end of the 3rd MUX is connected to the circuit output end of said circuit, and the MUX selecting side can be programmed first, second any signal that occurs with the 3rd MUX input end to be delivered in the 3rd MUX.

Above-mentioned and other purposes of the present invention, feature and advantage will become through the following detailed description with reference to description of drawings obviously, and wherein, same Reference numeral is represented identical or similar elements.

Description of drawings

Fig. 1 has illustrated to comprise the basic logic unit of LUT and d type flip flop;

Fig. 2 has illustrated according to the logical block of first embodiment of the present invention;

Fig. 3 has illustrated according to the logical block of second embodiment of the present invention;

Fig. 4 has illustrated the WLUT chain that formed by the some logical blocks shown in Fig. 2;

Fig. 5 has illustrated the 5 input LUT (LUT5) that the WLUT chain by Fig. 4 forms;

Fig. 6 has illustrated the bus MUX that the WLUT chain by Fig. 4 forms;

Fig. 7 has illustrated the interconnection example between the logical block in the basic logic piece;

Fig. 8 has illustrated according to the logical block of the 3rd embodiment of the present invention;

Fig. 9 has illustrated according to the logical block of the 4th embodiment of the present invention;

Figure 10 has illustrated partner's logic of being formed by the some logical blocks shown in Fig. 8;

Figure 11 has illustrated another kind of partner's logic of being formed by the some logical blocks shown in Fig. 8;

Figure 12 has illustrated another partner's logic of being formed by the some logical blocks shown in Fig. 8;

Figure 13 has illustrated with 32 demoders of the formation of the partner's logic shown in Figure 10;

Figure 14 has illustrated in the basic logic piece, to be used for forming the LC layout of 32 demoders;

Figure 15 has illustrated how to select partner's logic of 1 MUX to make up a LUT5 from two LC with having 2;

Figure 16 has illustrated according to the logical block of the 5th embodiment of the present invention;

Figure 17 has illustrated according to the logical block of the 6th embodiment of the present invention; And

Figure 18 has illustrated to be used in the basic logic piece, forming the mixed layout pattern of the partner LC of 32 demoders and WLUT chain.

Embodiment

Note that below each LC can have like more or less in the accompanying drawing that is about to discuss, and among the figure everywhere the basic components identical of function give mark with similarly numbering, last numeral of each label all is identical.

Fig. 2 has illustrated according to the logical block of first embodiment of the present invention.As shown in Figure 2, logical block 200 comprises LUT 202, first MUX 204, second MUX 206 and the d type flip flop 208 of 4 input ends.Logical block comprises four input end: ta0, ta1, ta2 and ta3, and they also are the input ends of LUT 210.This logical block also comprises two input ends, i.e. tsel and wlutin, and three output terminals, i.e. wlutout, regout and combout.

LUT 202 has an output terminal.LUT 202 can carry out any function of four variablees.

First MUX 204 has two data input ends, i.e. input end 0 and input end 1; Output terminal; And selecting side.The input end 0 of MUX 204 is connected to the output terminal of LUT 202; Input end 1 is connected to input end wlutin; The selecting side is connected to input end tsel, and in two inputs of MUX 204 which can be used to select to export.The output terminal of MUX 204 is connected to output terminal wlutout.

Second MUX 206 has two data input ends, i.e. input end 0 and input end 1; Output terminal; And selecting side.The input end 1 of second MUX 206 is connected to the output terminal of first MUX 204, and its input end 0 is connected to the output terminal of LUT 202.The selecting side is driven by static configuration bit (configuration bit).The output terminal of second MUX 206 is connected to the D input end and the output terminal combout of trigger 208.

In operation, the selecting side of MUX 206 can be used for the output signal transmission of LUT202 through second MUX 206 by configuration suitably, then via trigger 208 at output terminal regout with directly export at output terminal combout.

According to the present invention, first MUX 204 is used to select select signal to export at output terminal wlutout then from the signal of input end wlutin and signal from LUT 202 output terminals.Signal tsel can be used to select first MUX 204 will export in two signals which.If suitably dispose the selecting side of MUX 206, then select signal also can export at end regout place at the combout end or via d type flip flop 208.

In a word, can export at output terminal regout via MUX 206 and trigger 208 via first MUX 204 in output terminal wlutout output, perhaps export at output terminal combout via MUX 206 by the signal of LUT 202 outputs.

Similarly, LC 200 can select these signals at first MUX 204, then in output terminal wlutout, regout or combout output at the LUT reception signal of input end wlutin from contiguous LC.

Therefore, through being connected to the input end wlutin chain type of a LC output terminal wlutout of another LC, just can form the WLUT chain by a plurality of this type LC.Term ' WLUT ' refers to the wide LUT that the input of more Duoing is arranged than independent LUT.

Fig. 3 has illustrated according to the logical block of second embodiment of the present invention.Fig. 3 is different from Fig. 2 part and is that it has only a MUX 304 corresponding to the MUX among Fig. 2 204, and has omitted MUX 206.The function of MUX 304 is signals of selecting from the output terminal of input end tsel and LUT 304.Therefore, the WLUT chain can form through input end wlutin and the output terminal wlutout that chain type connects this type LC300.

In addition, LC 300 can play common LC.Through selecting signal at input end tsel, the D input end and the output terminal combout of d type flip flop 308 can be directly sent in the output of LUT 302.

Fig. 4 has illustrated the WLUT chain that formed by the logical block shown in Fig. 2.As shown in Figure 4,3 LC are arranged, i.e. LC 410, LC 420 and LC 430.Among LC 410, LC 420 and the LC 430 each all have with Fig. 2 in the identical structure of LC 200.Therefore, omitted its detailed structrual description for simplicity.Note that the configuration memory cell of LUT (configuration memory cell) is not only for illustrating for simplicity in some accompanying drawings that this accompanying drawing neutralization will be discussed hereinafter.

The output terminal wlutout of LC 410 is connected to the input end wlutin of LC 420, and the output terminal wlutout of LC 420 is connected to the input end wlutin of LC 430.

The input signal at the input end wlutin place of LC 410 possibly be the LUT output of contiguous LC.In LC 410, the output of it and LUT 412 is selected by MUX 414, and select signal via with the output terminal wlutout output of LUT 412; Then in LC 420, select by MUX 424 from the signal of the output terminal wlutout of LC 410 and the output signal of LUT 422, and select signal in the output terminal wlutout of LC420 output; Then in LC 430, be selected at MUX 434 places from the signal of the output terminal wlutout of LC 420 and the output signal of LUT 432, and select signal in the output terminal wlutout of LC 420 output.

Formed a WLUT chain thus, it is pointed out to the thick black line of the wlutout of LC 430 by the wlutin from LC 410.

Note that each LC in the LUT chain can select to transmit its LUT output or the LUT output of the upper reaches LC in the chain.For example, through suitably selecting signal at three LC selecting side tsel separately, the output signal of the LUT 412 of LC 410 can be delivered to the wlutout end of LC 410, LC420 and LC 430 along chain.And, through MUX 416,426 and 436 selecting side separately of suitably programming, the output signal of the LUT 412 of LC 410 can through among three LC any one in their combout or the output of regout output separately.

WLUT chain shown in Fig. 4 can be used to carry out the complex logic function such as LUT5 and bus MUX.Compare with similar traditional logic circuit, the method for WLUT chain uses less logic units to carry out some common logic functions.In addition, use the MUX of special-purpose WLUT link coupling faster owing to the LUT that is coupled together with universal interconnect has replaced with, performance has also obtained enhancing.

Fig. 5 has illustrated the 5 input LUT that the WLUT chain by Fig. 4 forms.As shown in Figure 5, this LUT5 is by two LC, and LC 510 and LC 520 form.LC 510 and LC 520 have with Fig. 2 in the identical structure of LC 200.

LUT5 has five input ends, din0, din1, din2, din3 and din4.Signal from din [3:0] is admitted to LUT512 and LUT 522 at LC 510 and LC 520 input end ta0, ta1, ta2 and ta3 separately.Tsel end through with LC 510 is chosen as logical zero, and the wlutout end that the output signal of LUT 512 is selected at LC 510 is exported and selected through the MUX 524 of LC 520 with the output signal of LUT 522.Be admitted to the selecting side of the MUX 524 of LC 520 from the signal of din4 via the input end tsel of LC 520, to select the output of LUT 512 still be the output of LUT 522 in decision then.Through the selecting side of the LUT 512 that suitably programmes, LUT 522 and MUX 526, the logical circuit of Fig. 5 can only be carried out LUT5 with two logical blocks, and it postpones less times greater than LUT 4.This compares more favourable with the classic method of from 3 LUT 4, setting up LUT5, the latter not only has secondary LUT and postpones also to exist slower common interconnect delay.

Fig. 6 has illustrated the bus MUX that the WLUT chain by Fig. 4 forms.As shown in Figure 6, there are three basic logic pieces (Basic Logic Block calls BLB in the following text), BLB 1, BLB2 and BLB 3.BLB 1 comprises LC 1-1,2-1 ..., and M-1; BLB 2 comprises LC 1-2,2-2 ..., and M-2; BLB 3 comprises LC 1-3,2-3 ..., and M-3.Each LC all have with Fig. 2 in the identical structure of LC 200.

Three LC among first row; LC 1-1, LC 1-2 and LC 1-3; Form a WLUT chain; Wherein, the output of the output of the LUT 6112 of LC 1-1 and the LUT 6122 of LC 1-2 is selected through the MUX among the LC 1-2 6124, selects through MUX 6134 with the output of LUT 6132 then.

Accordingly, the LC i-1 during i is capable, LC i-2 and LC i-3 form a WLUT chain, wherein respectively, i=2 ..., M.

Note that LC 1-1,2-1 among the BLB 1 ..., be the shared identical selection signal tsel0 of they MUX 6j14 separately with M-1; LC 1-2 among the BLB 2,2-2 ..., M-2 is the shared same selection signal tsel1 of they MUX 6j24 separately; And the LC1-3 among the BLB 3,2-3 ..., M-3 is the shared identical selection signal tsel2 of they MUX 6j34 separately; J=1 wherein ..., M.Through selecting signal tsel0 and tsel1, the LC among the BLB 1 (thereby this LUT) can send into their output the output terminal of corresponding LC among BLB 2 or the BLB 3.Therefore, the LC among the BLB 1 has embedded M bit wide 2 and has selected 1 MUX (M-bjt wide2-to-1multiplexer).

Similarly, the LC among the BLB 2 (LUT) can send their output into output terminal corresponding among BLB 2 or the BLB3, has embedded 2 of M bit wide and has selected 1 MUX.LC among the BLB 3 (LUT) can send into their output their output terminal, has embedded M bit wide 2 and has selected 1 MUX.These LC among the

BLB

1,2 and 3 are merged into 3 of M bit wide and select 1 bus MUX.

Note that the various combination of selecting signal tsel0, tsel1 and tsel2 possibly cause the different chain type output at the rightmost wlutout end of link.Can define like this, signal tsel0, tsel1 and tsel2 equal ' 0 ' expression they the LUT output of the LC that is driven is delivered on the link, and signal equals ' 1 ' expression they the LUT output of adjacent upstream LC is delivered on the link.

Have only in the middle of three signals a signal equal ' 0 ' situation under, promptly 0,1,1}, 1,0,1}, { 1,1,0} will be sent to the output of link by the LUT output of the LC of signal ' 0 ' driving.

Equal at least two signals in the middle of three signals ' 0 ' those situation under, promptly 0,0,0}, 0,0,1}, 0,1,0}, { 1,0,0} belongs to the output that will be passed to link by the LUT output of the rightmost LC of signal ' 0 ' driving.Therefore, can produce a right of priority by the big bus MUX of this type.In one example, the logic function with highest priority preferably is placed on the rightmost side of bus MUX, and the minimum logic function of right of priority can be arranged in the left side.

Select 1 bus MUX although shown 3 of M bit wide in the drawings, yet the N that it can expand to a M bit wide that is formed by the MUX of the LUT of MxN and MxN selects 1 bus MUX.Certainly, the numbering of tsel signal should be increased to N.

Select in the 1 bus MUX at the N of M bit wide, each LC possibly have different input signals for their LUT separately, perhaps shares identical input signal group with a part or other whole LC.

In a situation, the LUT among each BLB shares same wide input signal group, but carries out the algorithms of different operation such as ADD and SUB.Through bus select signal is made a choice, can select to export the different algorithms operating result.

In another situation, the LUT among each BLB can have different input signals and output different address signal.Through selecting bus select signal, at the output terminal of correspondence different address can appear.

In one embodiment, carry chain (carry chain) can be added to the LUT of at least a portion LC so that in the bus MUX, carry out special algorithm.

Because saved LUT crowd, so it is less to have an area that the integrated circuit of above-mentioned bus MUX takies.In addition, because adopted fixed connection, so the delay of bus MUX is shorter.With leftmost LUT is example, and it arrives the rightmost output terminal of bus MUX through 3 MUXs.

Note that the wlutin end of LC among Fig. 6 is connected to the wlutout end of each adjacent LC.Other input and output sides of LC will connect via the switch enclosure (switch box) between identical BLB or each BLB.Fig. 7 has illustrated the interconnection example between the logical block in the basic logic piece.In BLB, LC-0, LC-1 ..., LC-14 and LC-15 have input end ta0, ta1, ta2, ta3 separately; And output terminal regout and combout.The input end ta0-ta3 of LC-0 and output terminal regout and combout are connected to the switch enclosure of BLB, and LC-0 can be routed to other LC in the identical BLB from this switch enclosure, and perhaps input end umi and the output terminal umo via BLB is routed to outside LC.Similarly, LC-1 ..., each among LC-14 and the LC-15 can be routed to other LC in the identical BLB, perhaps is routed to outside LC through switch enclosure.Although not shown in Fig. 7, input end tsel also can be connected to switch enclosure, so that be routed to other LC in identical BLB or the outside BLB.

Although note that integrated circuit among Fig. 4-6 is illustrated comprises the logical block shown in Fig. 2, they also can be formed by the logical block shown in Fig. 3.

Fig. 8 has illustrated according to the logical block of the 3rd embodiment of the present invention.As shown in the figure, LC800 has LUT 802, rejection gate 803, MUX 806 and the d type flip flop 808 of 4 inputs.LC 800 comprises four input end: ta0, ta1, ta2 and ta3, and they also are the input ends of LUT 802.LC comprises two output terminals, i.e. regout and combout.In addition, LC also comprises another input end lutin and another output terminal lutout.

Except these 4 input end ta0, ta1, ta2 and ta3, LUT 802 also has an output terminal, and it is connected to output terminal lutout.Rejection gate 803 has two data input ends and an output terminal.One of them input end of MUX 803 is connected to the output terminal of LUT 802, and other input ends are connected to input end lutin.

MUX 806 has two data input ends, i.e. input end 0 and input end 1; Output terminal; And selecting side.The input end 0 of MUX 806 is connected to the output terminal of rejection gate 803, and input end 1 is directly connected to the output terminal of LUT 802.The selecting side is driven by the static configuration bit.The output terminal of second MUX 806 is connected to the D input end and the output terminal combout of trigger 808.

In operation, the selecting side of MUX 806 can be programmed the output of the signal at input end 1 place of selecting MUX 806 as MUX 806, and this signal is the output of LUT 802.Then, this signal will be passed to output terminal combout or be delivered to output terminal regout via trigger 808.

In another kind of approach, the input of the input end lutin of LC600 possibly be the output signal from the LUT of contiguous LC.Then, the output signal of this signal and LUT 802 carries out NOR operation, and consequential signal is transfused to MUX 806 at input end 0.Through the selection of configuration end, or non-signal can perhaps be exported at output terminal regout via trigger 808 directly in output terminal combout output.

Whereby, formed partner's logic (buddy logic), wherein, rejection gate is carried out NOR operation to the output of LUT802 with from the output of (one or more) LUT of another LC.

Fig. 9 has illustrated according to the logical block of the 4th embodiment of the present invention.This embodiment is different from Fig. 8 part and is that rejection gate 803 is replaced by MUX 905, and its selecting side is connected to the input end tsel of LC.

In operation, the output signal of the LUT 902 that occurs at the input end of MUX 906 1 can be selected by MUX 906, and in output terminal combout output or export at output terminal regout via trigger 908.

In another kind of approach, possibly be that the output signal from the LUT of contiguous LC is transfused to LC 900 at input end lutin.Then, the output of this signal and LUT 902 is selected in MUX 905.Through selecting signal tsel, MUX 905 selects the output of LUT 902 perhaps from the output that is close to LC, so that export to the input end 0 of MUX 906.In MUX 906,, then can perhaps export at output terminal regout directly in output terminal combout output via trigger 908 from the selection signal of MUX 905 if suitably programmed in its selecting side.Formed partner's logic thus, wherein, MUX is carried out selection operation to the output of LUT 902 with from the output of another LUT among the physically contiguous LC.

Should be appreciated that to be alternative in aforesaid NOR and MUX, also can adopt other circuit such as AND, NAND, OR and XOR gate to form partner's logic.

And, can be replaced into right LUT formation partner logic with LUT more than 2.For example, the output of a LUT, the 2nd LUT and the 3rd LUT can be connected respectively to such as MUX, the input end of circuit with door, Sheffer stroke gate or door, rejection gate and XOR gate to form partner's logic.

Partner's logic can be used carries out some logical operation.Because the element number that needs is less, so the area that the integrated circuit that produces takies is also less.In addition, because slow LUT is replaced by much fast logical circuit, so performance also will be enhanced.And, to compare with a long-chain road, partner's logic is only used the link of the LC of a special use to LC, with immediate LC coupling up and down, thereby makes that the layout of two partner LC is very flexible.

Figure 10 has illustrated partner's logic of being formed by logical block shown in Figure 8.As shown in, have three LC, LC 1010, LC 1020 and LC 1030.Each LC all have with Fig. 8 in the identical structure of LC.The output terminal lutout of LC 1030 is connected to the input end lutin of LC 1020, and the output terminal lutout of LC 1020 is connected to the input end lutin of LC 1010.

In operation, the output signal of LUT 1032 is admitted to LC1020 at the output terminal lutout of LC 1030.In LC 1020, the output of 1023 couples of LUT 1032 of rejection gate and carry out NOR operation from the output of LUT 1022.Through the selection signal of configuration MUX 1026, can select or non-signal in output terminal combout output or export at output terminal regout via d type flip flop 1028.

Similarly, the output of LUT 1022 and carry out NOR operation through rejection gate 1013 from the output of LUT 1012, and can be selected at the output terminal combout of LC 1010 or export at output terminal regout via d type flip flop 1018.

Thereby partner's logic can be used to carry out effectively many common logic functions, such as demoder and scrambler.

Note that in Figure 10 MUX 1016 signals that draw or non-can only be exported in LC 1010.That is, the output of LUT 1012 and LUT 1022 can only be carried out NOR operation and in LC1010, export.Figure 11 and Figure 12 have illustrated different partner's logics.

As shown in Figure 11, there are three LC, LC 1110, LC 1120 and LC 1130, LC 810 parts that they are different from Fig. 8 are that they have two couples of lutout and lutin end and one three input MUX, rather than two input MUXs.The two couples of lutout and lutin end are labeled as ulutout and ulutin, dlutout and dlutin again, because top ulutout will be connected to adjacent LC with the ulutin end, and following dlutout and dlutin hold the LC that will be connected to down the neighbour.

In LC 1110, the ulutout end is connected to the output terminal of LUT 1112, and dlutin holds one in two input ends that are connected to rejection gate 1113.Ulutin and dlutout end are connected to the input end 2 of MUX 1116 and the output terminal of rejection gate 1113 respectively.

LC 1120 and LC 1130 have the structure identical with LC 1110.

The dlutin of LC 1110 and dlutout end are connected to ulutout and the ulutin end of LC 1120 respectively; The dlutin of LC 1120 and dlutout end are connected to ulutout and the ulutin end of LC 1130 respectively.

Therefore; NOR operation is carried out in the output of 1113 couples of LUT 1112 of rejection gate of LC 1110 and the output of LUT 1122; And or non-signal be delivered on the input end 2 of input end 0 and MUX 1126 of MUX 1116; Therefore, or non-signal can be via LC 1110 and LC 1120 outputs.Similarly, formed by the output of the output of LUT 1122 and LUT 1132 or non-signal can be via LC 1120 and LC 1130 outputs.

Figure 12 has illustrated a diverse ways.In this case, LC 1210, LC 1220 and LC 1230 are similar to the situation of LC 1110,1120 and 1130.Difference is that among LC 1210, LC 1220 and the LC 1230 each all has one three input rejection gate and two input MUXs, rather than two input rejection gates and three input MUXs.

In LC 1210, input end ulutin is connected in three input ends of rejection gate 1213, and the output terminal of LUT 1212 is connected to the dlutout end.

LC 1220 and LC 1230 have the structure identical with LC 1210.

The dlutin of LC 1210 and dlutout end are connected to ulutout and the ulutin end of LC 1220 respectively; The dlutin of LC 1220 and dlutout end are connected to ulutout and the ulutin end of LC 1230 respectively.

In operation, the rejection gate 1223 of LC 1220 receive LUT 1212 output, LUT 1222 output and LUT 1232 output and they are carried out NOR operation.MUX 1226 can be selected or non-signal transmits and exports with output terminal combout or regout via LC 1220.Note that this partner's logic has three input ends, rather than shown in Figure 10 and Figure 11, have two input ends.

Figure 13 has illustrated 32 demoders being formed by some partner's logics.As shown in Figure 13, in a BLB, have 9 LC, LC 1310,1320 ... and 1390.Among the LC 1310-1380 each all with Fig. 8 in LC identical, and in link, connect mutually to form partner's logic.For example, in LC 1310, the output of the LUT 1312 among the LC 1310 and the output of the LUT 1322 among the LC 1320 are carried out NOR operation through rejection gate 1313, and or non-signal input at input end 0 place of MUX 1316.

Similarly, in LC 1330, the output of the LUT 1332 among the LC 1330 and the output of the LUT 1342 among the LC 1340 are carried out NOR operation through rejection gate 1333, and or the input of non-signal at input end 0 place of MUX 1336; In LC 1350, the output of the LUT 1352 among the LC 1350 and the output of the LUT 1362 among the LC 1360 are carried out NOR operation through rejection gate 1353, and or the input of non-signal at input end 0 place of MUX 1356; In LC 1370, the output of the LUT 1372 among the LC 1370 and the output of the LUT 1382 among the LC 1380 are carried out NOR operation through rejection gate 1373, and or non-signal be transfused to the input end 0 of MUX 1376.

MUX

1316,1336,1356 and 1376 output terminal are connected to input end ta3, ta2, ta1, the ta0 of the LUT 1392 of LC 1390 respectively via the combout end of LC separately, and LC 1390 can have the structure identical with LC 1310-1380.In LC 1390, the output of LUT 1392 can be selected by MUX 1396 outputs.Through suitably disposing the selecting side of

MUX

1316,1336,1356,1376 and 1396, thereby can realize 32 demoders.

In operation, 32 input signals are transfused to demoder.This signal is divided into the subsignal crowd; Din [3:0], din [7:4], din [11:8], din [15:12], din [19:16], din [23:20], din [27:24], din [31:28], they are transfused to LC 1310-1380 via input end ta0, ta1, ta2, ta3 respectively.When 32 input signals equal special value, 32: 1 demoder will dout end or combout end output ' 1 '; Otherwise it is output as 0.

Because saved some LUT, thus above-mentioned demoder operation is faster and area occupied still less.In fact, because can not only carry out, so it has realized the theoretical minimum-depth of two-stage LC with one-level LC with LUT 4.And, although this partner's logic has illustrated be connected to each other, yet each can be positioned in the BLB Anywhere partner LC.Therefore, the demoder that forms like this is owing to the interchangeability between the LC has layout flexibly.

Figure 14 has illustrated to be used in the basic logic piece, forming the layout pattern of the LC of 32 demoders.In Figure 14,4 LC that are used for forming 32 demoders shown in Figure 13 are to being placed in the first to second, the the the 6th to the 7th, the 9th to the tenth, the 13 to the 14 and sixteenth LC position of BLB respectively with single LC.Should be appreciated that the flexible topology's requirement owing to partner's logic, these LC are to can at random placing BLB with single LC.Place the layout method in the BLB can reach thousands of kinds 32 demoders.

How Figure 15 has illustrated to select partner's logic of 1 MUX to set up LUT5 from two LC with having 2.As shown in Figure 15, LC 1510 and LC 1520 have with Fig. 9 in the identical structure of LC 900.

This LUT5 has five input ends, din0, din1, din2, din3 and din4.Signal from din [3:0] is admitted to LUT1512 and LUT 1522 at LC 1510 and LC 1520 input end ta0, ta1, ta2 and ta3 separately; And din4 is connected to the input end tsel of LC 1510.The input end lutin of LC 1510 is connected to the output terminal lutout of LC 1520.The selecting side of MUX 1516 is programmed passes through the output signal transmission of MUX 1515.

In operation, the function of MUX 1515 is to select the output of LUT 1512 and the output of LUT1522.Through suitably LUT 1512 and LUT 1522 being programmed, the logical circuit of Figure 15 can only be realized LUT5 with two logical blocks, and LUT 4 is a bit larger tham in its delay.It compares more favourablely with the classic method of from 3 LUT 4, setting up LUT5, and the latter not only has secondary LUT and postpones also to exist slower general interconnection to postpone.

Figure 16 has illustrated according to the logical block of the 5th embodiment of the present invention.

LC 200 parts that LC 1600 shown in Figure 16 is different among Fig. 2 are that it also comprises rejection gate 1603, and it has two input ends and an output terminal; Input end lutin and output terminal lutout; And MUX 1606 has three input ends, and promptly

input end

0,1 and 2, rather than two input ends.One of them input end of rejection gate 1603 is connected to the output terminal of LUT 1602, and another input end is connected to the input end lutin of LC 1600.The output terminal of rejection gate 1603 is connected to the input end 2 of MUX 1606.The input end 0 of MUX 1606 is connected to the output terminal of LUT1602, and the input end 1 of MUX 1606 is connected to the output terminal of MUX 1604.

As stated, a plurality of LC with MUX 1604 can form a WLUT chain, and two LC 1600 with rejection gate 1603 can form partner's logic.Therefore, can form the combination of a kind of partner's logic and WLUT chain through a plurality of LC 1600.

Figure 17 has illustrated according to the logical block of the 6th embodiment of the present invention.LC 1600 parts that LC1700 among Figure 17 is different from Figure 16 are that mainly it has replaced MUX 1604 with MUX 1707 and MUX 1704.In addition, LC 1700 is shown having not gate 1701.

MUX 1707 has two input ends, input end 0 and input end 1; Output terminal; And selecting side.The input end 0 of MUX 1707 is connected to the input end lutin of LC, and they can receive the output signal from the LUT of the LC below another.The input end 1 of MUX 1707 is connected to the input end wlutin of LC, and it can receive output from the LUT of another LC on the left side.MUX 1707 is selected two input signals, and which signal in two input signals is selected and transmitted in the selecting side decision.

MUX 1704 also has two input ends, input end 0 and input end 1; Output terminal; And selecting side.The input end 1 of MUX 1704 is connected to the output terminal of MUX 1707; The input end 0 of MUX 1704 is connected to the output terminal of LUT 1702; Input end tsel is connected to the selecting side of MUX 1704, and in two inputs which decision will select and transmit.The output terminal of MUX 1704 is connected to the input end 1 of MUX 1706.

In operation, MUX 1707 can receive the output of LUT of another LC on the left side via input end wlutin, and it is passed to MUX 1704, and MUX 1704 also receives the output of LUT 1702.MUX 1704 can be selected in them one and it is delivered to the output terminal wlutout of LC.Therefore, a plurality of LC 1700 that have MUX 1707 and MUX 1704 can form a WLUT chain.

In addition, MUX 1707 can be in the output of the LUT of the LC below its input end 0 place receives another, and it is delivered to MUX 1704, and MUX 1704 also receives the output of LUT 1702.Therefore, two LC that have MUX 1707 and MUX 1704 can form partner's logic.

And two LC with rejection gate 1703 form another partner's logic.

Not gate 1701 has its input end that is connected to the output terminal of rejection gate 1703, and is connected to the output terminal of the input 3 of MUX 1706.One of ordinary skill in the art will recognize, LC1700 can carry out four kinds of algorithms through this layout, or non-or, with non-, and.

Figure 18 has illustrated to be used in the basic logic piece, forming the mixed layout pattern of the partner LC of 32 demoders and WLUT chain.As shown in Figure 18, have 3 BLB, each all has 16 LC.Have the LC of vertical-line pattern to be used to form the WLUT chain, and the LC with lattice is used to form 32 demoders.Because partner's logic lacking ' link ' middle formation, so partner's logic can place not in the middle of the LC that is taken by the WLUT chain neatly.Therefore, with realizing the very big integrated circuit of dirigibility.

LC formed according to the present invention and integrated circuit are not restricted to the FPGA circuit, but can be suitable for having embedded any integrated circuit of FPGA, such as CSoC and PSoC.And such LC that forms can interconnect with different interconnection network with integrated circuit.

Though combined the preferred embodiments of the invention to be described, for one of ordinary skill in the art, clearly, can make different changes and modification not breaking away under the prerequisite of the present invention.

For example, although aforesaid LUT has been illustrated 4 input ends, yet they can have the input end of any other quantity.In addition, d type flip flop can be replaced by any another kind of trigger.

Therefore, its objective is in accompanying claims, to cover change and the modification that all these types belong to true spirit of the present invention and scope that true spirit of the present invention and scope are defined by the boundary of accompanying claims.

Claims

1. integrated circuit with a plurality of logical blocks, each of said a plurality of logical blocks comprises:

First input end (wlutin), second input end (tsel), a plurality of the 3rd input ends (ta0, ta1, ta2, ta3) and first output terminal (wlutout);

Look-up table (LUT) (202,302), it has a plurality of LUT input ends that are connected respectively to said a plurality of the 3rd input ends of logical block; And, the LUT output terminal;

First MUX (MUX) (204,304) has the first MUX input end, the second MUX input end, selecting side and MUX output terminal; Wherein, The first MUX input end of first MUX is connected to first input end; The second MUX input end of first MUX is connected to the LUT output terminal; The MUX output terminal of first MUX is connected to first output terminal (wlutout), and the selecting side be connected to second input end and can be used for being chosen in the first MUX input end and signal that the second MUX input end occurs in which transmit through first MUX;

Wherein, through one in a plurality of logical blocks first input end (wlutin) chain type being coupled in a plurality of logical blocks another first output terminal (wlutout), a WLUT chain is formed, and wherein WLUT refers to have than independent LUT the wide LUT of the input of more Duoing;

In said a plurality of logical block each all comprises second MUX (206), and second MUX (206) has the first MUX input end, the second MUX input end, MUX selecting side and MUX output terminal; In in logical block each; The first MUX input end of second MUX is connected to the MUX output terminal of first MUX; And the second MUX input end of second MUX is connected to the output terminal of LUT, and the output terminal of second MUX is coupled to second output terminal (combout or regout) of logical block; Wherein, the MUX selecting side of second MUX is driven by configuration memory cell, and configuration memory cell can be programmed the signal that lets second MUX be delivered in its first or second MUX input end.

2. according to the integrated circuit of claim 1, wherein, integrated circuit comprises FPGA.

3. according to the integrated circuit of claim 1; Wherein, In said a plurality of logical block each all comprises trigger, and trigger has trigger input end and trigger output terminal, in identical logical block; Through being connected to the trigger input end of trigger the output terminal of second MUX and being connected to second output terminal to the trigger output terminal of trigger, realized the said coupling of output terminal of second output terminal and second MUX of logical block.

4. according to the integrated circuit of claim 1, wherein, each in said a plurality of logical blocks all comprises the 3rd output terminal, and the 3rd output terminal is coupled to the MUX output terminal of second MUX of same logical units.

5. according to the integrated circuit of claim 4; Wherein, In said a plurality of logical block each all comprises trigger, and trigger has trigger input end and trigger output terminal, in identical logical block; Through being connected to the trigger input end of trigger the output terminal of second MUX and being connected to the 3rd output terminal to the trigger output terminal of trigger, realized the said coupling of output terminal of the 3rd output terminal and second MUX of logical block.

6. according to the integrated circuit of claim 1, wherein, said a plurality of logical blocks comprise first logical block (510) and second logical block (520); Wherein, said a plurality of the 3rd input ends of said a plurality of the 3rd input ends of first logical block and second logical block are interconnected to share identical input signal; In first logical block, second input end is used to select the output of LUT of first logical block to transmit; Through the LUT to first logical block and second logical block, said a plurality of the 3rd input ends and second input end of second logical block are programmed, and have formed a wide LUT.

7. according to the integrated circuit of claim 1; Wherein, Said integrated circuit comprises first group of logical block and second group of logical block at least; First group and second group of logical block are connected to the WLUT chain respectively, and second input end of each logical block in first group of logical block all is connected to second input end of the counterlogic unit of second group of logical block, has formed a bus MUX thus.

8. according to the integrated circuit of claim 1; Wherein, In said a plurality of logical block each all comprises carry chain input end and carry chain output terminal; And, formed a carry chain through being coupled to one in said a plurality of logical blocks carry chain input end chain type in said a plurality of logical block another carry chain output terminal.

9. according to the integrated circuit of claim 1, wherein, said first MUX is formed by two MUXs (1707,1704) or more MUX.

10. according to the integrated circuit of claim 1; Wherein, In said a plurality of logical block each all comprises four-input terminal (lutin), the 4th output terminal (lutout) and has first circuit input end and the circuit of second circuit input end (1603); The LUT output terminal is connected to first circuit input end and the 4th output terminal of circuit, and the second circuit input end of circuit is connected to four-input terminal; Wherein, be coupled in said a plurality of logical block another the 4th output terminal to one four-input terminal in said a plurality of logical blocks, formed partner's logic (buddy logic).

11. according to the integrated circuit of claim 10, wherein, said circuit with first circuit input end and second circuit input end from comprise rejection gate, with the crowd of door, Sheffer stroke gate or door and XOR gate select.

12. according to the integrated circuit of claim 10, wherein, said circuit with first circuit input end and second circuit input end comprises one or more MUXs.

13. the integrated circuit with a plurality of logical blocks, each of said a plurality of logical blocks all comprises:

First input end (wlutin), second input end (tsel), the 3rd input end (lutin), a plurality of four-input terminal (ta0, ta1, ta2, ta3), first output terminal (wlutout) and second output terminal (lutout);

LUT (1702) has a plurality of LUT input ends, and they are connected respectively to a plurality of four-input terminals; And, the LUT output terminal;

First MUX (1707) has the first MUX input end, the second MUX input end, MUX selecting side and MUX output terminal; Wherein, The first MUX input end of first MUX is connected to first input end; The second MUX input end of first MUX is connected to the 3rd input end; And the MUX selecting side can be programmed any one in two signals that the first MUX input end that lets first MUX be delivered in first MUX and the second MUX input end occur

Second MUX (1704) has the first MUX input end, the second MUX input end, MUX selecting side and MUX output terminal; Wherein, The first MUX input end of second MUX is connected to the MUX output terminal of first MUX; The second MUX input end of second MUX is connected to the LUT output terminal; The MUX selecting side of second MUX is connected to second input end, and the MUX output terminal of second MUX is connected to first output terminal (wlutout);

Circuit (1703) has first circuit input end, second circuit input end and circuit output end; Wherein, first circuit input end is connected to the LUT output terminal, and the second circuit input end is connected to the 3rd input end;

The 3rd MUX (1706), it has the first MUX input end, the second MUX input end, the 3rd MUX input end, MUX selecting side and MUX output terminal; Wherein, The first MUX input end of the 3rd MUX is connected to the LUT output terminal; The second MUX input end of the 3rd MUX is connected to the MUX output terminal of second MUX; The 3rd MUX input end of the 3rd MUX is connected to the circuit output end of circuit, and the MUX selecting side can be programmed first, second any signal that occurs with the 3rd MUX input end that is delivered in the 3rd MUX.

14. integrated circuit according to claim 13; Wherein, When the selecting side of first MUX of each in a plurality of logical blocks all is programmed the signal of the first MUX input end that is delivered in same first MUX, through forming the WLUT chain to one in a plurality of logical blocks first input end (wlutin) by link couples another first output terminal (wlutout) in a plurality of logical blocks.

15. integrated circuit according to claim 13; Wherein, Through being coupled to first the 3rd input end in a plurality of logical blocks in a plurality of logical blocks second second output terminal, between first logical block and second logical block, formed partner's logic.

16. integrated circuit according to claim 13; Wherein, When the selecting side of first MUX is programmed the signal of second input end that is delivered in first MUX; Through being coupled to the 3rd the 3rd input end in a plurality of logical blocks in a plurality of logical blocks the 4th second output terminal, between the 3rd logical block and the 4th logical block, formed partner's logic (1704 and 1706).

17. according to the integrated circuit of claim 13, wherein, said circuit with first circuit input end, second circuit input end and circuit output end is selected from comprise the crowd with door, Sheffer stroke gate or door, rejection gate and XOR gate.

18. according to the integrated circuit of claim 17, wherein, said the 3rd MUX has the 4th MUX input end; Each all comprises not gate in said a plurality of logical block, and its input end is connected to the output terminal of circuit, and its output terminal is connected to the 4th MUX input end of the 4th MUX.

19. according to the integrated circuit of claim 13, wherein, said circuit with first circuit input end, second circuit input end and circuit output end comprises one or more MUXs.