CN102375905B - Technology mapping method for integrated circuits for improved logic cells - Google Patents

Abstract

The invention relates to a technology mapping method for integrated circuits for improved logic cells, which comprises the following steps of: firstly, decomposing a universal combinational logic circuit into circuits consisting of input logic cells 2; then, taking the input logic cell 2 as a node, partitioning the node based on an improved logic cell, and finding out all partitions of the node; taking a partition corresponding to the maximum ratio of the number of nodes covered by each partition PGCN(Propagate Gate Cover Number) to the number of actually-used improved logic cells PRUN(Propagate Resource Usage Number) as the optimal partition; and finally, converting the optimal partition into a corresponding improved logic cell. By using the method provided by the invention, through fully using the structural advantages of the improved logic cells, an improved circuit is more efficient on area and time. The method provided by the invention can be widely applied to technology mapping of integrated circuits.

Description

A kind of process mapping method of the integrated circuit for improving logical block

Technical field

The present invention relates to the Technology Mapping technology, relate in particular to the process mapping method of integrated circuit.

Background technology

FPGA (Field Programmable Gate Array, field programmable gate array) generally includes a large amount of logical blocks.Fig. 1 shows a kind of basic fpga logic unit (logic cell calls LC in the following text), and it comprises look-up table (look-up table, LUT) and DFF (d type flip flop).4 input LUT illustrate to have an assembly and puts storage unit, and totally 16, it can be configured or programme to be used for calculating the combination logic functions of any 4 inputs.The output of LUT not only is directly connected to the output of LC, but also sends into the D input end of d type flip flop, and the Q output of d type flip flop can be used as another LC output.In this logical block, can provide MUX (multiplexer, i.e. MUX) and other logic in order to allow the Q output terminal of trigger is connected to some input end of LUT.

Improving logical block is the improvement of having done on Fig. 1 basic logic unit basis, and Fig. 2 a shows the fpga logic unit after the improvement.For the ease of software modeling, the logical block after this improvement is divided into two kinds, a kind of is combined improvement logical block fc_comb, another kind is improvement logical block (register cell that namely the possesses specific function) fc_reg of sequential type.Fig. 2 b is combined improvement logical block fc_comb synoptic diagram, and Fig. 2 c is the improvement logical block fc_reg synoptic diagram of sequential type.

Combined improvement logical block can realize effectively by the cascade system of two-stage LUT 5 input LUT, LUT or operation, LUT and operations, and specific implementation is referring to Fig. 3, Fig. 4, Fig. 5, Fig. 6.Fig. 3, Fig. 4 are the synoptic diagram that utilizes respectively wlut chain structure realization level 5 input LUT (H-LUT5) and vertical 5 input LUT (V-LUT5), Fig. 5 utilizes buddy chain structure to realize the synoptic diagram of LUT or operation, and Fig. 6 utilizes buddy chain structure to realize the synoptic diagram of LUT and operation.Can realize the synchronizing function of register comprising the synchronous reset of realizing register, the synchronous set of register, the synchrodata of register that specific implementation is referring to Fig. 7, Fig. 8, Fig. 9 by the register cell that possesses specific function.Fig. 7 is that the register synchronous reset is realized synoptic diagram, and Fig. 8 is that the synchronous set of register realizes synoptic diagram, and Fig. 9 is that the register synchrodata realizes synoptic diagram.

The modified logical block can realize the quick logical operation between the Different L UT.In addition, improve logical block and comprise a register cell that possesses specific function, it can the synchronous set of effective support, reset or the synchrodata function.The modified logical block can intactly be expressed the functional characteristic that meets chip structure and Design Mode (satisfy certain restriction relation and the circuit of optimum structure is arranged).Directly user's design map is become to satisfy the structuring net table of modified logical block function by logic synthesis tool, guarantee the optimum of area and performance.Therefore, improvement logical block shown in Figure 2 can access better result aspect area and the sequential.

Technology Mapping (Technology Mapping) is to connect front end logic in the FPGA design cycle comprehensively and the important bridge of rear end placement-and-routing, at this one-phase, the circuit meshwork list irrelevant with technique is mapped to the relevant structure of technology library under certain hardware constraints, the fpga chip performance depends on structure and the corresponding process mapping method thereof of logical block to a great extent.

At present domestic and international academia is to FPGA Technology Mapping optimization method, mostly concentrate on general Boolean logic circuit meshwork list is mapped as the circuit that is comprised of K input LUT, the input number of concrete LUT is determined by the technology library of reality, but these methods only are aimed at and comprise a LUT structure merely among the LC, so these methods can't take full advantage of modified logical block advantage structurally shown in Figure 2.

Summary of the invention

The invention provides a kind of process mapping method for the integrated circuit that improves logical block that can overcome the above problems, to solve the Technology Mapping problem of modified logical block FPGA.

In first aspect, the invention provides a kind of process mapping method, the method at first resolves into the common group combinational logic circuit in the initial logic net table circuit that 2 input logic unit form; Then with this 2 input logic unit as a node, take this node as root node, and based on improving logical block this node is cut apart, all that find out again this node are cut apart; Then estimate every kind and cut apart institute's overlay node quantity (PGCN), and estimate the corresponding actual employed improvement number of logic cells (PRUN) of cutting apart, again with this overlay node quantity (PGCN) and actual the use corresponding the cutting apart as optimum segmentation of maximal value of improving ratio between the number of logic cells (PRUN); At last this optimum segmentation is converted to corresponding improvement logical block, in order to finish by initial logic net table to the Technology Mapping that improves other logic netlist of logical block level.

Further, cut apart institute overlay node quantity (PGCN) and be for described every kind

$\mathrm{PGCN}=1+\frac{{\mathrm{PGCN}}_{\mathrm{SUBCUT}1}}{{\mathrm{FANOUT}}_{\mathrm{SUBCUT}1}}+......\frac{{\mathrm{PGCN}}_{\mathrm{SUBCUTn}}}{{\mathrm{FANOUT}}_{\mathrm{SUBCUTn}}}$

Wherein, PGCN _SUBCUTnBe that described n of cutting apart is cut apart institute's overlay node quantity, and n is positive integer, FANOUT _SUBCUTnThe quantity that described n is cut apart the SUBCUTn fan out unit.

Further, the described actual improvement number of logic cells (PRUN) of using is

$\mathrm{PRUN}=\mathrm{RUN}+\frac{{\mathrm{PRUN}}_{\mathrm{SUBCUT}1}-{\mathrm{<figure-callout\; id="1"\; label="RUN\; SUBCUT"\; filenames="HSA00000248326500012.png,HSA00000248326500021.png"\; state="\{\{state\}\}">RUN</figure-callout>}}_{\mathrm{SUBCUT}}}{{\mathrm{FANOUT}}_{\mathrm{<figure-callout\; id="1"\; label="SUBCUT"\; filenames="HSA00000248326500012.png,HSA00000248326500021.png"\; state="\{\{state\}\}">SUBCUT</figure-callout>}1}}+......\frac{{\mathrm{PGCN}}_{\mathrm{SUBCUTn}}-{\mathrm{RUN}}_{\mathrm{SUBCUTn}}}{{\mathrm{FANOUT}}_{\mathrm{SUBCUTn}}}$

Wherein, RUN is described actual desired seek table (LUT) quantity, the PRUN cut apart _SUBCUTnThat described n of cutting apart is cut apart actual use improvement number of logic cells, RUN _SUBCUTnThat described n is cut apart actual desired seek table (LUT) quantity, FANOUT _SUBCUTnThe quantity that described n is cut apart the SUBCUTn fan out unit.

Further, the combination of described improvement logical block comprises LUT4, LUT5, LUTAND and LUTOR.

The present invention takes full advantage of the advantage of improving on the logical unit structure, general Boolean logic circuit conversion served as reasons improve the logical circuit that basic logic unit consists of, so that the circuit design after improving is more excellent on better on the area, performance, effectively reduced the difficulty of follow-up placement-and-routing problem.

Description of drawings

Below with reference to accompanying drawings specific embodiments of the present invention is described in detail, in the accompanying drawings:

Fig. 1 is basic fpga logic cellular construction synoptic diagram;

Fig. 2 improves fpga logic cellular construction synoptic diagram;

Fig. 3 is the synoptic diagram that utilizes wlut chain structure realization level 5 input LUT (H-LUT5);

Fig. 4 utilizes wlut chain structure to realize the synoptic diagram of vertical 5 input LUT (V-LUT5);

Fig. 5 utilizes buddy chain structure to realize the synoptic diagram of LUT or operation;

Fig. 6 utilizes buddy chain structure to realize the synoptic diagram of LUT and operation;

Fig. 7 is that the register synchronous reset is realized synoptic diagram;

Fig. 8 is that the synchronous set of register realizes synoptic diagram;

Fig. 9 is that the register synchrodata realizes synoptic diagram;

Figure 10 is the integrated circuit technology mapping process flow diagram for the improvement logical block of one embodiment of the invention;

Figure 11 is 4 inputs and door before decomposing;

Figure 12 is that the degree of depth that resolves into is 2 two inputs and door;

Figure 13 is that the degree of depth that resolves into is 3 two inputs and door;

Figure 14 is the improvement partitioning algorithm realization flow figure of one embodiment of the invention;

Figure 15 is that the Root node of one embodiment of the invention is cut apart synoptic diagram.

Embodiment

Figure 10 is the integrated circuit technology mapping process flow diagram for the improvement logical block of one embodiment of the invention.

In integrated circuit, the circuit in the initial logic net table is the universal logic circuit irrelevant with physical device, and this universal logic circuit comprises two types, and a kind of is general sequential logical circuit, and another kind is the common group combinational logic circuit.The following stated step 101 is the register fc_reg that general sequential logical circuit are mapped to specific function, and step 102, step 103, step 104 are that the common group combinational logic circuit is mapped to combined improvement logical block fc_comb.Therefore, step 101 can before step 102, also can after step 104, can also arrive optional position between the step 104 in step 102.

In step 101, according to initial logic net table, its general sequential logical circuit is mapped as the respective synchronization circuit fc_reg of register form, comprise the synchronous reset circuit, the synchronous setting circuit among Fig. 8 or the Circuit of Data Synchronous among Fig. 9 that are mapped among Fig. 7.

In step 102, adopt Binary Decision Diagrams (BDD) technology that the common group combinational logic circuit in the initial logic net table is optimized, to reduce the quantity of the logical device of common group, remove the redundancy of common group combinational logic circuit.As being optimized, A and B and A obtains A and B.

In step 103, all common group combinational logic circuit are decomposed into the logical circuit of 2 inputs.

Logical network after BDD optimizes comprises polytype common group combinational logic circuit, such as 4 Sheffer stroke gates of inputting, MUX etc., this step 103 resolves into the common group combinational logic circuit of 2 inputs with all common group combinational logic circuit greater than 2 inputs exactly, and this 2 input universal logic circuit comprises 2 inputs and door, 2 inputs or door, 2 input XOR gate.

Preferably, will resolve into greater than the common group combinational logic circuit of 2 inputs the logical circuit of degree of depth minimum, so that this logical circuit has prolong the most in short-term.For example, 4 inputs and door are resolved into 2 inputs and door with two-stage degree of depth, rather than resolve into have three grades of degree of depth 2 the input with the door, such as Figure 11, Figure 12, shown in Figure 13, Figure 11 is 4 inputs and door before decomposing, Figure 12 is that the degree of depth that resolves into is 2 two inputs and door, and Figure 13 is that the degree of depth that resolves into is 3 two inputs and door.In step 104, the 2 input common group combinational logic circuit that resolve into are carried out Technology Mapping, improve other combinational logic circuit of logical block level in order to convert to.Particularly, adopt the modified partitioning algorithm to realize that 2 input common group combinational logic circuit are to the Technology Mapping that improves other combinational logic circuit of logical block level, this improvement partitioning algorithm is the improvement of having done cutting apart enumeration (Cut Enumeration) basis, has the elaboration that the concrete principle of this improvement partitioning algorithm has been done in the back.

In step 105, all are improved logical block be converted to corresponding actual physics device, in order to will be converted to the actual physics circuit by logical circuit, this improvement logical block comprises the register that possesses specific function in the step 101 and other combinational logic circuit of improvement logical block level in the step 104.

The below elaborates the improvement partitioning algorithm of present embodiment, and Figure 14 is the improvement partitioning algorithm realization flow figure of one embodiment of the invention.

In step 141, the general combinatorial logic unit of each 2 input that will be obtained by step 103 is as a node, find out that each node is all possible cuts apart (CUT), comprise that 4 inputs cut apart that (corresponding to LUT5) cut apart in (corresponding to CUT4), 5 inputs, (corresponding to LUTAND and LUTOR) cut apart in 8 inputs, and all cut apart sum and corresponding every kind of form of cutting apart to store each node, and each node of needs traversal is cut apart in this improvement.Need to prove that be the sub-network that comprises a plurality of nodes described cutting apart.

In step 142, for each node, by evaluation method optimum segmentation of selection from all of respective nodes are cut apart, the below elaborates how to obtain optimum segmentation according to described evaluation method.

The evaluation function that this evaluation method adopts comprises two parts, a part is accumulation coverage quantity (Propagate Gate Cover Number, PGCN), another part is accumulation resource usage quantity (Propagate Resource Usage Number, PRUN).

(1) accumulation coverage quantity PGCN

Certain node PGCN is defined as, take this node as root, and under the condition of cutting apart of current selection, this current discreet value of cutting apart institute's overlay node total quantity, therefore, PGCN only is an estimated value cutting apart institute's overlay node sum to current, rather than explicit value.

Figure 15 is that the Root node of one embodiment of the invention is cut apart synoptic diagram, suppose the current CUT of being divided into of Root node, then as shown in figure 15, the current CUT of cutting apart is cut apart SUBCUT1 and the second son by the first son and is cut apart SUBCUT2 and merge and form, then the corresponding PGCN of the current CUT of cutting apart of this Root node can be expressed as

${\mathrm{PGCN}}_{\mathrm{CUT}}=1+\frac{{\mathrm{PGCN}}_{\mathrm{SUBCUT}1}}{{\mathrm{FANOUT}}_{\mathrm{SUBCUT}1}}+\frac{{\mathrm{PGCN}}_{\mathrm{SUBCUT}2}}{{\mathrm{FANOUT}}_{\mathrm{SUBCUT}2}}---\left(1\right)$

Wherein, PGCN _CUTPGCN corresponding to the current CUT of cutting apart of Root node, PGCN _SUBCUT1That Root node the first son is cut apart PGCN corresponding to SUBCUT1, PGCN _SUBCUT2That Root node the second son is cut apart PGCN corresponding to SUBCUT2, FANOUT _SUBCUT1The fan-out number that the first son is cut apart SUBCUT1, FANOUT _SUBCUT2The quantity that the second son is cut apart the fan out unit of SUBCUT2.Need to prove that if having n son when cutting apart (n for greater than 1 positive integer) current cutting apart, the PGCN that then should currently cut apart correspondence is,

${\mathrm{PGCN}}_{\mathrm{CUT}}=1+\frac{{\mathrm{PGCN}}_{\mathrm{SUBCUT}1}}{{\mathrm{FANOUT}}_{\mathrm{SUBCUT}1}}+......\frac{{\mathrm{PGCN}}_{\mathrm{SUBCUTn}}}{{\mathrm{FANOUT}}_{\mathrm{SUBCUTn}}}---\left(2\right)$

The below sets forth the acquisition methods of each parameter in the formula (1).

Present embodiment Adoption Network topological structure sequentially obtains the PGCN of each node, and therefore before calculating Root node PGCN, the PGCN of all forerunner's nodes of this Root node finishes as calculated, i.e. PGCN in the formula (1) _SUBCUT1, PGCN _SUBCUT2Finish as calculated, and boy cutting be the PGCN of outermost layer node in the network topology structure is 1, therefore by this outermost layer node PGCN value enough PGCN that sequentially obtains each node just.

The fan out unit of certain cutting refers to corresponding all nodes of the output of this cutting, and among Figure 15, the fan out unit (being the fan out unit of node S1) of the first son cutting SUBCUT1 is the Root node, and therefore the first son cutting has fan out unit, i.e. a FANOUT _SUBCUT1=1; The fan out unit (being the fan out unit of node S2) of the second son cutting SUBCUT2 is Root and N5, and therefore the second son cutting has two fan out unit, i.e. FANOUT _SUBCUT2=2.Suppose PGCN _SUBCUT1=5, PGCN _SUBCUT2=3, with FANOUT _SUBCUT1=1, FANOUT _SUBCUT2=2, PGCN _SUBCUT1=5, PGCN _SUBCUT2=3 substitution formula (1) obtain PGCN _CUT=7.5.

(2) accumulation resource usage quantity PRUN

Certain node PRUN is defined as, take this node as root, under the condition of cutting apart of current selection, this current discreet value of cutting apart improvement logical block (comprising LUT4, LUT5, LUTAN, the LUTOR) quantity of actual required use, therefore, PRUN only is the estimation of cutting apart required use number of devices to current.

The Root node of the below in Figure 15 set forth the PRUN account form as example, and the corresponding PRUN of the current CUT of cutting apart of this Root node can be expressed as,

${\mathrm{PRUN}}_{\mathrm{CUT}}={\mathrm{RUN}}_{\mathrm{CUT}}+\frac{{\mathrm{PRUN}}_{\mathrm{SUBCUT}1}-{\mathrm{<figure-callout\; id="1"\; label="RUN\; SUBCUT"\; filenames="HSA00000248326500012.png,HSA00000248326500021.png"\; state="\{\{state\}\}">RUN</figure-callout>}}_{\mathrm{SUBCUT}}}{{\mathrm{<figure-callout\; id="1"\; label="FANOUT\; SUNCUT"\; filenames="HSA00000248326500012.png,HSA00000248326500021.png"\; state="\{\{state\}\}">FANOUT</figure-callout>}}_{\mathrm{SUNCUT}}}+\frac{{\mathrm{PGCN}}_{\mathrm{SUBCUT}2}-{\mathrm{<figure-callout\; id="2"\; label="RUN\; SUBCUT"\; filenames="HSA00000248326500012.png,HSA00000248326500021.png"\; state="\{\{state\}\}">RUN</figure-callout>}}_{\mathrm{SUBCUT}}}{{\mathrm{FANOUT}}_{\mathrm{SUBCUT}2}}---\left(3\right)$

Wherein, RUN _CUTThe quantity of the actual required use of the current CUT of cutting apart of Root node LUT.Because LUT4 is made of a LUT, therefore, for the CUT with 4 inputs, its RUN _CUTValue is 1; Equally, owing to LUT5, LUTAND, LUTOR are made of two LUT, therefore for the CUT5 with 5 inputs and corresponding LUTAND, LUTOR with 8 inputs, its RUN _CUTValue is 2.Among Figure 15, the Root node is current to be divided into 4 input CUT, so RUN _CUT=1.

Be similar to the described PGCN of preamble, calculating PRUN _CUTThe time, PRUN _SUBCUT1, PRUN _SUBCUT2Calculated and finished, be i.e. PRUN _SUBCUT1, PRUN _SUBCUT2For known.

In the formula (3), RUN _SUBCUT1, RUN _SUBCUT2Respectively the quantity of the actual required use of SUBCUT1, SUBCUT2 LUT, its account form and RUN _CUTIdentical.In addition, FANOUT _SUBCUT1, FANOUT _SUBCUT2FANOUT in computing method and the formula (1) _SUBCUT1, FANOUT _SUBCUT2Computing method are identical.

Need to prove that if having n son when cutting apart (n for greater than 1 positive integer) current cutting apart, the PRUN that then should currently cut apart correspondence is,

${\mathrm{PRUN}}_{\mathrm{CUT}}={\mathrm{RUN}}_{\mathrm{CUT}}+\frac{{\mathrm{PRUN}}_{\mathrm{SUBCUT}1}-{\mathrm{<figure-callout\; id="1"\; label="RUN\; SUBCUT"\; filenames="HSA00000248326500012.png,HSA00000248326500021.png"\; state="\{\{state\}\}">RUN</figure-callout>}}_{\mathrm{SUBCUT}}}{{\mathrm{<figure-callout\; id="1"\; label="FANOUT\; SUBCUT"\; filenames="HSA00000248326500012.png,HSA00000248326500021.png"\; state="\{\{state\}\}">FANOUT</figure-callout>}}_{\mathrm{SUBCUT}}}+......+\frac{{\mathrm{PGCN}}_{\mathrm{SUBCUTn}}-{\mathrm{RUN}}_{\mathrm{SUBCUTn}}}{{\mathrm{FANOUT}}_{\mathrm{SUBCUTn}}}---\left(4\right)$

(3) evaluation function COST

Evaluation function COST selects present node by PGCN, PRUN all cuts apart the function of middle optimum segmentation, so evaluation function COST can be expressed as,

$\mathrm{COST}=\frac{\mathrm{PGCN}}{\mathrm{PRUN}}---\left(5\right)$

Wherein, PGCN is accumulation coverage quantity, and PRUN is accumulation resource usage quantity.

In the formula (5), evaluation function COST value is higher, and the corresponding evaluation of cutting apart with it is higher, therefore selects to have the corresponding optimum segmentation that is divided into present node of maximum COST value.

Need to prove that evaluation function COST account form is not limited to formula (5), can as evaluation function COST, can be expressed as such as evaluation function as long as can express the function of size differences relation between PGCN and the PRUN

Wherein, k1, a1, k2, a2 are arbitrary constant.

In step 143, the optimum segmentation of each node is converted to corresponding improvement logical block, comprise being converted to LUT4, LUT5, LUTAND, LUTOR.

In step 144, the redundancy of removing in the step 143 is improved logical block, comprises and removes redundant LUT4, LUT5, LUTAND or LUTOR, thereby finish by the common group combinational logic circuit to the Technology Mapping that improves logical block rank circuit.

Obviously, under the prerequisite that does not depart from true spirit of the present invention and scope, the present invention described here can have many variations.Therefore, the change that all it will be apparent to those skilled in the art that all should be included within the scope that these claims contain.The present invention's scope required for protection is only limited by described claims.

Claims (8)

1. a process mapping method is characterized in that, comprising:

Step a resolves into the circuit that 2 input logic unit form with the common group combinational logic circuit in the initial logic net table;

Step b as a node, take this node as root node, and is cut apart based on being improved logical block described 2 input logic unit to this node, all that find out again this node are cut apart;

Step c, estimate every kind and cut apart the overlay node quantity PGCN of institute, and estimate the corresponding actual employed improvement number of logic cells PRUN of cutting apart, then with this overlay node quantity PGCN and actual the use corresponding the cutting apart as optimum segmentation of maximal value of improving ratio between the number of logic cells PRUN;

Steps d is converted to corresponding improvement logical block with described optimum segmentation, in order to finish by initial logic net table to the Technology Mapping that improves other logic netlist of logical block level;

Cut apart the overlay node quantity PGCN of institute and be for described every kind,

$\mathrm{PGCN}=1+\frac{{\mathrm{PGCN}}_{\mathrm{SUBCUT}1}}{{\mathrm{FANOUT}}_{\mathrm{SUBCUT}1}}+......\frac{{\mathrm{PGCN}}_{\mathrm{SUBCUTn}}}{{\mathrm{FANOUT}}_{\mathrm{SUBCUTn}}}$

Wherein, PGCN _SUBCUTnBe that described n of cutting apart is cut apart institute's overlay node quantity, and n is positive integer, FANOUT _SUBCUTnThe quantity that described n is cut apart the SUBCUTn fan out unit;

Described actual use improves number of logic cells PRUN and is,

$\mathrm{PGCN}=\mathrm{RUN}+\frac{{\mathrm{PGCN}}_{\mathrm{SUBCUT}1}-{\mathrm{RUN}}_{\mathrm{SUBCUT}1}}{{\mathrm{FANOUT}}_{\mathrm{SUBCUT}1}}+......\frac{{\mathrm{PGCN}}_{\mathrm{SUBCUTn}}-{\mathrm{RUN}}_{\mathrm{SUBCUTn}}}{{\mathrm{FANOUT}}_{\mathrm{SUBCUTn}}}$

Wherein, RUN is described actual desired seek table LUT quantity, the PRUN cut apart _SUBCUTnThat described n of cutting apart is cut apart actual use improvement number of logic cells, RUN _SUBCUTnThat described n is cut apart actual desired seek table LUT quantity, FANOUT _SUBCUTnThe quantity that described n is cut apart the SUBCUTn fan out unit.

2. a kind of process mapping method as claimed in claim 1 is characterized in that, described method is further comprising the steps of:

General sequential logical circuit is mapped to the register that possesses specific function.

3. a kind of process mapping method as claimed in claim 2 is characterized in that, described possess the specific function register and comprise synchronous reset circuit, synchronously setting circuit, Circuit of Data Synchronous.

4. a kind of process mapping method as claimed in claim 1 is characterized in that, comprises before described step a:

Step e adopts Binary Decision Diagrams BDD technology to remove the redundant logical device of common group in the initial logic net table.

5. a kind of process mapping method as claimed in claim 1 is characterized in that, in step a, the is olation of selecting to have minimum-depth decomposes described common group combinational logic circuit.

6. a kind of process mapping method as claimed in claim 1 is characterized in that, comprises after described steps d:

Step f is converted to the actual physics device with the improvement logical block described in the step c.

7. a kind of process mapping method as claimed in claim 1 is characterized in that, is divided into 4 inputs when cutting apart, RUN=1 when described; Be divided into 5 inputs or 8 inputs when cutting apart, RUN=2 when described.

8. a kind of process mapping method as claimed in claim 1, it is characterized in that the combination of described improvement logical block comprises that four inputs cut apart that look-up table LUT4, five inputs are cut apart look-up table LUT5, look-up table LUTAND is cut apart in eight inputs and look-up table LUTOR is cut apart in eight inputs;

Described LUT4 is made of a look-up table LUT, and described LUT5, LUTAND, LUTOR are made of two look-up table LUT respectively.

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