CN105610427B - A kind of programmable logic cells based on and-or inverter structure - Google Patents

Abstract

The invention discloses a programmable logic unit based on an AND or NOT structure, which includes an AND or non basic unit, and the AND or non basic unit realizes the first input data and the second input data under the control of the output control signal of the SRAM storage unit. The function of two input data "and not" or "or not"; wherein, the AND or non-basic unit includes: a pull-up network pFET logic circuit module and a pull-down network nFET logic circuit module; the pull-up network pFET logic circuit module includes at least One first to at least one fifth pFET tube, the pull-down network nFET logic circuit module includes at least one first to at least one fifth nFET tube. The present invention uses a programmable NANDOR gate (NANDOR) as the basic AIC unit. Compared with the NANDOR structure, the number of circuit stages that the signal needs to pass through is less, the area is smaller, and the speed can be faster. By adjusting the parameters of the tube, it can achieve The difference in delay between different functions is small.

Description

A Programmable Logic Unit Based on AND-OR Structure

technical field

The invention belongs to the technical field of computer programmable logic, in particular to a programmable logic unit based on an NANDOR structure.

Background technique

Since the development of programmable logic devices, it has become an indispensable medium for the realization of digital circuits. The flexible programmability of programmable devices makes it configurable to implement different logic functions to meet the functional requirements of different users. With the advancement of manufacturing technology, the performance of programmable logic devices has been continuously improved. In addition, programmable logic devices also have a shorter product development time. The above advantages make programmable logic devices widely used in different application fields.

A programmable logic device is mainly composed of a programmable logic block (Configurable Logic Block, CLB) and a programmable interconnection module. The CLB implements the sub-logic functions in the application circuit, and the programmable interconnection module connects each sub-logic to form a complete application circuit logic function.

A programmable logic element (Logic Element, LE) of a mainstream FPGA chip is usually realized by a look-up table structure. FIG. 1 shows a typical implementation of a programmable logic element 100 with a 4-input look-up table structure. The programmable logic unit LUT4 is composed of 1 multiplexer MUX16S1 (select 1 from 16) 110 and 16 SRAM storage units 121, wherein the multiplexer MUX16S1 110 is composed of 5 MUX4S1 (select 1 from 4) 120. When a signal is connected to the input terminal, when the storage unit SRAM121 is configured with different values, different programmable functions can be realized. The programmable logic unit of this structure has a powerful programmable capability, but its high flexibility also brings corresponding performance overheads such as area and delay. At the same time, since this programmable logic unit structure has only one output terminal, when there is redundancy in the programmable function of the look-up table, the configurable resources cannot be reused.

Therefore, Hadi Parandeh et al. of the University of Technology in Lausanne, Switzerland first proposed an FPGA logic unit based on an And-Inverter Cone (AIC) structure (US Pat. No. 8,836,368B2). As shown in FIG. 2 , taking a three-level AIC logic cone AIC3 200 as an example, the AIC3 is composed of four bottom AIC units (Bottom AIC Element, EAE) 210 and three basic AIC units (Basic AIC Element, BAE) 220 . Wherein, the basic AIC unit 220 is made up of a two-input NAND gate 221, an inverter 222, a two-input selector 223, and an SRAM configuration unit 224; the bottom AIC unit 210 actually includes a basic AIC unit 220, and the rest Part of the circuit is composed of two two-input selectors 211 , two inverters 212 , and two SRAM configuration units 213 . An AIC3200 has 8 input terminals i0-i7, when the storage unit SRAM is configured with different values, AIC3 can realize different logic functions. In the example, AIC3 starts to output from at least one second layer, and at least one operation result of the first layer is not output. Because any function can be rewritten into a combined expression of AND and NOT units through logical operations. Thus any function can be mapped to the AIC combination structure. This kind of logic unit has the characteristics of multiple output and multiple input. On the one hand, it can satisfy the operation function of multi-bit width input, and at the same time, it can conveniently use the intermediate output results to effectively utilize programmable resources.

Wherein the implementation form of the basic AIC unit BAE220 is generally shown as 300 in FIG. , 320, 330, 340 shown. The whole AIC unit BAE220 needs 12 transistors to realize.

When this programmable logic unit based on the NAND structure is configured for different operation functions, the basic AIC unit will have different path selections, that is, whether to pass through the inverter or not. Without the inverter, the basic AIC unit realizes the function of the NAND gate; if the path of the inverter is selected, the basic AIC unit realizes the function of the AND gate. The two configurations have different delay performances on the delay path, which brings inconvenience to the application circuit to realize the later timing constraints.

Contents of the invention

In view of this, the present invention proposes a programmable logic unit based on an NOR cone structure, that is, a programmable NOR gate (NANDOR) is used as a basic logic cone unit.

The present invention proposes a programmable logic unit based on an AND or NOT structure, which includes an AND or non-basic unit, and the AND or non-basic unit realizes the first input data and the second input data under the control of the output control signal of the SRAM storage unit. 2. The function of "AND" or "OR" of the input data can realize any logical function expression through multi-level interconnection;

Wherein, the AND-OR basic unit includes: a pull-up network pFET logic circuit module and a pull-down network nFET logic circuit module; the pull-up network pFET logic circuit module includes at least one first pFET to at least one fifth pFET tube;

The sources of the at least one first pFET tube and the at least one third pFET tube are connected to a power supply, the drains of the at least one first pFET tube are connected to the sources of at least one second pFET tube and at least one fifth pFET tube, The drain of the at least one third pFET is connected to the source of the at least one fourth pFET and the drain of the at least one fifth pFET, and the at least one second pFET and the at least one fourth The drain signal line y end of the pFET tube; the gates of the at least one first to the at least one second pFET tube are respectively connected to one of the first input data and the output control signal of the SRAM memory unit, the said A gate of at least one of at least one third pFET to at least one fourth pFET is connected to the second input data, and a gate of at least one fifth pFET is connected to an inversion signal of an output control signal of the SRAM memory unit.

The number of tubes required for the realization of the circuit of the present invention is less than that of the NAND-cone structure in the prior art, the area is better than that of the NAND-cone basic AIC unit in Fig. 2, and the speed is better than that of the original structure. When different functions are realized, its time delay The difference is small, and the delay of different functions can be the same by adjusting the tube parameters.

Description of drawings

Fig. 1 is a schematic diagram of the programmable logic unit structure of a typical 4-input look-up table structure in the prior art;

Fig. 2 is a kind of structure schematic diagram of FPGA logic unit based on and non-cone (And-Inverter Cone, AIC) structure in the prior art;

Fig. 3 is the realization structure diagram based on the basic AIC unit in the And-Inverter Cone (AIC) structure in the prior art;

Fig. 4 is the circuit realization diagram of NANDOR unit (NANDOR) by COMS standard composite logic gate in the first embodiment of the present invention;

Fig. 5 is the circuit realization diagram of NANDOR unit (NANDOR) by COMS standard composite logic gate in the second embodiment of the present invention;

Fig. 6 is the circuit implementation diagram of the NANDOR unit (NANDOR) by the COMS standard composite logic gate in the third embodiment of the present invention;

Fig. 7 is the circuit implementation diagram of the NANDOR unit (NANDOR) by the COMS standard composite logic gate in the fourth embodiment of the present invention;

Fig. 8 is the circuit implementation diagram of the NANDOR unit (NANDOR) by the COMS standard composite logic gate in the fifth embodiment of the present invention;

FIG. 9 is a circuit realization diagram of the NANDOR unit (NANDOR) through the CMOS standard composite logic gate in the sixth embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

The present invention proposes a programmable logic unit based on a NANDOR structure, which is used to replace the AIC basic unit module BAE of 300 shown in FIG. 3 . The basic working principle of BAE is that it can control the storage value of the SRAM unit through programming to realize the logic function of "and not" or "and". Through the multi-level connection of the structure shown in Figure 2, complex logic functions can be realized. According to Demogan's theorem, any function can be rewritten into a combined expression of AND and NOT units through logical operations, so the function can be realized through the AIC structure.

The programmable NANDOR unit (NANDOR) proposed by the present invention can also control the SRAM storage unit, and the unit module function can be configured as a “AND” or “NOR” function, and any NANDOR can also be realized through multilevel interconnection. logical function expression.

The NANDOR unit proposed by the present invention is realized by the COMS standard composite logic gate, and the whole NANDOR unit (NANDOR) module includes two parts: a pull-up network pFET logic circuit module and a pull-down network nFET logic circuit module.

In the first embodiment of the present invention, a programmable logic unit based on an AND or NOT structure is proposed, which includes an AND or non-basic unit, and the AND or non-basic unit realizes the first step under the control of the output control signal of the SRAM storage unit. The function of "AND" or "NOR" of the first input data and the second input data can realize any logical function expression through multi-level interconnection;

Wherein, the AND-OR basic unit includes: a pull-up network pFET logic circuit module and a pull-down network nFET logic circuit module; the pull-up network pFET logic circuit module includes at least one first pFET tube to at least one fifth pFET tube;

The source of the at least one first pFET tube and the at least one fourth pFET tube is connected to the power supply, the drain of the at least one first pFET tube is connected to the source of at least one second pFET tube, and the at least one fourth pFET tube The drain of the tube is connected to the source of the at least one fifth pFET tube, the drain of the at least one second pFET is connected to the source of the at least one third pFET tube, and the at least one third pFET tube is connected to the source of the at least one third pFET tube. The drain of the at least one fifth pFET tube is connected to the y terminal of the signal line; wherein, the drain of the at least one fourth pFET tube is interconnected with the drain of the at least one first pFET tube or the at least one fourth pFET tube The drain of the tube is interconnected with the drain of at least one second pFET tube to divide the pull-up network pFET logic circuit module into two parts connected in series up and down; the at least one first pFET tube to at least one third pFET tube The gates of the gates are respectively connected to one of the first input data and the output control signal of the SRAM storage unit, and the gates of the at least one fourth pFET to at least one fifth pFET are connected to the second input data and the SRAM One of the output control signals of the storage unit.

The pull-down network nFET logic circuit module includes at least one first nFET tube to at least one fifth nFET tube;

The drains of the at least one first nFET and the at least one fourth nFET are connected to the signal line y terminal, the source of the at least one first nFET is connected to the drain of at least one second nFET, and the at least one The source of the fourth nFET is connected to the drain of the at least one fifth nFET, the source of the at least one second nFET is connected to the drain of the at least one third nFET, and the at least one third nFET The source of the tube and the at least one fifth nFET tube is grounded; wherein, the source of the at least one fourth nFET tube is interconnected with the source of the at least one first nFET tube or the at least one fourth nFET tube The source of the at least one second nFET tube is interconnected to divide the pull-down network nFET logic circuit module into two parts connected in series up and down; the gate of the at least one first nFET tube to at least one third nFET tube The poles are respectively connected to one of the output control signals of the first input data and the SRAM storage unit, and the gates of the at least one fourth nFET to at least one fifth nFET are connected to the second input data and the SRAM storage unit One of the output control signals.

The circuit structures shown in FIGS. 4-6 are schematic diagrams of several typical circuit structures of the programmable logic unit based on the AND or NOR structure proposed by the first embodiment of the present invention.

As shown in FIG. 4 , the pull-up pFET logic circuit module 410 is composed of five pFET transistors 411 , 412 , 413 , 414 , and 415 and one SRAM unit 416 . Among them, the source of the tube 411 is connected to the power supply, the drain is connected to the source of the tube 412, and the gate is controlled by the output _s of the SRAM unit; the source of the tube 412 is connected to the drain of the tube 411, and the drain is connected to the sources of the tubes 413 and 415 , and connect the drain of tube 414 at the same time, the gate is controlled by signal a; the source of tube 413 is connected to the drain of 412, the drain is connected to signal line y terminal, and the gate is controlled by signal a; the source of tube 414 is connected to power supply, and the drain The source of the tube 415 is connected to the source, and the gate is controlled by the signal b; the source of the tube 415 is connected to the drain of the tubes 412 and 414, and the drain is connected to the signal line y, and the gate is controlled by the output s of the SRAM unit.

When the stored value in the SRAM unit 416 is configured as a high level 1, the pFET tubes 411 and 415 are cut off, the tubes 413 and 414 are connected in series, and the a and b signals respectively control the tubes 413 and 414, realizing the pFET circuit logic function of NOR operation; When the stored value in the SRAM unit 416 is configured as low level 0, the pFET tubes 411 and 415 are turned on, the tubes 412 and 414 are connected in parallel, the a and b signals respectively control the parallel connection of the tubes 412 and 414, 413 and 415, and the two are connected in series , realizing the logic function of pFET circuit for NAND operation. That is, the stored value in the SRAM unit 416 determines the logic function of the NANDOR pFET circuit.

Similarly, module 420 in FIG. 4 is an nFET logic circuit module, which is composed of five nFET tubes 421, 422, 423, 424, and 425, and is symmetrical to the pFET logic circuit in FIG. 4.

Among them, the drain of the tube 421 is connected to the signal line y terminal, the source is connected to the drain of the tube 422, and the gate is controlled by the output s of the SRAM unit; the drain of the tube 422 is connected to the source of the tube 421, and the source is connected to the tubes 423 and 425 The drain of the tube 424 is connected to the source of the tube 424, and the gate is controlled by the signal a; the drain of the tube 423 is connected to the source of the 422, the source is grounded, and the gate is controlled by the signal a; the drain of the tube 424 is connected to the signal line y The source is connected to the drain of the tube 425, and the gate is controlled by the signal b; the drain of the tube 425 is connected to the source of the tubes 422 and 424, the source is grounded, and the gate is controlled by the output s of the SRAM unit. Its s signal comes from the SRAM unit shared by 410 modules.

When the stored value in the SRAM unit is configured as high level 1, the nFET tubes 421 and 425 are turned on, the tubes 422 and 424 are connected in parallel, the a and b signals respectively control the parallel connection of the tubes 422 and 424, 423 and 425, and the two are connected in series again. The nFET circuit logic function of NOR operation is realized; when the storage value in the SRAM unit is configured as low level 0, the nFET tubes 421 and 425 are cut off, the tubes 423 and 424 are connected in series, and the a and b signals respectively control the tubes 423 and 424 to realize nFET circuit logic function for NAND operation.

The module 410 and the module 420 are connected through the y signal line and output from the port of the y signal line, that is, the complete NAND or NOR logic function can be realized by configuring the SRAM unit.

Similarly, the pFET logic circuit of the NANDOR basic unit can also be realized by the circuit structures shown in 510 in FIG. 5 and 610 in FIG. 6 .

Wherein, the s signal and a data connected to the first-third pFET tube in the module 410 shown in FIG. 4 are interchangeable. Similarly, the s signal and a data connected to the first-third nFET tube in the module 420 interchangeable.

As shown in Figure 5, the source of tube 511 in the 510 module is connected to the power supply, the drain is connected to the source of tube 512, and the drain of tube 514 is connected at the same time, and the gate is controlled by signal a; the source of tube 512 is connected to tube 511, The drain of 514 is connected to the source of tube 513 and the source of tube 515. The gate is controlled by signal a; the source of tube 513 is connected to the drain of 512, the drain is connected to the y terminal of the signal line, and the gate It is controlled by the output s of the SRAM unit; the source of the tube 514 is connected to the power supply, the drain is connected to the source of the tubes 512 and 515, and the gate is controlled by the output s of the SRAM unit; the source of the tube 515 is connected to the drain of the tubes 511 and 514, and the drain is connected to the Signal line y terminal, the gate is controlled by signal b.

As shown in Figure 6, the source of the tube 611 in the 610 module is connected to the power supply, the drain is connected to the source of the tube 612, and the drain of the tube 614 is connected at the same time, and the gate is controlled by the signal a; the source of the tube 612 is connected to the tube 611 , The drain of 614 is connected to the source of 615 at the same time, the drain is connected to the source of the tube 613, and the gate is controlled by the output s of the SRAM unit; the source of the tube 613 is connected to the drain of 612, and the drain is connected to the y terminal of the signal line, The gate is controlled by signal a; the source of the tube 614 is connected to the power supply, the drain is connected to the source of the tubes 612 and 615, and the gate is controlled by the output s of the SRAM unit; the source of the tube 615 is connected to the drain of the tubes 611 and 614, and the drain is connected to Signal line y terminal, the gate is controlled by signal b.

The nFET logic circuit of the NANDOR basic unit can also be realized by the circuit structures shown in 511 in FIG. 5 and 611 in FIG. 6 .

As shown in Figure 5, the drain of the tube 521 in the 520 module is connected to the y terminal of the signal line, the source is connected to the drain of the tube 522, and the source of the tube 524 is connected at the same time, and the gate is controlled by the signal a; the drain of the tube 522 is connected to The source of the sub 521, 524, the source is connected to the drain of the sub 523, and the gate is controlled by the signal a; the drain of the tube 523 is connected to the source of the 522, the source is grounded, and the gate is controlled by the output s of the SRAM unit; the tube 524 The drain is connected to the y terminal of the signal line, the source is connected to the drain of the tubes 522 and 525, and the source of 521 is connected at the same time, and the gate is controlled by the output s of the SRAM unit; the drain of the tube 525 is connected to the source of the tubes 521 and 524, and at the same time Take over the drain of sub-522, the source is grounded, and the gate is controlled by signal b.

As shown in Figure 6, the drain of the tube 621 in the 620 module is connected to the y terminal of the signal line, the source is connected to the drain of the tube 622, and the source of the tube 624 is connected at the same time, and the gate is controlled by the signal a; the drain of the tube 622 is connected to the The source of the sub 621, 624, the source is connected to the drain of the sub 623, and the gate is controlled by the output s of the SRAM unit; the drain of the tube 623 is connected to the source of the 622, the source is grounded, and the gate is controlled by the signal a; the tube 624 The drain is connected to the y terminal of the signal line, the source is connected to the drains of the tubes 622 and 625, and the source of the tube 621, and the gate is controlled by the output s of the SRAM unit; the drain of the tube 625 is connected to the sources of the tubes 621 and 624, and the source The pole is grounded and the gate is controlled by signal b.

The logic function realized by the circuit structure shown in above-mentioned Fig. 5 and Fig. 6 is the same as the logic function of the structure shown in Fig. 4, that is, when s is high level 1, the pull-up network pFET logic circuit module Realize the pFET circuit logic function of "NOR" operation, the pull-down network nFET logic circuit module realizes the nFET circuit logic function of "NOR" operation; when the output control signal of the SRAM storage unit is low level, the pull-up network The pFET logic circuit module realizes the pFET circuit logic function of "AND" operation, and the pull-down network nFET logic circuit module realizes the nFET circuit logic function of "AND" operation.

The above programmable logic unit based on the AND-OR structure proposed by the present invention can also be realized by the second circuit structure proposed in the second embodiment.

The programmable logic unit based on the AND or NOR structure disclosed in the second embodiment of the present invention includes an AND or non-basic unit, and the AND or non-basic unit realizes the first input under the control of the output control signal of the SRAM storage unit The function of "AND" or "OR" between the data and the second input data can realize any logical function expression through multi-level interconnection;

Wherein, the AND-OR basic unit includes: a pull-up network pFET logic circuit module and a pull-down network nFET logic circuit module; the pull-up network pFET logic circuit module includes at least one first pFET to at least one fifth pFET tube;

The sources of the at least one first pFET tube and the at least one third pFET tube are connected to a power supply, the drains of the at least one first pFET tube are connected to the sources of at least one second pFET tube and at least one fifth pFET tube, The drain of the at least one third pFET is connected to the source of the at least one fourth pFET and the drain of the at least one fifth pFET, and the at least one second pFET and the at least one fourth The drain signal line y end of the pFET tube; the gates of the at least one first to the at least one second pFET tube are respectively connected to one of the first input data and the output control signal of the SRAM memory unit, the said A gate of at least one of at least one third pFET to at least one fourth pFET is connected to the second input data, and a gate of at least one fifth pFET is connected to an inversion signal of an output control signal of the SRAM memory unit.

The pull-down network nFET logic circuit module includes at least one first nFET to at least one fifth nFET;

The drains of the at least one first nFET tube and the at least one third nFET tube are connected to the y terminal of the signal line, and the source electrodes of the at least one first nFET tube are connected to at least one second nFET tube and at least one fifth nFET tube the drain of the at least one third nFET, the source of the at least one third nFET is connected to the drain of the at least one fourth nFET and the source of the at least one fifth nFET, the at least one second nFET and the The source of at least one fourth nFET tube is grounded; the gates of the at least one first to at least one second nFET tube are respectively connected to one of the first input data and the output control signal of the SRAM memory unit, so The gate of at least one of the at least one third nFET to at least one fourth nFET is connected to the second input data, and the gate of at least one fifth nFET is connected to the inversion signal of the output control signal of the SRAM memory unit .

A typical implementation of the second circuit structure proposed in the second embodiment of the present invention is shown in FIGS. 7-8 and will be described in detail below.

The pFET logic circuit module of the NANDOR basic unit can also be realized by the module 710 shown in FIG. 7 . The module 710 is composed of five pFET tubes 711, 712, 713, 714 and 715, a SRAM unit 716 and an inverter module.

The output terminal s of the SRAM cell 716 is connected to the input terminal of the inverter to generate an inverted output ns.

In the 710 module, the source of the tube 711 is connected to the power supply, the drain is connected to the source of the tubes 712 and 715, and the gate is controlled by signal a; the source of the tube 712 is connected to the drain of the tube 711, the drain is connected to the y terminal of the signal line, and the gate Controlled by the signal s; the source of the tube 713 is connected to the power supply, the drain is connected to the source of the tube 714 and the drain of the tube 715, and the gate is controlled by the signal s; the source of the tube 714 is connected to the drain of the 713, and the drain is connected to the signal line y terminal, the gate is controlled by signal b; the gate of tube 715 is controlled by signal ns.

When the value stored in the SRAM unit 716 is configured as a high level 1, that is, the s signal terminal is 1, and the ns is a low level 0, the tubes 712 and 713 are turned off, and the 715 is turned on, and the a and b signals control the tubes 711 and 715 respectively. 714, tubes 711 and 714 are connected in series to realize the logic function of pFET circuit for NOR operation; when the stored value in SRAM unit 716 is configured as low level 0, that is, the s signal terminal is 0, ns is low level 1, the tube 715 is turned off, 712 and 713 are turned on, and tubes 711 and 714 are connected in parallel, respectively controlled by a and b signals, realizing the pFET circuit logic function of NAND operation.

Similarly, module 720 in FIG. 7 is an nFET logic circuit module, which is composed of five nFET tubes 721, 722, 723, 724, and 725, and is symmetrical to the pFET logic circuit in FIG. 7. Among them, the s signal comes from the SRAM unit shared with the 710 module.

In the 720 module, the drain of the tube 721 is connected to the signal y terminal, the source is connected to the drains of the tubes 722 and 725, and the gate is controlled by the signal a; the drain of the tube 722 is connected to the source of the tube 721, the source is grounded, and the gate is controlled by the signal s control; the drain of the tube 723 is connected to the signal y terminal, the source is connected to the drain of the tube 724 and the source of the tube 725, and the gate is controlled by the signal s; the drain of the tube 724 is connected to the source of the 723, the source is grounded, and the gate Controlled by signal b; the gate of tube 725 is controlled by signal ns.

When the stored value in the SRAM unit is configured as high level 1, the s signal terminal is 1, and ns is low level 0. The nFET tubes 722 and 723 are turned on, 715 is turned off, the tubes 722 and 723 are connected in parallel, and the a and b signals control the tubes 722 and 723 respectively, realizing the nFET circuit logic function of the NOR operation; when the stored value in the SRAM unit is configured as a low level When 0, the s signal terminal is 0, and ns is low level 1. The nFET tubes 722 and 723 are cut off, the tubes 721 and 724 are connected in series, and the signals a and b respectively control the tubes 721 and 724, realizing the nFET circuit logic function of NAND operation.

The module 710 and the module 720 are connected through the y signal line and output from the port of the y signal line, that is, the complete NAND or NOR logic function can be realized by configuring the SRAM unit.

Similarly, the pFET and nPFET logic circuits of the NANDOR basic unit can also be realized by the module circuits 810 and 820 shown in FIG. 8 .

In the 810 module, the source of the tube 811 is connected to the power supply, the drain is connected to the source of the tubes 812 and 815, and the gate is controlled by signal a; the source of the tube 812 is connected to the drain of the tube 811, the drain is connected to the y terminal of the signal line, and the gate Controlled by the signal s; the source of the tube 813 is connected to the power supply, the drain is connected to the source of the tube 814 and the drain of the tube 815, and the gate is controlled by the signal b; the source of the tube 814 is connected to the drain of the 813, and the drain is connected to the signal line y terminal, the gate is controlled by the signal b; the gate of the tube 815 is controlled by the signal ns.

In the 820 module, the drain of the tube 821 is connected to the signal y terminal, the source is connected to the drains of the tubes 822 and 825, and the gate is controlled by the signal a; the drain of the tube 822 is connected to the source of the tube 821, the source is grounded, and the gate is controlled by the signal s control; the drain of tube 823 is connected to the signal y terminal, the source is connected to the drain of tube 824 and the source of tube 825, and the gate is controlled by signal b; the drain of tube 824 is connected to the source of 823, the source is grounded, and the gate Controlled by signal b; the gate of tube 825 is controlled by signal ns.

Among them, the s signal and a data connected to the first-second pFET tube in the module 810 shown in FIG. 8 are interchangeable. Similarly, the s signal and a data connected to the first-second nFET tube in the module 820 interchangeable.

The pull-up network pFET logic circuit modules and the pull-down network nFET logic circuit modules shown in Figures 7-8 can be combined arbitrarily to form a NANDOR basic unit.

The above programmable logic unit based on the AND-OR structure proposed by the present invention can also be realized by the third circuit structure proposed in the third embodiment.

The programmable logic unit based on the AND or NOT structure proposed in the third embodiment of the present invention includes an AND or non-basic unit, and the AND or non-basic unit realizes the first input under the control of the output control signal of the SRAM storage unit The function of "AND" or "OR" between the data and the second input data can realize any logical function expression through multi-level interconnection;

Wherein, the AND-OR basic unit includes: a pull-up network pFET logic circuit module and a pull-down network nFET logic circuit module; the pull-up network pFET logic circuit module includes at least one first pFET tube to at least one sixth pFET tube;

The source of the at least one first pFET tube and the at least one fourth pFET tube is connected to the power supply, the drain of the at least one first pFET tube is connected to the source of at least one second pFET tube, and the at least one fourth pFET tube The drain of the tube is connected to the source of the at least one fifth pFET tube, the drain of the at least one second pFET is connected to the source of the at least one third pFET tube, and the drain of the at least one fifth pFET tube is The pole is connected to the source of the at least one sixth pFET tube, and the drains of the at least one third pFET tube and the at least one sixth pFET tube are connected to the y terminal of the signal line; wherein, the at least one fourth pFET tube The drain is interconnected with the drain of the at least one first pFET or the drain of the at least one fourth pFET is interconnected with the drain of at least one second pFET, so that the pull-up network pFET logic The circuit module is divided into two parts connected in series up and down; the gates of the at least one first pFET tube to at least one third pFET tube are respectively connected to one of the first input data and the output control signal of the SRAM memory unit, and the at least one Gates of one fourth pFET to at least one sixth pFET are connected to one of the second input data and the output control signal of the SRAM memory unit.

The pull-down network nFET logic circuit module includes at least one first nFET tube to at least one sixth nFET tube;

The drains of the at least one first nFET and the at least one fourth nFET are connected to the signal line y terminal, the source of the at least one first nFET is connected to the drain of at least one second nFET, and the at least one The source of the fourth nFET is connected to the drain of the at least one fifth nFET, the source of the at least one second nFET is connected to the drain of the at least one third nFET, and the at least one fifth nFET The source of the tube is connected to the drain of the at least one sixth nFET tube, and the sources of the at least one third nFET tube and the at least one sixth nFET tube are connected to the signal line y end; The sources of the four nFET tubes are connected to the sources of at least one second nFET tube, so as to divide the pull-up network pFET logic circuit module into two parts connected in series up and down; the at least one first nFET tube to at least one third nFET tube The gates of the tubes are respectively connected to one of the first input data and the output control signal of the SRAM memory unit, and the gates of the at least one fourth nFET tube to at least one sixth nFET tube are connected to the second input data and One of the output control signals of the SRAM memory cell.

A typical implementation of the third circuit structure is shown in Fig. 9, which will be described in detail below.

The pFET logic circuit module of the NANDOR basic unit can also be realized by the 910 module shown in FIG.

As shown in Figure 9, the source of the tube 911 in the 910 module is connected to the power supply, the drain is connected to the source of the tube 912, and the gate is controlled by the output s of the SRAM unit; the source of the tube 912 is connected to the drain of the tube 911, and the drain is connected to the The source and gate of tube 913 and 915 are controlled by signal a; the source of tube 913 is connected to the drain of tube 912 and 914, the drain is connected to signal line y terminal, and the gate is controlled by signal a; the source of tube 914 is connected to power supply , the drain is connected to the source of the tube 913, 915, the gate is controlled by the signal b; the source of the tube 915 is connected to the drain of the tube 912, 914, the drain is connected to the source of the tube 916, and the gate is controlled by the output s of the SRAM unit; The source of the tube 916 is connected to the drain of the tube 915, the drain is connected to the y terminal of the signal line, and the gate is controlled by the signal b.

When the stored value in the SRAM unit 917 is configured as a high level 1, the tubes 911 and 915 are turned off, the a signal controls the tubes 912 and 913, the b signal controls the tubes 914 and 916, and the tubes 913 and 914 are connected in series to realize the pFET circuit of the NOR operation Logic function; when the value stored in the SRAM unit 917 is configured as low level 0, the tubes 911 and 915 are turned on, realizing the logic function of the pFET circuit for NAND operation.

Similarly, module 920 in FIG. 9 is an nFET logic circuit module, which is composed of six pFET tubes 921, 922, 923, 924, 925, and 926, which are symmetrical to the pFET logic circuit in FIG. 9 . Among them, the s signal comes from the SRAM unit shared with the 910 module.

In the 920 module, the drain of the tube 921 is connected to the signal line y terminal, the source is connected to the drain of the tube 922, and the gate is controlled by the output s of the SRAM unit; the drain of the tube 922 is connected to the source of the tube 921, and the source is connected to the tube 923, The drain of tube 925 is connected to the source of tube 924, and the gate is controlled by signal a; the drain of tube 923 is connected to the source of tube 922, the source is grounded, and the gate is controlled by signal a; the drain of tube 924 is connected to the signal line At the y terminal, the source is connected to the drain of the sub-923 and 925, and the gate is controlled by the signal b; the drain of the tube 925 is connected to the source of the sub-922 and 924, and the source is connected to the drain of the sub-926, and the gate is output by the SRAM unit s Control: the drain of the tube 926 is connected to the source of the tube 925, the source is grounded, and the gate is controlled by signal b.

When the stored value in the SRAM unit is configured as a high level 1, the nFET tubes 921 and 923 are turned on, realizing the nFET circuit logic function of the NOR operation; when the stored value in the SRAM unit is configured as a low level 0, the nFET tube 921 and 923 are cut off, tubes 923 and 924 are connected in series, a and b signals respectively control tubes 923 and 924, realizing the nFET circuit logic function of NAND operation.

The module 910 and the module 920 are connected through the y signal line and output from the port of the y signal line, that is, the complete NAND or NOR logic function can be realized by configuring the SRAM unit.

Wherein, the s signal and a data connected to the first-third pFET tubes in the module 910 shown in FIG. 9 are interchangeable, and the s signal and b signal connected to the third to sixth pFET tubes are interchangeable. Similarly, The s signal and a data connected to the first-third nFET tubes in the module 920 are interchangeable, and the s signal and b signal connected to the third to sixth nFET tubes are interchangeable.

The implementation form of the NANDOR basic unit can also be realized by any combination of pFET logic circuit modules and nFET logic circuit modules in the above units.

The pull-up network pFET logic circuit module and the pull-down network nFET logic circuit module shown in Figure 4-9 can be combined arbitrarily to form a NANDOR basic unit. Furthermore, the pull-up network pFET logic circuit modules shown in FIGS. 4-9 proposed by the present invention can also be combined with any other pull-down network nFET logic circuit modules in the prior art to form a NANDOR basic unit.

The present invention proposes a programmable logic unit based on an AND-OR cone structure, which can be used as a basic unit of AIC logic to realize various complex logic functions through multi-layer cascading. The structure of this NANDOR logic unit is simple. Compared with the basic AIC unit in Figure 2, the number of tubes required to realize a complete function can be reduced, and the delay path passed is also relatively small, so the area and delay performance are better than the existing ones. The AIC basic unit in Figure 2 of the prior art is better. At the same time, the NANDOR logic unit alleviates the problem that the AIC basic unit in FIG. to the desired range.

The NANDOR unit proposed by the present invention maintains the fast speed compared with the traditional LUT structure of the AIC basic unit in Figure 2, has strong scalability, can reuse logic resources, and improves resource utilization, and is more efficient in structural realization. It is simple, smaller in area, faster in speed, and can make up for the configuration path delay difference problem of the AIC basic unit in Figure 2 by adjusting the tube parameters.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention, and are not intended to limit the present invention. Within the spirit and principles of the present invention, any modifications, equivalent replacements, improvements, etc., shall be included in the protection scope of the present invention.

Claims (8)

1. A kind of programmable logic unit based on and or non-structural, it comprises and or non-basic unit, described and or non-basic unit realizes the first input data and the second input under the control of the output control signal of SRAM storage unit The function of data "and not" or "or not" can realize any logical function expression through multi-level interconnection; Wherein, the AND-OR basic unit includes: a pull-up network pFET logic circuit module and a pull-down network nFET logic circuit module; the pull-up network pFET logic circuit module includes at least one first pFET to at least one fifth pFET tube; The sources of the at least one first pFET tube and the at least one third pFET tube are connected to a power supply, the drains of the at least one first pFET tube are connected to the sources of at least one second pFET tube and at least one fifth pFET tube, The drain of the at least one third pFET tube is connected to the source of the at least one fourth pFET tube and the drain of the at least one fifth pFET tube, and the at least one second pFET and the at least one fourth pFET tube The drain signal line y end of the drain; the gates of the at least one first pFET and the at least one second pFET are respectively connected to one of the first input data and the output control signal of the SRAM memory unit, and the at least one The gate of at least one of the third pFET to at least one fourth pFET is connected to the second input data, and the gate of at least one fifth pFET is connected to the inversion signal of the output control signal of the SRAM storage unit. 2. The programmable logic unit based on an AND-OR structure as claimed in claim 1, wherein the gate of said at least one first pFET tube is connected to the first input data, and the gate of at least one second pFET tube is connected to the SRAM The output signal of the storage unit, the gate of the at least one third pFET tube is connected to the output signal of the SRAM storage unit, and the gate of the at least one fourth pFET tube is connected to the second input data. 3. The programmable logic unit based on an AND-OR structure as claimed in claim 1, wherein the gate of said at least one first pFET tube is connected to the first input data, and the gate of at least one second pFET tube is connected to the SRAM The output signal of the storage unit, the gates of the at least one third pFET transistor and the at least one fourth pFET transistor are connected to the second input data. 4. The programmable logic unit based on an AND-OR structure according to any one of claims 1-3, wherein the pull-down network nFET logic circuit module comprises at least one first nFET to at least one fifth nFET tube; The drains of the at least one first nFET tube and the at least one third nFET tube are connected to the y terminal of the signal line, and the source electrodes of the at least one first nFET tube are connected to the terminals of the at least one second nFET tube and at least one fifth nFET tube The drain, the source of the at least one third nFET is connected to the drain of at least one fourth nFET and the source of the at least one fifth nFET, the at least one second nFET and the at least one first nFET The sources of the four nFET tubes are grounded; the gates of the at least one first to at least one second nFET tube are respectively connected to one of the first input data and the output control signal of the SRAM memory unit, and the at least one The gate of at least one of the third nFET to at least one fourth nFET is connected to the second input data, and the gate of at least one fifth nFET is connected to the inversion signal of the output control signal of the SRAM storage unit. 5. The programmable logic unit based on an AND-OR structure as claimed in claim 4, wherein the gate of said at least one first nFET tube is connected to the first input data, and the gate of at least one second nFET tube is connected to the SRAM The output signal of the storage unit, the gate of the at least one third nFET is connected to the output signal of the SRAM storage unit, and the gate of at least one fourth nFET is connected to the second input data. 6. The programmable logic unit based on an AND-OR structure as claimed in claim 4, wherein the gate of said at least one first nFET tube is connected to the first input data, and the gate of at least one second nFET tube is connected to the SRAM For the output signal of the storage unit, the gates of the at least one third nFET transistor and the at least one fourth nFET transistor are connected to the second input data. 7. as claim 1 or 2 or 3 or 5 or 6 described based on and or the programmable logic unit of NOR structure, wherein, when the output control signal of SRAM storage unit is high level, described pull-up network pFET logic The circuit module realizes the pFET circuit logic function of the first input data and the second input data "NOR" operation, and the pull-down network nFET logic circuit module realizes the nFET circuit logic of the first input data and the second input data "NOR" operation Function; when the output control signal of the SRAM storage unit is low level, the pFET logic circuit module of the pull-up network pFET logic circuit module realizes the "AND" operation of the first input data and the second input data, and the pull-down network nFET The logic circuit module realizes the nFET circuit logic function of "AND" operation of the first input data and the second input data. 8. The programmable logic unit based on the AND or NOR structure as claimed in claim 4, wherein, when the output control signal of the SRAM storage unit is a high level, the pull-up network pFET logic circuit module realizes the first input data and The pFET circuit logic function of the second input data "NOR" operation, the pull-down network nFET logic circuit module realizes the nFET circuit logic function of the first input data and the second input data "NOR" operation; when the output of the SRAM storage unit When the control signal is low level, the pull-up network pFET logic circuit module realizes the pFET circuit logic function of "AND" operation of the first input data and the second input data, and the pull-down network nFET logic circuit module realizes the first input data The nFET circuit logic function of "AND" operation with the second input data.