CN111812490B

CN111812490B - Method for testing signal transmission delay in FPGA chip

Info

Publication number: CN111812490B
Application number: CN201910292343.2A
Authority: CN
Inventors: 谈佳瑛; 俞剑; 陈宁; 徐烈伟; 沈鸣杰
Original assignee: Shanghai Fudan Microelectronics Group Co Ltd
Current assignee: Shanghai Fudan Microelectronics Group Co Ltd
Priority date: 2019-04-12
Filing date: 2019-04-12
Publication date: 2023-04-28
Anticipated expiration: 2039-04-12
Also published as: CN111812490A

Abstract

A method for testing signal transmission delay in an FPGA chip comprises the steps of connecting at least one CLB module and at least one I/O module into a ring oscillator through a programmable interconnection line, wherein the number of the CLB modules in the ring oscillator is an odd number, and LUT modules in the CLB modules are configured as NOT circuits. The invention directly utilizes the logic resource and the interconnection resource of the FPGA chip to carry out signal transmission delay test, thereby avoiding extra circuit cost, saving circuit area, having very flexible and accurate test method and being capable of supporting the test of each position and the test of various transistor types.

Description

Method for testing signal transmission delay in FPGA chip

Technical Field

The invention relates to a method for testing signal transmission delay in an FPGA chip.

Background

An FPGA (field programmable logic array) is an integrated circuit chip that contains configurable logic modules CLB (Configurable Logic Block), input/output modules (I/O modules), and programmable interconnect lines PI (Programmable Interconnect). For different specifications of FPGA chips, 8 x 8, 20 x 20, 44 x 44, and even 92 x 92 CLB arrays can be included, respectively, with 64, 160, 352, and even 448I/O modules and other components necessary to implement programmable wiring.

The performance of an integrated circuit is mainly determined by the propagation delay of signals. As shown in fig. 1, the first method of testing the transmission delay is to analyze the transmission delay of the signal by a separate testing system. Since a large number of chips are fabricated simultaneously on one wafer, scribe areas exist between the chips. The scribe areas may enable the wafer to be singulated into individual chips without damaging the chips themselves. And the scribe area also provides a dedicated test area for use in conventional integrated circuit testing techniques. In the scribing area outside the FPGA chip, the independent ring oscillator test circuit is built and packaged by the same transistor as the transistor in the chip, and then the output frequency of the circuit is measured on a test bench to obtain the transmission delay of the transistor. This delay may reflect manufacturing issues associated with the die. As shown in fig. 2, in the second scheme, some embedded ring oscillator test circuits (PMV) are additionally arranged in the FPGA chip, and the output frequency of the oscillator is obtained through the output port of the FPGA, so as to obtain the transmission delay of the transistor.

As shown in fig. 3, the ring oscillator is connected to form a loop using an odd number of inverters, and satisfies the amplification and feedback conditions of the oscillator, so that a stable clock can be generated. Half the period of the clock is the delay of the whole loop. The clock period generated by the oscillator is measured, and the transmission delay inside each inverter can be calculated according to the number n of stages.

For the first test scheme, its test area is outside the FPGA circuit, and the signal propagation delay at different locations of the wafer is different due to manufacturing variations, so it does not show up well with the signal propagation delay inside the FPGA circuit. Moreover, the frequency of the test performed by the measuring table is limited and is generally lower than 1MHz, and the signal transmission frequency inside the FPGA circuit is generally higher than 100MHz, so that the scheme is difficult to accurately measure.

For the second test scheme, the delay of signal transmission in the FPGA circuit can be tested, but the test circuit is only placed in a small part in the FPGA, and the delay of signal transmission in different positions in the FPGA chip is different due to manufacturing deviation, so the test scheme is not comprehensive. And the internal circuit delay of the FPGA circuit is divided into a front-section delay and a back-section delay, wherein the front-section delay depends on transistors of logic resources, and the back-section delay depends on interconnection resources. In the front-end delay, the delays of the different kinds of transistors are also different, for example, the transmission delays of the high-speed transistors in the core logic block CLB and the high-power transistors in the input/output block are different. Therefore, in order to sufficiently simulate the delay in the circuit, it is necessary to design a plurality of test circuits at the same position, which consumes an area and increases the cost.

Disclosure of Invention

The method for testing the signal transmission delay in the FPGA chip directly utilizes the logic resources and the interconnection resources of the FPGA chip to carry out signal transmission delay test, avoids extra circuit cost, saves circuit area, is very flexible and accurate, and can support the test of each position and the test of various transistor types.

In order to achieve the above objective, the present invention provides a method for testing signal transmission delay in an FPGA chip, wherein at least one CLB module and at least one I/O module are connected to form a ring oscillator through a programmable interconnect, the number of CLB modules in the ring oscillator is an odd number, and LUT modules in the CLB modules are configured as not gates.

The logic function of the LUT module is changed by changing the value of the SRAM in the CLB module.

The modules connected across the programmable interconnect line are changed by changing the value of the SRAM in the programmable interconnect line.

The FPGA chip changes the values of the SRAM in the CLB module and the SRAM in the programmable interconnect by downloading an external bit stream file.

The invention directly utilizes the logic resource and the interconnection resource of the FPGA chip to carry out signal transmission delay test, thereby avoiding extra circuit cost, saving circuit area, having very flexible and accurate test method and being capable of supporting the test of each position and the test of various transistor types.

Drawings

Fig. 1 is a schematic diagram of a first type of signal transmission delay test FPGA in the background art.

Fig. 2 is a schematic diagram of a second type of signal transmission delay test FPGA in the background art.

Fig. 3 is a schematic diagram of a ring oscillator circuit in the background.

Fig. 4 is a circuit diagram of a ring oscillator constructed using LUT modules in the present invention.

Fig. 5 is a schematic diagram of testing signal propagation delays between adjacent modules in an FPGA chip.

Fig. 6 is a schematic diagram of testing signal propagation delay between two adjacent modules in an FPGA chip.

Fig. 7 is a schematic diagram of testing signal propagation delays between four adjacent modules in an FPGA chip.

Fig. 8 is a schematic diagram of testing signal propagation delays of different kinds of transistors in an FPGA chip.

Fig. 9 is a schematic diagram of testing signal propagation delays of transistors in different locations in an FPGA chip.

Detailed Description

The following describes the preferred embodiment of the present invention with reference to fig. 4 to 9.

The FPGA chip contains configurable logic modules CLB (Configurable Logic Block), input/output modules (I/O modules), and programmable interconnect lines that enable the connection between CLB modules, between I/O modules, and between CLB modules and I/O modules. The CLB module, I/O module and programmable interconnect lines all contain SRAM (Static Random Access Memory ), and prior to using the FPGA chip, a bitstream file is downloaded, in which the values of the SRAM in the FPGA chip are described, which can be flexibly changed. By changing the value in the SRAM in the CLB module, different logic functions, such as the functions of various combinational logics of AND gates, OR gates, NOT gates and the like, can be realized. By changing the values in the SRAM in the programmable interconnect, different connection relationships between CLB modules, between I/O modules, and between CLB modules and I/O modules can be achieved.

The CLB module is a core logic module inside the FPGA chip, and generally comprises a flip-flop and a LUT module (Look-Up Table), and the digital logic circuit generally performs a series of functions through a sequential component (flip-flop) and a combinational logic (and gate, or gate, exclusive or gate, etc.). The combinational logic portion of the FPGA chip is typically based on LUT modules. The LUT module is essentially a RAM, and after writing data into the RAM in advance, each time a signal is input, it is equal to inputting an address to perform table lookup, find the content corresponding to the address, and then output.

The LUT module can be configured as a plurality of logic, and assuming that a 2-input and gate is to be implemented in the FPGA chip, the input-output correspondence of the and gate is:

input device	Output of
		0,0	0
0,1	0
		1,0	0
1,1	1

Since the corresponding logical relationship exists, only the corresponding output value is stored in the address corresponding to the SRAM, and the input value is used as the address to look up the table to obtain the correct output value. When the input address is 0, the value stored in the output 0 address is 0, when the input address is 0,1, the value stored in the output 1 address is 0, when the input address is 1,0, the value stored in the output 2 address is 0, and when the input address is 1, the value stored in the output 3 address is 1.

The logic function of the LUT module is changed by writing the bit stream file of the FPGA chip to change the value in the SRAM in the CLB module, the LUT module is constructed as different logic, such as inverse logic (NOT gate), namely the LUT module can be constructed as an inverter, and a certain delay exists, so that the ring oscillator can be built by the LUT module.

As shown in fig. 4, an odd number of LUT modules are connected to form a loop to form a ring oscillator, thereby satisfying the amplification and feedback conditions of the oscillator and generating a stable clock. Half the clock period is the delay of the whole loop. The clock period generated by the ring oscillator is measured, and the transmission delay inside each LUT module can be calculated according to the number n of stages.

The connection between CLB modules, i.e. between LUT modules, is achieved by programmable interconnect lines so that an odd number of LUT modules constitute a ring oscillator. The bit stream file written into the FPGA chip is used for changing the value in the SRAM in the programmable interconnection line, so that the selection end of the programmable interconnection line is changed, and the connection lines with different directions and lengths are freely selected.

The invention provides a method for testing signal transmission delay in an FPGA chip, which is characterized in that at least one CLB module and at least one I/O module are connected into a ring oscillator through a programmable interconnection line, the number of the CLB modules in the ring oscillator is an odd number, and LUT modules in the CLB modules are configured as NOT circuits.

As shown in fig. 5, if the signal transmission delay between adjacent modules in the FPGA chip needs to be tested, the bit stream file of the FPGA chip is written to change the value in the SRAM in the programmable interconnect line, so as to change the selection end of the programmable interconnect line, so that the programmable interconnect line is respectively connected with two adjacent CLB modules, an odd number of LUT modules form a ring oscillator, and the signal transmission delay of each CLB module is tested.

As shown in fig. 6, if the signal transmission delay between two adjacent modules in the FPGA chip needs to be tested, the bit stream file of the FPGA chip is written to change the value in the SRAM in the programmable interconnect line, so as to change the selection end of the programmable interconnect line, so that the programmable interconnect line is respectively connected with two CLB modules with a distance of 2, an odd number of LUT modules form a ring oscillator, and the signal transmission delay of each CLB module is tested.

As shown in fig. 7, if the signal transmission delay between four adjacent modules in the FPGA chip needs to be tested, the bit stream file of the FPGA chip is written to change the value in the SRAM in the programmable interconnect line, so as to change the selection end of the programmable interconnect line, so that the programmable interconnect line is respectively connected with two CLB modules with a distance of 4, an odd number of LUT modules form a ring oscillator, and the signal transmission delay of each CLB module is tested.

The invention can test the signal transmission delay between the CLB modules and the signal transmission delay between the I/O modules. As shown in fig. 8, a plurality of I/O modules and one CLB module may be combined together through a programmable interconnect to form a ring oscillator (at least one CLB module is required to implement the function of an inverter), and the signal propagation delay of the I/O module is tested. The transistors in the I/O module and the CLB module are two different transistors, and the invention can conveniently test the signal transmission delay of different types of transistors in the FPGA chip without increasing extra circuit area cost.

Due to some random factors during the fabrication of the chip, the same device may vary in speed at different locations of the chip. As shown in fig. 9, CLB modules at different positions in the FPGA chip may be combined together through programmable interconnect lines to form a ring oscillator, and signal transmission delay of the CLB modules may be tested. The invention can conveniently test the signal transmission delay of transistors at different positions in the chip without increasing extra circuit area cost.

While the present invention has been described in detail through the foregoing description of the preferred embodiment, it should be understood that the foregoing description is not to be considered as limiting the invention. Many modifications and substitutions of the present invention will become apparent to those of ordinary skill in the art upon reading the foregoing. Accordingly, the scope of the invention should be limited only by the attached claims.

Claims

1. A method for testing signal transmission delay in an FPGA chip, the method comprising: at least one CLB module and at least one I/O module are connected into a ring oscillator through a programmable interconnection line, the modules connected at two ends of the programmable interconnection line are changed by changing the value of SRAM in the programmable interconnection line, the number of the CLB modules in the ring oscillator is an odd number, and the LUT modules in the CLB modules are configured as NOT circuits.

2. The method of testing signal propagation delay in an FPGA chip of claim 1, wherein the logic function of the LUT module is changed by changing the value of the SRAM in the CLB module.

3. A method of testing signal propagation delay in FPGA chips as claimed in claim 1 or 2 wherein the FPGA chip alters the value of the SRAM in the CLB module and the SRAM in the programmable interconnect line by downloading an external bitstream file.