CN110674608B - Modeling method and system for NAND flash memory storage unit - Google Patents
Modeling method and system for NAND flash memory storage unit Download PDFInfo
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Abstract
The invention provides a modeling method and a system for a NAND flash memory storage unit, wherein the modeling method comprises the following steps: performing behavior level modeling on the NAND flash memory storage unit to generate a storage unit behavior level model; and replacing the transistor simulation model with the memory cell behavior level model. According to the invention, the transistor simulation model is replaced by the memory cell behavior level model, so that the design simulation time is obviously reduced.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to a modeling method and system for a NAND flash memory storage unit.
Background
The NAND flash memory is one of flash memories, and belongs to a nonvolatile memory device. The internal structure adopts a nonlinear macro-unit mode, has the advantages of low power consumption, large capacity, high reading and writing speed and the like, and is suitable for storing a large amount of data. The method is widely applied to various electronic digital products, such as solid state disks, U disks, digital cameras, MP3 and the like.
The operation of the NAND flash memory includes three parts, a read operation, a program operation and an erase operation, wherein the program operation and the erase operation update the threshold voltage (Vth) of the memory Cell, and since the number of the memory cells is huge, wherein 1Gbit S L C (Single-L ev Cell) devices have more than 1 hundred million memory transistors, a large amount of computer resources and time are consumed in design simulation, and project progress is seriously affected.
Therefore, a modeling method and system for a NAND flash memory cell are urgently needed to improve the speed of design simulation.
Disclosure of Invention
The invention provides a modeling method of a NAND flash memory storage unit, aiming at the technical problems that a great amount of computer resources and time are consumed and project progress is seriously influenced when design simulation is carried out due to excessive transistors in the prior art, and the modeling method comprises the following steps:
step S1: performing behavior level modeling on the NAND flash memory storage unit to generate a storage unit behavior level model;
step S2: and replacing the transistor simulation model with the memory cell behavior level model.
In the modeling method of the present invention, the NAND flash memory cell includes a programmable threshold voltage trigger switch, a first current limiting resistor and a second current limiting resistor;
the NAND flash memory storage unit comprises a grid end used for simulating a grid electrode of a transistor, a substrate end used for simulating a substrate of the transistor, a drain end used for simulating a drain electrode of the transistor and a source end used for simulating a source electrode of the transistor;
one end of the programmable threshold voltage trigger type switch is connected with the drain terminal through a first current limiting resistor, and the other end of the programmable threshold voltage trigger type switch is connected with the source terminal through a second current limiting resistor; the memory cell behavior level model includes:
and when the voltage between the grid end and the source end and the voltage of the drain end reach preset conditions, adjusting the threshold voltage of the programmable threshold voltage trigger type switch by adopting a preset adjusting mode to generate a memory cell behavior level model.
In the modeling method of the present invention, the NAND flash memory cell has a read operation function, a program operation function, and an erase operation function,
the memory cell behavior level model includes:
under the condition that the NAND flash memory storage unit is subjected to programming operation, when the voltage of a drain terminal is detected to be less than or equal to 0.1V, and the voltage between a grid terminal and a source terminal is detected to be greater than or equal to 13V, updating the threshold voltage of the programmable threshold voltage trigger type switch;
under the condition that the NAND flash memory storage unit carries out erasing operation, when the voltage of a drain terminal is detected to be 0V or floating, and the voltage between a grid terminal and a source terminal is less than or equal to-13V, updating the threshold voltage of the programmable threshold voltage trigger type switch;
when the voltage of the drain terminal is less than or equal to 2V and the voltage between the gate terminal and the source terminal is 0V under the condition that the NAND flash memory storage unit carries out read operation,
if the voltage between the grid end and the source end is greater than or equal to the threshold voltage of the programmable threshold voltage trigger switch, the programmable threshold voltage trigger switch is conducted;
and if the voltage between the grid end and the source end is less than the threshold voltage of the programmable threshold voltage trigger type switch, the programmable threshold voltage trigger type switch is closed.
The invention also provides a modeling system of the NAND flash memory storage unit, which comprises the following steps:
the behavior level modeling module is used for performing behavior level modeling on the NAND flash memory storage unit to generate a storage unit behavior level model;
and the replacing module is used for replacing the transistor simulation model with the memory cell behavior level model.
In the modeling system of the present invention, the NAND flash memory cell behavior level model includes: a programmable threshold voltage triggered switch, a first current limiting resistor, and a second current limiting resistor;
the NAND flash memory storage unit comprises a grid end used for simulating a grid electrode of a transistor, a substrate end used for simulating a substrate of the transistor, a drain end used for simulating a drain electrode of the transistor and a source end used for simulating a source electrode of the transistor;
one end of the programmable threshold voltage trigger type switch is connected with the drain terminal through a first current limiting resistor, and the other end of the programmable threshold voltage trigger type switch is connected with the source terminal through a second current limiting resistor;
the storage behavior level modeling module further comprises:
and when the voltage between the grid end and the source end and the voltage of the drain end reach preset conditions, adjusting the threshold voltage of the programmable threshold voltage trigger type switch by adopting a preset adjusting mode.
In the modeling system of the present invention, the NAND flash memory cell has a read operation function, a program operation function, and an erase operation function;
the memory cell behavior level model includes:
under the condition that the NAND flash memory storage unit is subjected to programming operation, when the voltage of a drain terminal is detected to be less than or equal to 0.1V, and the voltage between a grid terminal and a source terminal is detected to be greater than or equal to 13V, updating the threshold voltage of the programmable threshold voltage trigger type switch;
under the condition that the NAND flash memory storage unit carries out erasing operation, when the voltage of a drain terminal is detected to be 0V or floating, and the voltage between a grid terminal and a source terminal is less than or equal to-13V, updating the threshold voltage of the programmable threshold voltage trigger type switch;
when the voltage of the drain terminal is less than or equal to 2V and the voltage between the gate terminal and the source terminal is 0V under the condition that the NAND flash memory storage unit carries out read operation,
if the voltage between the grid end and the source end is greater than or equal to the threshold voltage of the programmable threshold voltage trigger switch, the programmable threshold voltage trigger switch is conducted;
and if the voltage between the grid end and the source end is less than the threshold voltage of the programmable threshold voltage trigger type switch, the programmable threshold voltage trigger type switch is closed.
The technical scheme provided by the embodiment of the invention has the following beneficial effects: the invention provides a modeling method and a modeling system for a NAND flash memory storage unit, aiming at the technical problems that a large amount of computer resources and time are consumed and project progress is seriously influenced when design simulation is carried out due to the fact that a large number of transistors are used in the prior art. According to the invention, the memory cell behavior level model is modeled by using the Verilog-A language, the memory cell behavior level model is generated and replaces the transistor simulation in the circuit with the memory cell behavior level model, and the technical effect of remarkably improving the design simulation speed is realized.
Drawings
FIG. 1 is a flow chart of a method of modeling a NAND flash memory cell in accordance with a preferred embodiment of the present invention;
FIG. 2 is a schematic diagram of a memory cell behavioral level model of the modeling method shown in FIG. 1;
FIG. 3 is an internal circuit diagram of a memory cell behavioral level model of the modeling method shown in FIG. 2;
FIG. 4 is a graph of voltage changes at each port of a behavioral level model of a NAND flash memory cell in the case of a programming operation of the cell;
FIG. 5 is a graph of voltage changes at each port of a behavioral level model of a NAND flash memory cell in the case of an erase operation of the cell;
FIG. 6 is a functional block diagram of a modeling system for NAND flash memory cells in accordance with a preferred embodiment of the present invention.
Detailed Description
In order to solve the technical problems that in the prior art, a large amount of computer resources and time are consumed and project progress is seriously influenced when simulation is designed due to the fact that a large number of transistors are used in the prior art, the invention provides a modeling method and a modeling system of a NAND flash memory storage unit, and the core idea is as follows: the technical effect of remarkably improving the simulation speed of the design is achieved by performing behavior-level modeling on the storage unit by using the Verilog-A language, generating a behavior-level model of the storage unit and replacing the behavior-level model of the storage unit with a transistor simulation model.
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Referring to fig. 1, a preferred embodiment of the present invention provides a method for modeling a NAND flash memory cell, including:
step S1: performing behavior level modeling on the NAND flash memory storage unit to generate a storage unit behavior level model;
step S2: and replacing the transistor simulation model with the memory cell behavior level model.
Further, with reference to fig. 2, the NAND flash memory cell includes a gate terminal G for the gate of the analog transistor, a substrate terminal B for the substrate of the analog transistor, a drain terminal D for the drain of the analog transistor, and a source terminal S for the source of the analog transistor; by setting the function of the port of the NAND flash memory storage unit, the NAND flash memory storage unit can completely replace a transistor to realize the same function as the transistor, but the speed of the NAND flash memory storage unit is obviously improved compared with that of the transistor in the design simulation;
further, in conjunction with fig. 3, it can be seen that: the NAND flash memory cell includes a programmable threshold voltage trigger-type switch S1, a first current limiting resistor R1, and a second current limiting resistor R2; one end of the programmable threshold voltage trigger type switch S1 is connected with the drain terminal D through a first current limiting resistor R1, and the other end of the programmable threshold voltage trigger type switch S1 is connected with the source terminal S through a second current limiting resistor R2; it should be noted that: the resistance values of the first and second current limiting resistors R1 and R2 may be selected according to process parameters. The threshold voltage of the programmable threshold voltage triggered switch S1 is equivalent to the threshold voltage of the transistor.
Further, the memory cell behavior level model includes:
and when the voltage between the grid end G and the source end S and the voltage of the drain end D reach preset conditions, adjusting the threshold voltage of the programmable threshold voltage trigger type switch S1 by adopting a preset adjusting mode.
It should be noted that the NAND flash memory cell has a read operation function, a program operation function, and an erase operation function;
with reference to fig. 4, in the case of a programming operation of the NAND flash memory cell, when it is detected that the voltage at the drain terminal D is less than or equal to 0.1V and the voltage between the gate terminal G and the source terminal S is greater than or equal to 13V, the threshold voltage of the programmable threshold voltage trigger switch S1 is linearly increased from 2V to 5V;
with reference to fig. 5, in the case of performing an erase operation on the NAND flash memory cell, when it is detected that the voltage at the drain terminal D is 0V or floating, and the voltage between the gate terminal G and the source terminal S is less than or equal to-13V, the threshold voltage of the programmable threshold voltage trigger switch S1 is linearly decreased from-2V to-5V;
under the condition that the NAND flash memory storage unit carries out reading operation, when the voltage of a drain terminal D is smaller than or equal to 2V, the voltage between a grid terminal G and a source terminal S is 0V, and if the voltage between the grid terminal G and the source terminal S is larger than or equal to the threshold voltage of a programmable threshold voltage trigger type switch S1, a programmable threshold voltage trigger type switch S1 is conducted; if the voltage between the gate terminal G and the source terminal S is less than the threshold voltage of the programmable threshold voltage trigger switch S1, the programmable threshold voltage trigger switch S1 is turned off.
The preferred embodiment of the present invention provides a modeling system for NAND flash memory cells, which is combined with fig. 6, and the modeling system includes:
the behavior level modeling module 100 is used for performing behavior level modeling on the NAND flash memory storage unit to generate a storage unit behavior level model;
a replacement module 200 for replacing the transistor simulation model with the memory cell behavioral level model.
Wherein the NAND flash memory cell includes a programmable threshold voltage triggered switch S1, a first current limiting resistor R1, and a second current limiting resistor R2;
the NAND flash memory storage unit comprises a gate end G used for simulating a gate of a transistor, a substrate end B used for simulating a substrate of the transistor, a drain end D used for simulating a drain of the transistor and a source end S used for simulating a source of the transistor;
one end of the programmable threshold voltage trigger type switch S1 is connected with the drain terminal D through a first current limiting resistor R1, and the other end of the programmable threshold voltage trigger type switch S1 is connected with the source terminal S through a second current limiting resistor R2;
further, the memory cell behavior level model includes:
and when the voltage between the grid end G and the source end S and the voltage of the drain end D reach preset conditions, adjusting the threshold voltage of the programmable threshold voltage trigger type switch S1 by adopting a preset adjusting mode.
Further, the NAND flash memory cell has a read operation function, a program operation function, and an erase operation function;
specifically, the memory cell behavior level model includes:
under the condition that the NAND flash memory storage unit carries out programming operation, when the voltage of a drain terminal D is detected to be less than or equal to 0.1V, and the voltage between a gate terminal G and a source terminal S is detected to be greater than or equal to 13V, the threshold voltage of a programmable threshold voltage trigger type switch S1 is linearly increased to 5V from 2V;
when the NAND flash memory storage unit carries out erasing operation, when the voltage of a drain terminal D is detected to be 0V or float, and the voltage between a gate terminal G and a source terminal S is less than or equal to-13V, the threshold voltage of the programmable threshold voltage trigger type switch S1 is linearly reduced to-5V from-2V;
under the condition that the NAND flash memory storage unit carries out reading operation, when the voltage of a drain terminal D is smaller than or equal to 2V, the voltage between a grid terminal G and a source terminal S is 0V, and if the voltage between the grid terminal G and the source terminal S is larger than or equal to the threshold voltage of a programmable threshold voltage trigger type switch S1, a programmable threshold voltage trigger type switch S1 is conducted; if the voltage between the gate terminal G and the source terminal S is less than the threshold voltage of the programmable threshold voltage trigger switch S1, the programmable threshold voltage trigger switch S1 is turned off.
In summary, the key points of the present invention mainly include the following: the method comprises the steps of utilizing a Verilog-A language to conduct behavioral modeling on a NAND flash memory storage unit, generating a storage unit behavioral model, and replacing a transistor simulation model with the storage unit behavioral model, so that the technical effect of remarkably improving the design simulation speed is achieved.
Those skilled in the art will appreciate that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing associated hardware, and the program may be stored in a computer readable storage medium.
In summary, the invention provides a modeling method and a system for a NAND flash memory unit, which achieve the technical effect of significantly improving the design simulation speed by modeling the memory unit behavior level by using Verilog-a language, generating a memory unit behavior level model and replacing the memory unit behavior level model with a transistor simulation model.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (4)
1. A modeling method for a NAND flash memory cell, comprising:
step S1: performing behavior level modeling on the NAND flash memory storage unit to generate a storage unit behavior level model;
step S2: replacing a transistor simulation model with a memory cell behavior level model;
wherein the NAND flash memory cell comprises a programmable threshold voltage triggered switch (S1), a first current limiting resistor (R1), and a second current limiting resistor (R2);
the NAND flash memory cell comprises a gate terminal (G) for a gate of the analog transistor, a substrate terminal (B) for a substrate of the analog transistor, a drain terminal (D) for a drain of the analog transistor, and a source terminal (S) for a source of the analog transistor;
one end of the programmable threshold voltage trigger type switch (S1) is connected with the drain terminal (D) through a first current limiting resistor (R1), and the other end of the programmable threshold voltage trigger type switch (S1) is connected with the source terminal (S) through a second current limiting resistor (R2);
the memory cell behavior level model includes:
and when the voltage between the grid end (G) and the source end (S) and the voltage of the drain end (D) reach preset conditions, adjusting the threshold voltage of the programmable threshold voltage trigger type switch (S1) by adopting a preset adjusting mode.
2. The modeling method of claim 1, wherein the NAND flash memory cells have a read operation function, a program operation function, and an erase operation function;
the memory cell behavior level model includes:
under the condition that the NAND flash memory storage unit carries out programming operation, when the voltage of a drain terminal (D) is detected to be less than or equal to 0.1V, and the voltage between a gate terminal (G) and a source terminal (S) is detected to be more than or equal to 13V, updating the threshold voltage of a programmable threshold voltage trigger type switch (S1);
under the condition that the NAND flash memory storage unit carries out an erasing operation, when the voltage of a drain terminal (D) is detected to be 0V or float, and the voltage between a gate terminal (G) and a source terminal (S) is less than or equal to-13V, updating the threshold voltage of a programmable threshold voltage trigger type switch (S1);
when the voltage of the drain terminal (D) is less than or equal to 2V and the voltage between the gate terminal (G) and the source terminal (S) is 0V under the condition that the NAND flash memory storage unit carries out read operation,
if the voltage between the grid terminal (G) and the source terminal (S) is larger than or equal to the threshold voltage of the programmable threshold voltage trigger type switch (S1), the programmable threshold voltage trigger type switch (S1) is conducted;
the programmable threshold voltage trigger switch (S1) is turned off if the voltage between the gate terminal (G) and the source terminal (S) is less than the threshold voltage of the programmable threshold voltage trigger switch (S1).
3. A modeling system for a NAND flash memory cell, comprising:
the behavior level modeling module (100) is used for performing behavior level modeling on the NAND flash memory storage unit to generate a storage unit behavior level model;
a replacement module (200) for replacing the transistor simulation model with the memory cell behavioral level model;
wherein the NAND flash memory cell comprises a programmable threshold voltage triggered switch (S1), a first current limiting resistor (R1), and a second current limiting resistor (R2);
the NAND flash memory cell comprises a gate terminal (G) for a gate of the analog transistor, a substrate terminal (B) for a substrate of the analog transistor, a drain terminal (D) for a drain of the analog transistor, and a source terminal (S) for a source of the analog transistor;
one end of the programmable threshold voltage trigger type switch (S1) is connected with the drain terminal (D) through a first current limiting resistor (R1), and the other end of the programmable threshold voltage trigger type switch (S1) is connected with the source terminal (S) through a second current limiting resistor (R2);
the memory cell behavior level model includes:
and when the voltage between the grid end (G) and the source end (S) and the voltage of the drain end (D) reach preset conditions, adjusting the threshold voltage of the programmable threshold voltage trigger type switch (S1) by adopting a preset adjusting mode.
4. The modeling system of claim 3, wherein the NAND flash memory storage unit has a read operation function, a program operation function, and an erase operation function;
the memory cell behavior level model includes:
under the condition that the NAND flash memory storage unit carries out programming operation, when the voltage of a drain terminal (D) is detected to be less than or equal to 0.1V, and the voltage between a gate terminal (G) and a source terminal (S) is detected to be more than or equal to 13V, updating the threshold voltage of a programmable threshold voltage trigger type switch (S1);
under the condition that the NAND flash memory storage unit carries out an erasing operation, when the voltage of a drain terminal (D) is detected to be 0V or float, and the voltage between a gate terminal (G) and a source terminal (S) is less than or equal to-13V, updating the threshold voltage of a programmable threshold voltage trigger type switch (S1);
when the voltage of the drain terminal (D) is less than or equal to 2V and the voltage between the gate terminal (G) and the source terminal (S) is 0V under the condition that the NAND flash memory storage unit carries out read operation,
if the voltage between the grid terminal (G) and the source terminal (S) is larger than or equal to the threshold voltage of the programmable threshold voltage trigger type switch (S1), the programmable threshold voltage trigger type switch (S1) is conducted;
the programmable threshold voltage trigger switch (S1) is turned off if the voltage between the gate terminal (G) and the source terminal (S) is less than the threshold voltage of the programmable threshold voltage trigger switch (S1).
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| US9639649B2 (en) * | 2015-08-18 | 2017-05-02 | Kabushiki Kaisha Toshiba | Semiconductor memory device, method for designing semiconductor memory device, and recording medium having designing method recorded therein |
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| CN206312139U (en) * | 2016-11-07 | 2017-07-07 | 上海飞斯信息科技有限公司 | A kind of NandFLASH cablings topological structure |
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