TWI650756B - Erasing method used in flash memory - Google Patents

Abstract

A method of erasing a flash memory is exemplified as follows, wherein the flash memory includes at least one memory block, and the memory block is divided into a plurality of memory segments. Determining, according to the segment enable signal, whether the memory block or the memory segment corresponding to the one address has at least one erased memory cell, wherein the segment enable signal is based on whether the memory block has at least one over-erase The transistor memory cell is determined. If the memory block or the memory segment corresponding to the address has an insufficient memory cell, the memory cell of the memory block or the memory segment is erased according to the segment enable signal.

Description

Wiping method for flash memory

This invention relates to a flash memory, and more particularly to an erase method for flash memory.

The flash memory includes a plurality of individual metal oxide semiconductor (MOS) field effect transistor memory cells, each transistor memory cell including a source, a drain, a floating gate, and a control gate. The plurality of electrodes of the transistor memory unit can be applied with various voltages to program (ie, write) the transistor memory cells into binary ones or zeros, and erase all of the transistor memory cells as memory blocks. Read the transistor memory unit, verify that the transistor memory unit is erased, or verify that the transistor memory unit has not been over erased.

The adverse effects of the leakage current of the over-erased transistor memory cell are described as follows. In a typical flash memory, a large number of transistors of a transistor memory cell, such as 512 transistor memory cells, are connected to each bit line. If a large number of transistor memory cells on the bit line are extracting background leakage current, the total leakage current on the bit line may exceed the cell read current. This prevents the state of any of the transistor memory cells on the bit line from being read and thus rendering the flash memory inoperable.

Please refer to FIG. 1. FIG. 1 is a flow chart of a conventional erasing method. The flash memory includes a memory module and a memory management device electrically connected to the memory module, wherein the memory module has a plurality of memory banks, each memory group includes a plurality of memory blocks, and the memory management device Used to perform an erase method on the memory block of the memory group.

In step S11, the memory management device performs an operation of verifying and pre-writing all of the transistor body units of the memory module. Next, in step S12, the memory management device verifies and erases all of the transistor memory cells as memory blocks, that is, the erased unit is a memory block. Finally, in order to avoid the flash memory of the over-erased transistor body unit, the flash memory cannot operate, and in step S13, the memory management device verifies all of the plurality of transistor body units of the memory module, and when the verification result When the at least one over-erased transistor body unit is present in the memory block, the over-erasing of the memory module is over-erased.

In detail, step S12 includes steps S121 to S124. In step S121, the memory management device verifies the transistor memory unit corresponding to the memory block of the address. Then, in step S122, if the verification result indicates that at least one of the transistor memory cells of the memory block is under-erased (ie, the verification result indicates that the erase verification of the memory block fails), the memory management device will Step S124 is performed; otherwise, the memory management device will perform step S123.

Then, since at least one of the transistor memory cells of the memory block is insufficiently erased, in step S124, the memory management device injects an erasing shot into the transistor memory unit of the memory block (ie, erases the memory block). The transistor memory cell) is used to change the threshold voltage of the transistor memory cell of the memory block (ie, the transistor memory cell of the memory block is erased). Then, step S121 will be executed again. Then, if it is determined in step S122 that the transistor memory cell of the memory block is erased, step S123 will be performed. In step S123, the memory management device checks whether the address is the largest address (ie, the memory cells of all the memory blocks are erased). If the address is not the largest address, step S125 will be performed; otherwise, step S13 will be executed. In step S125, the memory management device adds an increment to the address, and then step S121 is executed.

It is worth noting that when the bit line of the slow erased transistor memory cell has a large bit line leakage current, the erase threshold voltage will become higher after the bit line leakage current is restored in step S13. . At the same time, more over-erased transistor memory cells will suffer from long over-erase correction times.

Different from the above method of verifying and erasing all the transistor memory cells in the memory block, for each memory block, another conventional erasing method can erase only the memory cells in the memory segment. Insufficient transistor memory unit. Please refer to FIG. 2. FIG. 2 is a schematic diagram of another conventional erase method performed on a memory block. The memory block 2 is divided into several memory sections G1 to G15, and a plurality of flag registers are used for the memory sections G1 to G15, respectively, to record whether or not all of the transistor memory cells in the memory sections G1 to G15 are recorded. Was erased.

As shown in FIG. 2, all of the memory segments G1 to G15 initially have a plasma memory cell with insufficient erase, and thus inject the erase firing into the transistor memory cells of the memory segments G1 to G15 (ie, erase the memory region). Block 2 transistor memory unit). Then, it is verified that all the transistor memory cells 2 of the memory block 2, for example, the memory segment G3, have not erased the insufficient transistor memory cells, and the flag register corresponding to the memory segment G3 records the state as erased. status. Thereby, the erase firing is injected into the transistor memory cells of the memory segments G1, G2, G4 to G15 (i.e., the transistor memory cells that erase the memory segments G1, G2, G4 to G15).

Then, all the transistor memory cells of the memory block 2 are verified again, for example, the memory segments G1, G3, G4 to G15 are not erased by the insufficient transistor memory cells, and correspond to the memory segments G1, G3, G4 to G15. The flag register records its status as erased. Therefore, the eraser is injected into the transistor memory unit of the memory section G2 (i.e., the transistor memory unit of the erase memory section G2). This conventional erase method requires a plurality of additional flag registers and consumes more erase verification time.

It is an object of the present disclosure to provide an erase method for a flash memory that does not require an additional plurality of flag registers and does not require more erase verify time.

Another object of the present disclosure is to provide a flash memory to perform the above erase method.

In order to achieve at least the above objects, the present disclosure provides an erasing method for flash memory. The flash memory includes at least one memory block, and the memory block is divided into a plurality of memory segments. The erasing method is exemplified as follows. Determining, according to the segment enable signal, whether the memory block or the memory segment corresponding to the one address has at least one erased memory cell, wherein the segment enable signal is based on whether the memory block has at least one over-erase The transistor memory cell is determined. If the memory block or the memory segment corresponding to the address has an insufficient memory cell, the memory cell of the memory block or the memory segment is erased according to the segment enable signal.

In order to achieve at least the above objects, the present disclosure provides a flash memory including: a memory module and a memory management device. The memory module includes at least one memory block, and the memory block is divided into a plurality of memory segments. The memory management device is electrically connected to the memory module. The memory management device verifies, according to the segment enable signal, whether the memory block or the memory segment corresponding to the one address has at least one erased memory cell, wherein the segment enable signal is based on whether the memory block has at least one It is determined by over-wiping the transistor memory cell. If the memory block or the memory segment corresponding to the address has an insufficient memory cell, the memory management device erases the memory cell of the memory block or the memory segment according to the segment enable signal.

In an embodiment of the present disclosure, if the segment enable signal is asserted and the memory segment corresponding to the address has an erased memory cell, the memory segment The transistor memory cell will be implanted with an erasing shot at least once until the memory segment has no erase memory cells.

In an embodiment of the present disclosure, if the memory segment does not have a transistor memory cell with insufficient erase, the address will be incremented by an increment, and then if another memory segment corresponding to the address has at least Once the insufficient transistor memory cell is erased, the transistor memory cell of the other memory segment will be injected and erased at least once until the other memory segment does not have the erased memory cell.

In an embodiment of the present disclosure, when the address reaches the maximum address, it is verified whether the memory block has an over-erased transistor memory unit, and if there is excessive erasure of the transistor memory in the memory block Unit, the over-erasing correction of the over-erased transistor memory cell.

In one embodiment of the present disclosure, the transistor memory cells of the memory block are verified and pre-programmed prior to verifying and erasing the memory cell of the memory block.

In an embodiment of the disclosure, the segment enable signal is initially set to be de-asserted, and if the memory block corresponding to the address has an erased memory cell, the memory The transistor memory cell of the block will be injected with a wipe memory at least once until the memory block is verified to have an over-erased transistor memory cell.

In one embodiment of the present disclosure, when the memory block is verified to have an over-erased transistor memory cell, an over-erased correction shot is injected into the over-erased transistor memory. The unit, and the section enable signal is set to the active state.

In summary, the erasing method provided by the embodiment of the present invention does not require an additional plurality of flag registers to record the state of the memory segment, and does not require more erasure verification time.

S11~S13‧‧‧Steps

S121~S125‧‧‧Steps

G1~G15‧‧‧ memory section

S31~S33‧‧‧Steps

S321~S329‧‧‧Steps

[Fig. 1] is a flow chart of a conventional erasing method.

[Fig. 2] is a schematic diagram of another conventional erasing method performed on a memory block.

FIG. 3 is a flow chart of a method for erasing a flash memory according to an embodiment of the present disclosure.

In order to fully understand the objects, features and advantages of the present invention, the present invention will be described in detail by the accompanying drawings.

An embodiment of the present disclosure provides an erasing method for a flash memory in which all of the transistor memory cells (ie, wipes) are injected into the memory block during the verifying and erasing steps. After all of the transistor memory cells of the memory block, the erase method provided verifies whether the memory block has at least one over-erased transistor body unit. When the memory block has at least one over-erased transistor body unit, the erase method is provided to inject the erased shot into the plurality of transistor memory cells of the memory segment (ie, erase all of the memory segments) The transistor memory unit) then provides an erase method to verify that all of the transistor memory cells of the memory segment are erased. The erase method provided erases the plurality of transistor memory cells of the memory segment at least once until all of the transistor memory cells of the memory segment are erased. Next, the erase method is provided to erase a plurality of transistor memory cells of another memory segment in the same memory block at least once until a plurality of transistor memory cells of the other memory segment are erased. When all of the transistor memory cells of the other memory segment in the memory block are erased, a similar erase scheme will be performed for the other memory block. Therefore, the erase method provided does not require an additional plurality of flag registers to record the state of the memory segment and does not require more erase verify time.

Please refer to FIG. 3. FIG. 3 is a flowchart of a method for erasing a flash memory according to an embodiment of the present disclosure. The flash memory (not shown) includes a memory module and a memory management device electrically connected to the memory module. The memory module includes a plurality of memory groups, each memory group includes a plurality of memory blocks, and each memory block is divided into a plurality of memory segments. For example, the memory block has 64K bytes (ie, 64*8K bits), and the memory segment has 4K bytes (ie, 4*8K bits). However, the disclosure is not limited by the examples described above.

In step S31, the memory management device performs an operation of verifying and pre-writing a plurality of transistor body units of the memory module. Then, in step S32 (ie, the erasing and verifying step), the memory management device verifies and erases the plurality of transistor body units of the memory module. It should be noted that, in step S32, the erase method provided may be based on whether an over-erased correction shot is injected into the transistor memory unit of the memory block (ie, whether the memory block has The at least one erased transistor cell unit is erased to erase the isoelectric memory cell of the memory block or the memory segment. Finally, in order to avoid the excessively erased leakage current of the transistor body unit, the flash memory cannot be operated. In step S33, the memory management device verifies all the transistor body units of the memory module and the excessive wipe of the memory module. In addition to the transistor memory unit, the correction is performed by over-erasing.

In detail, step S32 includes steps S321 to S329. In step S321, the memory management device verifies whether the transistor memory unit corresponding to the memory block or the memory segment of the address is erased to generate a verification result. When the segment enable signal SEC_EN corresponding to the memory block is set to the active state, the transistor memory unit of the memory segment is verified; and when the segment enable signal SEC_EN corresponding to the memory block is set In the inactive state, the memory cell of the memory block is verified, wherein the segment enable signal SEC_EN corresponding to the memory block is determined according to whether the memory block has at least one over-erased transistor memory unit. . If the memory block or the memory segment has at least one erase The memory management unit of the foot, the memory management device will determine that the verification result is a failure; and if the memory block or the memory segment does not have at least one erased memory cell, the memory management device determines that the verification result is a pass.

In step S322, the memory management device checks if the verification result is a failure or a pass. If the verification result is a failure, step S323 will be executed; otherwise, step S328 will be executed. In step S323, the memory management device injects the erased shot into the plurality of transistor memory units of the memory block or the memory segment according to the segment enable signal SEC_EN corresponding to the memory block. If the segment enable signal SEC_EN corresponding to the memory block is set to the active state, the memory management device injects the erase firing into the plurality of transistor memory units of the memory block; otherwise, the memory management device erases the firing A plurality of transistor memory cells injected into the memory segment.

In step S324, the memory management device checks whether the segment enable signal SEC_EN corresponding to the memory block is set to the active state. If the section enable signal SEC_EN corresponding to the memory block is set to the active state, step S321 will be performed; otherwise, step S325 will be executed. In step S325, the memory management device verifies whether the memory block has at least one over-erased transistor body unit, and when the memory block has at least one over-erased transistor body unit, the memory block is The crystal memory unit is corrected for over-erasing.

Next, in step S326, the memory management device checks whether the over-erase correction is performed (ie, whether the memory block has at least one over-erased transistor body unit, or checks for over-erasing correction (over-erased). Correction, OEC) fires an over-erased transistor cell unit that is injected into the memory block. If the over-erase correction is performed, step S327 will be performed; otherwise, step S321 will be performed. In step S327, the memory management device sets the segment enable signal SEC_EN corresponding to the memory block to an active state. In step S328, the memory management device checks whether the address is Reach the maximum address. In step S329, the memory management device adds an increment to the address, wherein the increment corresponds to the size of the memory segment.

Initially, when the erase method provided first erases a plurality of transistor memory cells of the memory block, the segment enable signal SEC_EN corresponding to the memory block is set to an inactive state. For example, in step S321, a plurality of transistor memory cells of the memory block are first verified; the memory block has a transistor memory cell with insufficient erase, so in step S323, the erased plurality of cells injected into the memory block are erased. Crystal memory unit. Then, since the segment enable signal SEC_EN corresponding to the memory block is set to the inactive state, in step S325, it is checked whether the memory block has at least one over-erased transistor body unit. Generally, after the provided erase method erases the isoelectric memory unit of the memory block one or more times, the memory block unit is over-erased in the memory block, and therefore, in step S327, The section enable signal SEC_EN corresponding to this memory block is set to the active state.

Next, in step S321, the transistor memory unit corresponding to the memory segment of the address is verified, and in step S323, the erase firing is injected into the transistor memory unit of the memory segment corresponding to the address, and Until the transistor memory cells of the memory segment are erased, steps S321 and S323 are repeatedly performed. If all the transistor memory cells of the memory segment corresponding to the address are erased, the address will be incremented by an increment in step S329, and the address corresponding to the address in the same memory block The transistor memory unit of a memory segment is verified in step S321 and the erase firing is injected into the transistor memory unit of another memory segment corresponding to the address in the same memory block in step S323. And until a plurality of transistor memory cells of the other memory segment are erased, steps S321 and S323 are repeatedly performed. Therefore, after the transistor memory cells of all the memory segments in the memory block are erased, the erase method provided will perform a similar erase scheme for the next memory block.

In summary, in the verification and erasing steps, the erasing method for flash memory according to an embodiment of the present disclosure is based on whether the memory block has at least one over-erased transistor record. The body unit erases the memory cell of the memory segment or the memory block, whereby the erase method does not require an additional plurality of flag registers to record the state of the memory segment. In addition, the eraser injection method is used to erase and verify the entire memory block compared to the conventional method of FIG. 2 (for example, the verified unit is 8 or more bits), and the erase method in the present disclosure is The erase shot is injected to perform OEC verification on the bit line of the entire memory block (for example, the verified unit is 8 or more bits), so that the erase method of the present disclosure can save more time. Furthermore, the slower and faster erased transistor memory cells in the memory segment are less likely to be connected to the same bit line, and the erase method of the present disclosure achieves a small erase threshold voltage distribution, such as Obtained by the conventional method of FIG. 2, the problem that the over-erased transistor memory unit can be masked to erase the insufficient transistor memory cell can be avoided, and the over-erased transistor memory unit does not suffer from prolonged over-wiping. In addition to the over-erased correction time and the post-over-erased correction time.

The invention has been described above in terms of the preferred embodiments, and it should be understood by those skilled in the art that the present invention is not intended to limit the scope of the invention. It should be noted that variations and permutations equivalent to those of the embodiments are intended to be included within the scope of the present invention. Therefore, the scope of protection of the present invention is defined by the scope of the patent application.

Claims (7)

An erasing method for a flash memory, the flash memory comprising at least one memory block, the memory block being divided into a plurality of memory segments, the erasing method comprising: enabling according to a segment The signal verification corresponds to whether the memory block of the address of the address or the memory segment has at least one erased memory cell, wherein the segment enable signal is based on whether the memory block has at least one over-erasing The transistor memory unit is determined; and if the memory block or the memory segment corresponding to the address has the under-dissolved transistor memory unit, the memory block is erased according to the segment enable signal or a plurality of transistor memory cells of the memory segment; wherein the segment enable signal is initially set to be de-asserted, and if the memory block corresponding to the address has the erase The transistor memory unit, the transistor memory cells of the memory block will be injected with a eraser at least once until the memory block is verified to have the transistor memory unit with the over-erase. The erasing method of claim 1, wherein if the segment enable signal is asserted and the memory segment corresponding to the address has the erased memory cell, The transistor memory cells of the memory segment will be injected with an erasing shot at least once until the memory segment does not have the erased memory cell. The erasing method of claim 2, wherein if the memory segment does not have the erase memory cell, the address is added with an increment, and then if the address corresponds to the address a memory segment having at least one erased memory cell, the plurality of transistor memory cells of the other memory segment being injected into the eraser at least once until the other memory segment does not have the erased defect The transistor memory unit. The erasing method of claim 3, further comprising: when the address reaches a maximum address, verifying whether the memory block has the over-erased transistor memory unit, and if the memory block is in the memory block The transistor memory cell having the over-erase is corrected for over-erasing the over-erased transistor memory cell. The erasing method of claim 1, further comprising: verifying and pre-writing the transistor memory cells of the memory block before verifying and erasing the transistor memory cells of the memory block. Pre-programing. The erasing method of claim 1, wherein an over-erased correction shot is injected into the memory block when the memory block is verified to have the over-erased transistor memory unit. The transistor memory cell is over-erased, and the segment enable signal is set to an active state. A flash memory device, comprising: a memory management device electrically connected to a memory module for performing the erasing method according to any one of claims 1 to 6; The memory module includes the memory block.