TWI442403B - Erase process for use in semiconductor memory device - Google Patents

Description

Erasing program used in semiconductor memory devices

The present invention relates to electronic memory devices, and more particularly to semiconductor memory devices suitable for use as memory devices.

Semiconductor memory devices have been widely used and can be found in almost all electronic devices used today. Most semiconductor memory devices can be distinguished as volatile or non-volatile. A volatile memory device requires power to store the stored data, while a non-volatile memory device can store the stored data without power.

Flash memory is a well-known non-volatile memory. A typical flash memory includes a memory array in which the memory cells are arranged in rows and columns. Each memory cell includes a floating gate field effect transistor. The logic state of a memory cell is determined by the threshold voltage of the transistor, which is determined by the number of electrons in the floating gate of the transistor. The electrons in the floating gate partially cancel the electric field generated by the control gate, thus adjusting the threshold voltage of the transistor. Therefore, the logic state of a flash memory can be controlled by controlling the number of electrons in the floating gate of the transistor.

A flash memory cell can be programmed and erased to write its respective logic state to this memory cell. This stylization and erase operation corresponds to the respective logic being written, which corresponds to the respective threshold voltages. For the sake of simplicity, the threshold voltage will only be referred to as the high and low threshold voltages, which is understood to be that the high threshold voltage is relatively higher than the low threshold voltage by several detectable voltage boundaries. The number of electrons stored in the floating gate of the transistor can be changed by applying a strong electric field between the control gate and at least one of the source, the drain and the substrate of the transistor to remove or stack electrons. In this floating gate. An "erase" operation is an operation in which electrons are removed from the floating gate, thereby lowering the threshold voltage of the memory cell to a lower threshold voltage, and a "stylized" operation is to deposit electrons in the floating gate. The operation thus increases the critical voltage of this memory cell to a high threshold voltage. Because the memory cells that are programmed and erased can be easily identified by their different threshold voltages, the stylized and erased memory cells can be used to represent different logic states. For example, the erased memory cell can be used to represent the logic state "1", and the stylized memory cell can be used to represent the logic state "0."

Figure 1 shows a flow chart of a conventional erase operation used in a flash memory device. In flash memory devices, memory cells called blocks are usually erased together in groups. A block represents a certain number of memory cells that can be erased simultaneously during an erase operation. A conventional erase operation that erases a memory cell in a block typically includes a pre-programming loop 110, an erase loop 120, and a soft stylization loop 130.

During the pre-programming loop 110, the floating gates of all of the memory cells in the selected block are programmed to have approximately equal numbers of electrons such that all of the memory cells in the selected block have approximately the same threshold voltage. The pre-programmed loop 110 includes a pre-programming program 112 and a pre-programmed verification program 114. A pre-programmed pulse is applied to the pre-programming program 112 to all of the memory cells in the selected block. In this pre-programmed verification program 114, all of the memory cells in this block segment are examined to verify that their respective threshold voltages are substantially the same after the application of the pre-programmed pulses. The pre-programming process 112 can be re-executed if there are not enough cells to have the expected threshold voltage. Otherwise, this operation continues to erase cycle 120.

During the erase cycle 120, all of the memory cells in the selected block are removed from the floating gates of all of the memory cells in the block by applying an erase pulse to the control gates of all of the memory cells in the block. . This erase cycle 120 includes a erase program 122 and an erase verification program 124. In this erase program 122, an erase pulse is applied to all of the memory cells in the selected block. In this erase verification program 124, all memory cells in this block segment are checked to verify that they have been erased. If enough memory cells are erased, then this block is considered to be successfully erased. If the block is not erased by the verification program 124, then all of the memory cells in the block can be re-applied by re-applying another erase pulse. In some systems, a voltage stepping procedure can be used in which the voltage is incremented after each erase cycle 120. In other systems, a time stepping procedure can be used in which the pulse width is incremented after each erase cycle 120.

Because in practical applications, the threshold voltage of the memory cells in any given block segment often changes, so that the voltage of the erase pulse required for erasing between different memory cells can be varied. In the latter stage of the erase cycle 120, the application of a relatively large or long erase pulse can result in excessive erasure of certain memory cells. An over-erased memory cell can cause other memory cells coupled to the same row to be considered as erased memory cells, even though they may have been programmed. Therefore, over-erased memory cells typically need to be repaired using a soft stylized loop 130.

In the soft stylized loop 130, the over-erased memory cells in this block are detected and repaired. A soft stylization program 132 and a soft stylization verification program 134 are included in the soft stylization loop 130. In this soft programming program 132, all memory cells in this block are checked to determine if any memory cells are over-erased. If an over-erasing of the memory cell is detected, a soft stylized pulse is applied to repair it. This soft stylized pulse is different from a normal stylized pulse in which the word line and bit line voltages are lower than the word line and bit line voltages in the normal stylized pulses. Furthermore, unlike the stylized pulse execution, which is programmed to program a memory cell, the execution of the soft stylized pulse erases an over-erased memory cell. For example, a normal stylized pulse can use a 3.0 to 4.0V word line voltage and a 3.0 to 4.0V bit line voltage. A soft stylized pulse uses a word line voltage of approximately 2.5V and a bit line voltage of approximately 3.0V. In the soft stylized verification program 134, all of the memory cells in this block are examined to determine if there are any over-erased memory cells after the soft stylized pulse. Assuming that the number of over-erased memory cells in such a block is less than or equal to a predetermined number, such as zero, the block is considered to pass the soft stylization verification procedure 134. If the block does not pass the soft stylization verification program 134, the soft program program 132 is re-executed. This soft stylization loop 130 can be executed continuously until the block passes the soft stylization verification program 134.

In step 140, if another block needs to be erased, the pre-programming loop 110 of the traditional block erasing operation, an erase loop 120, and a soft stylization loop 130 are sequentially executed to erase the next block. . In this case, a conventional "soft stylization" operation is performed to correct over-erase memory cells in all erased blocks in the flash memory.

When performing traditional "soft stylization" operations, using a traditional soft stylization loop requires a significant amount of time to correct over-erased memory cells. There is therefore a need for a new block erase method that can be used in non-volatile memory to reduce the time and/or steps required to erase blocks in the non-volatile memory.

It is an object of the present invention to provide an erasing method for use in a memory. The memory includes a plurality of memory cells and is divided into a plurality of segments of the memory cells. The method includes performing an erase program on a memory cell of a memory unit, receiving a pause command when executing the erase program, and interrupting the erase program and performing a program operation on the memory unit in response to the pause command At least one memory cell.

Another object of the present invention is to provide a memory device. The device includes a memory array and a memory controller. The memory array includes a plurality of memory cells and is divided into a plurality of memory blocks, each memory block being divided into memory cells of a plurality of memory segments. The memory controller is configured to perform an erasing process on the memory cells of a memory unit of the memory array, suspending the erasing of the memory cells when performing the erasing process, to perform an interrupt operation, and After the command is paused and before the interrupt operation is performed, a stylization operation is performed on at least one memory cell of the memory unit.

2 is a block diagram showing a memory device 200 according to an embodiment of the present invention. The memory device 200 includes a memory array 202, a row decoder 204, a sense amplifier 206, a column decoder 208, and a memory controller. 209. This memory array 202 can include a plurality of memory blocks 210.

The memory device 200 can be configured such that the memory array 202 includes anti-gate (NOR) flash memory cells 214 arranged in the memory block 210, the memory blocks 210 being labeled as block 0 through block i, where i" can be any natural number desired according to the design specifications of a particular application. The address and control signals can be input from controller 209 via row decoder 204, sense amplifier 206, column decoder 208 to the address/signal lines of memory array 202 for read and write and other operations. The memory controller 209 can include address and control circuitry and can be configured to communicate with other devices external to the memory device 200, such as one or more processors. The memory controller 209 can also be configured to issue a pause command to the erase operation interrupt in the memory array 202 to allow another operation, such as a read or program operation, to be performed in the memory array 202.

As shown in FIG. 3, each memory block 210 includes inverse OR gate (NOR) flash memory cells 214 arranged in memory segment 212, which are labeled as block 0 through block j, wherein "j" can be any natural number desired according to the design specifications of a particular application. For example, the memory block 210 or the memory cell sharing the substrate can form a memory of 64 kB or 128 kB, which can be arranged into a memory segment 212 of 4 kB each.

Referring to FIG. 4, a detailed block diagram of a memory block 210 including a plurality of memory segments 212 including exemplary memory segments 212a and 212b is shown, in accordance with an embodiment of the present invention. Memory segments 212a and 212b each include a group of flash memory cells 214 arranged in a reverse OR gate (NOR) flash memory architecture. The memory block 210 also includes a plurality of bit lines BL0-BLm, a plurality of word lines WL0-WLn, and a plurality of source lines SL0-SLm, which allow the memory cells 214 and the memory block 200 to be outside the memory block 210. Other components, such as row decoder 204, sense amplifier 206, column decoder 208, and memory controller 209, communicate.

In this illustrative embodiment, first memory segment 212a includes word lines WL0-WLs, where "s" can be any natural number desired according to the design specifications of a particular application.

This memory block 210 may form part of a flash memory device 200 that supports a pause-restart function. For example, the memory controller 209 of the flash memory device 200 can be configured to issue a pause command while the erase operation is in progress to allow the erase operation to be interrupted for another operation. For example, the erase program can be interrupted such that data can be read from or otherwise programmed into other segments 212 of flash memory device 200 or memory cells 214 in block 210.

FIG. 5 shows a flow chart of the segment erase operation used in the flash memory device 200. In the flash memory device 200, the memory cells 214 are group erased in units of segments, such that the memory cells 214 in a given segment 212 are erased together in a group manner. For example, in order to erase a memory cell 214 in the memory segment 212a, all memory cells 214 in the memory segment 212a are erased according to the erase operation in FIG. 5, while the memory in other segments is erased. The cell, for example, the memory segment 212b will remain unchanged. Since only the memory cells 214 in the memory segment 212a are erased, this erase process requires less time than erasing all of the memory cells 214 in the entire memory block 210.

The sector erase operation includes a pre-programming program in block 302, an erase (ERS pulse) program in block 308, a soft programming program in block 312, and an erase/software verification. The program is in block 316. The section erase operation description shown in Fig. 5 is related to the memory section 212a shown in Fig. 4. However, the segment erase operation shown in FIG. 5 can similarly perform erase on other memory segments 212 of memory array 202.

In the pre-programming process of block 302, the floating gates of all of the memory cells 214 in the memory segment 212a are programmed to have approximately equal electrons such that all of the memory cells 214 in the memory segment 212a have approximately the same criticality. Voltage. In this pre-programmed program, a pre-programmed pulse is applied to all of the memory cells 214 in the memory segment 212a. In some embodiments, the pre-programming program can include a pre-programmed verification program in which all of the memory cells 214 in the memory segment 212a are checked to verify that their respective threshold voltages are after the application of the pre-programmed pulses. Roughly the same. In such an embodiment, if there are not enough memory cells 214 to have the desired threshold voltage, then the pre-programmed pulses can be reapplied.

In the erase process of block 308, all of the memory cells 214 in the memory segment 212a are erased by applying an erase pulse to the memory cells 214 in the memory segment 212a such that all of the memory in the electronic self-memory segment 212a The cell 214 is removed. In the erase process of block 308, an erase pulse can be applied to the memory cell 214 in the memory segment 212a such that the voltage at the source, drain and/or substrate of each memory cell is more The gate voltage of the memory cell is larger (positive), thus forcing electrons to move out of the floating gate of the transistor.

In some embodiments, a erase verification procedure can be included in the erase program of block 308, wherein all memory cells 214 in memory segment 212a are examined to verify that they are erased. In such an embodiment, the memory segment 212a is considered to be successfully erased if sufficient memory cells are erased. In such an embodiment, if the memory segment 212a does not pass the erase verification procedure, then all of the memory cells in the memory segment 212a may be re-applied with another erase pulse. In some such embodiments, a voltage stepping procedure can be used in which the voltage is incremented after each erase/erase verification procedure of block 308. In other such embodiments, a time stepping procedure can be used in which the pulse width is incremented after each erase/erase verification procedure of block 308.

In a practical application, the threshold voltage of the memory cell 214 can be varied within the memory segment 212a, such as between the different memory cells 214, for example, due to variations in the floating gate transistor generated by the process, the eraser The voltage of the desired erase pulse can vary. In the erase procedure of block 308, applying an erase pulse can result in excessive erasure of certain memory cells 214. An over-erased memory cell can cause other memory cells coupled to the same row to be considered as over-erased memory cells, even though they may have been programmed. Therefore, over-erased memory cells need to be repaired using a soft stylized loop that includes blocks 312 and 316.

In the soft programming of block 312, the over-erased memory cells in memory segment 212a are detected and repaired. In the soft stylization program of block 312, all of the memory cells 214 in the memory segment 212a are examined to determine if any of the memory cells 214 have been over erased. If an over-erased memory cell is detected, a soft stylized pulse is applied to the floating gate transistor that is over-erased.

This soft stylized pulse is different from a normal stylized pulse in which the word line and bit line voltages are lower than the word line and bit line voltages in the normal stylized pulses. Furthermore, unlike the stylized pulse execution, which is programmed to program a memory cell, the execution of the soft stylized pulse erases an over-erased memory cell. For example, in some embodiments, an erased memory cell can represent a logic state of "1" and a stylized memory cell can represent a logic state of "0." In such an embodiment, the soft stylized pulse can cause the write logic state to be "1", while the stylized pulse can cause the write logic state to be "0."

In the soft stylization verification procedure of block 316, all of the memory cells 214 in the memory segment 212a are examined to determine if there are any over-erased memory cells after the soft stylized pulse. If the number of over-erased memory cells of memory segment 212a is less than or equal to a predetermined number, such as zero, then memory segment 212a is considered to be a soft stylization verification procedure through block 316. If the memory section 212a does not pass the soft stylization verification procedure of block 316, then the soft programming of block 312 is re-executed. The soft stylization loop including the soft stylization program of block 312 and the soft stylization verification program of block 316 can be continuously executed until the memory section 212a passes the soft stylization verification procedure of block 316.

Because the memory device 200 supports a pause command to execute an interrupt routine, such as a read or program program, the erase program can be interrupted by a pause command before it is completed, as represented by blocks 304, 310, 314. General. For performance reasons, the time between when the memory controller 209 issues a pause command to hand over an interrupt command to the controller, such as a read or program command, is expected to be short. For example, in some embodiments, once a pause command is issued, the controller 209 should switch to the interrupt command within 20 microseconds.

Depending on where the command is paused, the eraser is interrupted. If the controller fails to move further, it may cause some problems. In flash memory array 202, each block 210 includes a plurality of memory segments 212 that share a common substrate. For example, in memory block 210, memory cell 214 in memory segment 212a shares bit line BL0-BLn and source line SL0-SLn with memory cell 214 in memory segment 212b. Therefore, when the erase program, for example, when the erase program of block 308 or the soft program of block 312 is interrupted, the memory cell 214 in the memory segment 212a potentially generates leakage, which may The memory cells 214 of the shared bit line of other memory segments 212 are affected by subsequent reading or stylization commands of other memory segments 212.

In the procedure shown in Figure 5, if a pause command is received at any point in the program, then the erase operation switches to block 306 where a Fuller-Nordheim (FN) stylized pulse is executed. program. In some embodiments, the Fuller-Nordheim (F-N) stylization of block 306 can be applied to all of the memory cells 214 in the memory segment 212a. In an alternate embodiment, the Fuller-Nordheim (F-N) stylization of block 306 is only applied to memory cells 214 in memory segment 212a that have not completed blocks 302, 308, 312, and 316 erase programs. In the Fuller-Nordheim (FN) stylization program of block 306, a positive voltage is applied to the word lines WL0-WLs of the memory segment 212a where the erase process is being performed, and a negative voltage is applied to The Fuller-Nordheim (FN) stylized memory segment 212a is being processed on the substrate of each memory cell 214.

Figure 6 shows a memory cell 214 that is undergoing a Fuller-Nordheim (F-N) stylization in which a positive voltage is applied to the gate of the transistor and a negative voltage is applied to the substrate on which the transistor is formed. Because this Fuller-Nordheim (FN) stylized drive electron enters the floating gate of the respective memory cell instead of driving it out of the floating gate as in the erase procedure, this Fuller-Nord Han (FN) stylization leads to stylized memory cells instead of erasing memory cells. However, the memory cells caused by block 306 do not generally generate leakage in the interrupt program as if they were over-erased. Since the area of the memory section 212a is relatively small, this Fuller-Nordheim (F-N) stylization does not affect the memory cells 214 of other sections, such as section 212b. The Fuller-Nordheim (F-N) stylization in block 306 can have the advantage of completing the pause command in a very short time to meet the timing requirements of the pause command to avoid leakage problems.

In some embodiments, once the interrupt routine is completed, the erase program in FIG. 5 can be re-executed or restored to erase at least the memory cells that were programmed in block 306.

Although the present invention has been described with reference to the embodiments, the present invention is not limited by the detailed description thereof. Alternatives and modifications are suggested in the foregoing description, and other alternatives and modifications will be apparent to those skilled in the art. In particular, all combinations of components that are substantially identical to the invention can achieve substantially the same results as the present invention without departing from the spirit of the invention. Therefore, all such alternatives and modifications are intended to be within the scope of the invention as defined by the appended claims and their equivalents.

200. . . Memory device

202. . . Memory array

204. . . Row decoder

206. . . Sense amplifier

208. . . Column decoder

209. . . Memory controller

210. . . Memory block

212. . . Memory section

214. . . Flash memory cell

The invention is defined by the scope of the patent application. These and other objects, features, and embodiments are described in the following sections of the accompanying drawings, in which:

Figure 1 shows a flow chart of a conventional erase operation used in a flash memory device.

Figure 2 is a block diagram showing a memory device in accordance with an embodiment of the present invention.

Fig. 3 is a block diagram showing the memory block of the memory device shown in Fig. 2.

Fig. 4 is a detailed block diagram showing the memory block of the memory device shown in Fig. 2.

Figure 5 shows a flow chart of the segment erase operation used in the flash memory device.

Fig. 6 is a detailed block diagram showing the memory cells of the memory device shown in Fig. 2.

For a flow chart, the component symbols have been illustrated in the figures.

Claims (15)

An erasing method in a memory, the memory comprising a plurality of memory cells and being divided into a plurality of segments of the memory cells, the method comprising: performing a erasing procedure on a memory cell of a memory unit; A pause command is received when the erase program is executed; and the erase program is interrupted and a programmatic operation is performed in at least one memory cell of the memory unit in response to the pause command. The method of claim 1, wherein the memory unit is part of one of the plurality of sections. The method of claim 1, wherein the stylizing operation comprises a Fuller-Nordheim (F-N) stylization operation. The method of claim 3, wherein the at least one memory cell comprises a transistor formed on a substrate, and wherein the staging operation comprises applying a positive voltage to a gate of the transistor and applying A negative voltage is applied to the substrate. The method of claim 1, wherein the erasing process comprises applying a pre-programmed pulse to the memory cells of the memory unit. The method of claim 1, wherein the erasing process comprises applying a wipe pulse to the memory cells of the memory unit. The method of claim 1, wherein the erasing process comprises applying a soft stylized pulse to the memory cells of the memory unit. A memory device comprising: a memory array comprising a plurality of memory cells and divided into a plurality of memory blocks, each memory block being divided into memory cells of a plurality of memory segments; and a memory controller, group Forming: erasing a memory cell of a memory unit of the memory array; suspending erasing of the memory cells when performing the erase process to perform an interrupt operation; and after the pause command and executing the Before the interrupt operation, a stylization operation is performed on at least one memory cell of the memory unit. The memory device of claim 8, wherein the memory unit is part of one of the plurality of segments. The memory device of claim 8, wherein the memory unit is a segment. The memory device of claim 8, wherein the stylized operation comprises a Fuller-Nordheim (F-N) stylization operation. The memory device of claim 11, wherein the at least one memory cell comprises a transistor formed on a substrate, and wherein the staging operation comprises applying a positive voltage to a gate of the transistor And applying a negative voltage to the substrate. The memory device of claim 8, wherein the erasing process comprises applying a pre-programmed pulse to the memory cells of the memory unit. The memory device of claim 8, wherein the erasing process comprises applying a wipe pulse to the memory cells of the memory unit. The memory device of claim 8, wherein the erasing program comprises applying a soft stylized pulse to the memory cells of the memory unit.