CN110556145A - Programming method and device of storage unit, electronic equipment and storage medium - Google Patents

Programming method and device of storage unit, electronic equipment and storage medium Download PDF

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Publication number
CN110556145A
CN110556145A CN201810554755.4A CN201810554755A CN110556145A CN 110556145 A CN110556145 A CN 110556145A CN 201810554755 A CN201810554755 A CN 201810554755A CN 110556145 A CN110556145 A CN 110556145A
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China
Prior art keywords
memory cells
programming
verification
memory
memory cell
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CN201810554755.4A
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Chinese (zh)
Inventor
贺元魁
潘荣华
马思博
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Xi'an Geyi Anchuang Integrated Circuit Co Ltd
GigaDevice Semiconductor Beijing Inc
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Xi'an Geyi Anchuang Integrated Circuit Co Ltd
GigaDevice Semiconductor Beijing Inc
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Priority to CN201810554755.4A priority Critical patent/CN110556145A/en
Publication of CN110556145A publication Critical patent/CN110556145A/en
Pending legal-status Critical Current

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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • G11C16/14Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure

Abstract

The invention discloses a programming method and a device of a storage unit and electronic equipment, wherein the method comprises the following steps: performing a programming operation on memory cells in the programming region except for the memory cells passing the program verification; performing programming verification on the memory cells except the memory cells passing the programming verification in the set memory cells; and if the program verification is passed, continuing the programming operation on the memory cells except the set memory cell, otherwise, returning to the step of performing the one-time programming operation on the memory cells except the memory cell passed by the program verification in the programming region. By adopting the technical scheme, the threshold voltage of the storage unit is quickly raised to a higher area, and the programming time is saved.

Description

Programming method and device of storage unit, electronic equipment and storage medium
Technical Field
The embodiment of the invention relates to the technical field of storage, in particular to a programming method and device of a storage unit, electronic equipment and a storage medium.
background
a Nand flash Memory (Nand flash) is a common Memory chip, has the advantages of a Random Access Memory (RAM) and a Read-Only Memory (ROM), does not lose data when power is lost, is a Memory capable of performing electrical erasing in a system, has the advantages of high rewriting speed, large storage capacity and the like, and is widely applied to electronic products.
according to the division of the number of bits of data stored in each memory Cell, Nand flash can be divided into three types, namely SLC (Single-Level Cell), MLC (Multi-Level Cell), and TLC (Triple-Level Cell), wherein each memory Cell of SLC stores one-bit (1bit) of data, each memory Cell of MLC stores 2bit of data, and each memory Cell of TLC stores 3bit of data. The data storage is realized by controlling the distribution of the threshold voltage of the memory cell, and in particular, referring to a schematic diagram of the threshold voltage distribution of the memory cell of TLC shown in fig. 1, when the threshold voltage of the memory cell falls in an a region, it indicates that the data currently stored by the memory cell is 001, when the threshold voltage of the memory cell falls in a B region, it indicates that the data currently stored by the memory cell is 010, and when the threshold voltage of the memory cell falls in a G region, it indicates that the data currently stored by the memory cell is 111.
therefore, to achieve proper data storage of the TLC storage unit, the threshold distribution of the storage unit needs to be controlled by a complex algorithm. How to quickly program the threshold voltage of a TLC memory cell to a desired state becomes a matter of common effort for those skilled in the art.
Disclosure of Invention
the invention provides a programming method and device of a storage unit, electronic equipment and a storage medium, which can quickly raise the threshold voltage of the storage unit to a higher area and save the programming time.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
In a first aspect, an embodiment of the present invention provides a method for programming a memory cell, where the method includes:
performing a programming operation on memory cells in the programming region except for the memory cells passing the program verification;
performing program verification on the memory cells except the memory cells which pass the program verification in the set memory cells;
and if the program verification is passed, continuing the programming operation on the memory cells except the set memory cell, otherwise, returning to the step of performing the one-time programming operation on the memory cells except the memory cell passed by the program verification in the programming region.
further, the set memory cell is a memory cell having a target threshold voltage distribution in a lower range in a program area.
Further, the performing program verification on the memory cells except the memory cell which passes program verification in the set memory cells includes:
and performing program verification on the memory cells except the memory cells passing the program verification in the set memory cells one by one, and shielding the memory cells passing the program verification.
Further, the performing program verification on the memory cells except the memory cells which pass the program verification in the set memory cells includes:
Performing programming verification on a memory cell with the lowest grade in the set memory cells;
If the program verification is not passed, returning to the step of executing the one-time programming operation on the memory cells in the programming region except the memory cells passing the program verification;
If the program verification is passed, shielding the storage unit, and continuously performing program verification on the storage unit with the lowest grade in the rest storage units of the set storage unit;
repeating the judging operation of the verification result until the programming verification of the set storage unit is passed;
The grades of the memory cells are divided according to the distribution range of the target threshold voltage of the memory cells.
Further, the continuing of the programming operation on the memory cells other than the set memory cell includes:
continuing to perform a programming operation on the memory cells except the set memory cell;
Shielding the memory cell with the lowest grade in the memory cells except the set memory cells;
Continuing to perform one-time programming operation on the rest memory cells in the memory cells except the set memory cell;
masking a memory cell with the lowest rank among the remaining memory cells other than the set memory cell;
repeating the continuous programming-shielding operation until the rest memory cells in the memory cells except the set memory cell are zero, and ending the process;
The grades of the memory cells are divided according to the distribution range of the target threshold voltage of the memory cells.
Further, the one-time programming operation is performed on the memory cell, and includes:
the corresponding programming voltages are applied to the gate and the drain of the memory cell, respectively.
Further, the program verifying the memory cell includes:
applying a corresponding read voltage to a gate of a memory cell;
and determining whether the result of the programming verification is passed or not according to the voltage value at the set node of the sensitive amplifier matched with the memory cell.
in a second aspect, an embodiment of the present invention provides an apparatus for programming a memory cell, the apparatus including:
The first programming module is used for carrying out one-time programming operation on the memory cells except the memory cells passing the program verification in the programming region;
The verification module is used for performing programming verification on the memory units except the memory units which pass the programming verification in the set memory units;
The second programming module is used for continuing programming operation on the storage units except the set storage unit if the programming verification is passed;
and the return module is used for returning to the step of carrying out one-time programming operation on the memory cells in the programming area except the memory cells passing the programming verification if the results of the programming verification are not all passed.
in a third aspect, an embodiment of the present invention provides an electronic device, which includes a first memory, a first processor, and a computer program stored in the memory and executable on the first processor, where the first processor implements the method for programming the memory unit according to the first aspect when executing the computer program.
In a fourth aspect, embodiments of the present invention provide a storage medium containing computer-executable instructions which, when executed by a computer processor, implement a method of programming a storage unit as described in the first aspect above.
According to the programming method of the memory unit provided by the embodiment of the invention, after the programming operation is performed on the memory units except the memory unit which passes the programming verification in the programming area for one time, the programming verification is performed on the set memory unit only, and when the programming verification result is passed, the programming operation is continued on the memory units except the set memory unit without performing the programming verification, so that the threshold voltage of the memory unit can be quickly raised to a higher area, and the programming time is saved.
drawings
FIG. 1 is a schematic diagram of a TLC memory cell threshold voltage distribution;
FIG. 2 is a flow chart illustrating a method for programming a memory cell according to one embodiment of the present invention;
Fig. 3 is a schematic structural diagram of a memory cell block according to a first embodiment of the present invention;
FIG. 4 is a diagram illustrating a programming process according to a first embodiment of the present invention;
FIG. 5 is a flowchart illustrating a method for programming a memory cell according to a second embodiment of the present invention;
FIG. 6 is a structural diagram of a programming device for a memory cell according to a third embodiment of the present invention;
Fig. 7 is a schematic structural diagram of an electronic device according to a fourth embodiment of the present invention.
Detailed Description
the present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
example one
Fig. 2 is a flowchart of a programming method of a memory cell according to an embodiment of the present invention, and the programming method provided in this embodiment is suitable for programming a TLC-like Nand flash. Can be implemented by means of a programming device of the memory unit, which can be implemented by means of software and/or hardware, generally integrated in an electronic product applying a TLC type Nand flash. Referring to fig. 2 specifically, the programming method of the memory cell provided in this embodiment specifically includes the following steps:
210. And performing one-time programming operation on the memory cells except the memory cells passing the program verification in the programming region.
the programming region may specifically refer to a programming page. The Nandflash chip is composed of thousands of memory cells inside, the memory cells constitute pages, the pages constitute blocks, and due to the special physical structure, Nandflash performs programming operation (or reading/writing data) in units of pages and performs erasing operation in units of blocks. Referring specifically to the schematic structural diagram of the memory cell block shown in fig. 3, the memory cells with word lines connected together are memory cell pages, and the memory cell block shown in fig. 3 includes 3 memory cell pages.
illustratively, the one-time programming operation is performed on the memory cell, including:
The purpose of changing the threshold voltage of a memory cell is to change the number of electrons on the floating gate of the memory cell by a voltage difference by applying a corresponding programming voltage to the gate and the drain of the memory cell, that is, applying a corresponding programming voltage to the word line and the bit line of the memory cell once. The programming operation is to increase the number of electrons on the floating gate, thereby raising the threshold voltage of the memory cell. Since the programming voltage applied to the word line and the bit line of a memory cell in a programming region in one programming operation only lasts for ns, the application of the programming voltage is usually selected by a charge pump.
since the memory cells that pass the program verification are zero when the program operation is performed for the first time, all the memory cells in the program area are targeted for the first program operation.
220. And performing program verification on the memory cells except the memory cells which pass the program verification in the set memory cells.
The set memory cell is a memory cell in which a target threshold voltage in a programming region is distributed in a lower range, and the target threshold voltage refers to a desired voltage after raising a threshold voltage of the memory cell. As each memory cell of the TLC-type Nandflash can store 3-bit data, and the storage of the 3-bit data is realized by raising the threshold voltage of the memory cell to different voltage ranges, referring to a schematic distribution diagram of the threshold voltage of the TLC memory cell shown in fig. 1, when the threshold voltage of the memory cell falls in an area a, it indicates that the currently stored data of the memory cell is 001, and when the threshold voltage of the memory cell falls in an area B, it indicates that the currently stored data of the memory cell is 010, and when the threshold voltage of the memory cell falls in an area G, it indicates that the currently stored data of the memory cell is 111. The target threshold voltage distribution may specifically be any one of a-G. The memory cells in the program region having the target threshold voltage distribution in the lower range may specifically refer to the memory cells having the target threshold voltage distribution in any one of a-C. In this embodiment, the set memory cell is taken as a memory cell with a target threshold voltage distribution in A-C.
in the first program verification, the storage unit passing the verification is zero, so that the first program verification is performed on all set storage units, namely, storage units with target threshold voltages distributed in A-C. And then, each program verification is only carried out on the memory cells which do not pass the program verification in the set memory cells.
Illustratively, the program verifying the memory cell includes:
applying corresponding reading voltages to the gates of the memory cells respectively;
And determining whether the result of the programming verification is passed or not according to the voltage value at the set node of the sense amplifier matched with the memory cell, and determining that the result of the programming verification is passed if the voltage value at the set node is lower than a set value. The specific structure of the sense amplifier matched with the setting memory cell can refer to the prior art, and the detailed explanation of the embodiment is omitted.
For example, the performing program verification on the memory cells except the memory cells which pass the program verification among the set memory cells includes:
And performing program verification on the memory cells except the memory cells passing the program verification in the set memory cells one by one, and shielding the memory cells passing the program verification.
230. And judging whether the programming verification passes, if so, executing the step 240, otherwise, returning to execute the step 210.
240. and continuing the programming operation on the memory cells except the set memory cell.
Illustratively, the continuing of the programming operation on the memory cells other than the set memory cell includes:
continuing to perform a programming operation on the memory cells except the set memory cell;
Shielding the memory cell with the lowest grade in the memory cells except the set memory cells;
continuing to perform one-time programming operation on the rest memory cells in the memory cells except the set memory cell;
Masking a memory cell with the lowest rank among the remaining memory cells other than the set memory cell;
repeating the continuous programming-shielding operation until the rest memory cells in the memory cells except the set memory cell are zero, and ending the process;
The grades of the memory cells are divided according to the distribution range of the target threshold voltage of the memory cells.
To illustrate the above process, assuming that the levels of all the memory cells of the program area include seven levels a to G, the levels a to G of the memory cells are divided according to the distribution range of the target threshold voltages of the memory cells, as shown in fig. 1. The setting storage unit is a storage unit of a grade A-C. Since the memory cells passing the program verification are zero at the beginning of the program, the program operation is performed on all the memory cells in the program area once, that is, the memory cells with the levels of A-G are subjected to the program operation once, then the memory cells with the levels of A-C of the memory cells are subjected to the program verification, if the verification results are all passed, the program operation is continued on the memory cells with the levels of D-G, but the program verification is not performed on the memory cells with the levels of D-G. If the set memory cells which do not pass the verification exist, the step 210 is returned to continue the programming operation for the memory cells in the programming region except the memory cells which pass the program verification. For example, if the memory cell with the level A passes verification but the memory cells with the levels B and C do not pass verification, the memory cell with the levels B-G continues to be subjected to one-time programming operation, then the memory cells with the levels B and C are subjected to programming verification, and if the memory cell with the level B passes verification but the memory cell with the level C does not pass verification, the memory cell with the levels C-G continues to be subjected to one-time programming operation until the memory cell with the level C passes verification.
And then continuing to perform programming operation on the memory cells with the levels D-G without performing programming verification, specifically: performing one-time programming operation on the memory cells with the levels of D-G, and shielding the memory cells with the lowest level (D level); continuing to perform one-time programming operation on the memory cells with the levels of E-G, and shielding the memory cells with the lowest level (E level); continuing to perform one-time programming operation on the memory cells with the F-G levels, and shielding the memory cells with the lowest level (F level); continuing to perform a programming operation on the memory cell of level G, and ending the process, see the schematic diagram of the programming process shown in fig. 4.
Since the threshold voltages of the memory cells are slowly raised, only the memory cells with the target threshold voltage distribution in the low range can be selectively subjected to program verification, and if the program verification is passed, the memory cells with the target threshold voltage distribution in the high range continue to be subjected to the program operation, so that the threshold voltages of the memory cells in the part are raised higher. Because the programming verification is not carried out on the storage units except the set storage unit, the occupied time of the whole programming process is shorter, and the programming speed is higher.
in the programming method of a memory cell provided in this embodiment, after performing a programming operation on a memory cell in a programming region, only a set memory cell is subjected to programming verification, and if the result of the programming verification is passed, the programming operation is continued on a memory cell other than the set memory cell.
example two
Fig. 5 is a schematic flow chart of a programming method of a memory cell according to a second embodiment of the present invention, and on the basis of the second embodiment, the present embodiment optimizes the operation "program verify the memory cell except the memory cell that passes the program verify" in the set memory cell, so as to further improve the programming speed. Referring to fig. 5, the programming method of the memory cell provided in this embodiment specifically includes the following steps:
510. And performing one-time programming operation on the memory cells except the memory cells passing the program verification in the programming region.
520. and performing programming verification on the memory cell with the lowest current grade in the set memory cells.
530. and judging whether the program verification passes, if so, continuing to execute the step 540, otherwise, returning to execute the step 510.
540. And shielding the memory cells passing the program verification.
550. And judging whether the programming verification of the set memory cells passes, if so, executing step 560, otherwise, returning to execute step 520.
560. And continuing the programming operation on the memory cells except the set memory cell.
to illustrate the above process, assuming that the ranks of all the memory cells of the program area include seven ranks A-G, the memory cells are set to be the memory cells of ranks A-C. Since the memory cells that pass the program verification are zero at the beginning of the program, first, a program operation is performed on all the memory cells in the program area, that is, a program operation is performed on the memory cells of the levels a to G, then, a program verification is performed on the memory cell (the memory cell of the level a) with the lowest level among the memory cells (the memory cells of the levels a to C), if the program verification result is passed, the memory cell of the level a is masked, and the step 520 is continuously performed to perform the program verification on the memory cell of the level B; if the program verification result of the memory cell of the level a is failed, the program verification of the memory cells of the levels B and C is abandoned, and the step 510 is directly returned to perform a program operation on the memory cells in the program area except the memory cell of which the program verification is passed, thereby further saving the program time. If the program verification result of the memory cell with level a in the one-time program verification cycle is passed, but the program verification result of the memory cell with level B is failed, the step 510 is returned to perform one-time program operation on the memory cells with levels B to G, and not perform any program operation on the memory cell with level a with program verification passed, and then the program verification … … is continued to perform program verification on the memory cell with level B, and the program verification cycle is repeated until the program verification result of the memory cell is set to pass. After the programming verification results of the set memory cells are all passed, only the memory cells (the memory cells of the level D-G) except the set memory cells are subjected to the programming operation, and the programming verification is not performed any more, and the specific process of performing the programming operation on the memory cells (the memory cells of the level D-G) except the set memory cells can refer to the explanation in the first embodiment, and is not repeated here.
The memory cells of level D-G continue the programming operation, but the memory cells of level D-G are no longer program verified. If the set memory cells which do not pass the verification exist, the step 210 is returned to continue the programming operation for the memory cells in the programming region except the memory cells which pass the program verification. For example, if the memory cell with the level A passes verification but the memory cells with the levels B and C do not pass verification, the memory cell with the levels B-G continues to be subjected to one-time programming operation, then the memory cells with the levels B and C are subjected to programming verification, and if the memory cell with the level B passes verification but the memory cell with the level C does not pass verification, the memory cell with the levels C-G continues to be subjected to one-time programming operation until the memory cell with the level C passes verification.
and then continuing to perform programming operation on the memory cells with the levels D-G without performing programming verification, specifically: performing one-time programming operation on the memory cells with the levels of D-G, and shielding the memory cells with the lowest level (D level); continuing to perform one-time programming operation on the memory cells with the levels of E-G, and shielding the memory cells with the lowest level (E level); continuing to perform one-time programming operation on the memory cells with the F-G levels, and shielding the memory cells with the lowest level (F level); continuing to perform a programming operation on the memory cell of level G, and ending the process, see the schematic diagram of the programming process shown in fig. 4.
in the programming method of the memory cell provided in this embodiment, if the program verification result of the memory cell with the lowest rank in the set memory cells is failed, the program verification of the memory cells with other ranks in the set memory cells is abandoned, and the step of performing the one-time programming operation on the memory cells except the memory cells with the program verification passed in the programming region is directly returned until the program verification result of the memory cell with the lowest rank is passed, and then the program verification is performed on the memory cells with other ranks in the set memory cells, thereby further saving the programming time and improving the programming speed.
EXAMPLE III
Fig. 6 is a schematic structural diagram of a programming apparatus for a memory cell according to a third embodiment of the present invention. Referring to fig. 6, the apparatus includes: a first programming module 610, a verification module 620, a second programming module 630, and a return module 640;
The first programming module 610 is configured to perform a one-time programming operation on memory cells in the programming region, except for memory cells passing program verification;
the verifying module 620 is configured to perform program verification on the memory cells except for the memory cells that pass the program verification in the set memory cells;
a second programming module 630, configured to continue the programming operation on the memory cells other than the set memory cell if the program verification passes;
and a returning module 640, configured to return to the step of performing a program operation on memory cells in the program area except the memory cells that have passed the program verification if the program verifications do not all pass.
In the programming apparatus for a memory cell provided in this embodiment, after performing a programming operation on memory cells in a programming region except for the memory cells passing the programming verification, only the set memory cells are subjected to the programming verification, and if the programming verification passes, the programming operation is continued on the memory cells except for the set memory cells, and the programming verification is not performed on the memory cells except for the set memory cells, so that the threshold voltage of the memory cells can be quickly raised to a higher region, and the programming time is saved.
Example four
fig. 7 is a schematic structural diagram of an electronic device according to a fourth embodiment of the present invention. As shown in fig. 7, the electronic apparatus includes: a first processor 770, a first memory 771, and computer programs stored on the first memory 771 and executable on the first processor 770; the number of the first processors 770 may be one or more, and one first processor 770 is taken as an example in fig. 7; the first processor 770, when executing the computer program, implements the method for programming the memory cell as described in the first embodiment above. As shown in fig. 7, the electronic device may further include a first input device 772 and a first output device 773. The first processor 770, the first memory 771, the first input device 772, and the first output device 773 may be connected by a bus, as exemplified by a bus in fig. 7.
The first memory 771 is used as a computer-readable storage medium for storing software programs, computer-executable programs, and modules, such as a programming device/module of a memory unit (e.g., the first programming module 610 and the verification module 620 in the programming device of the memory unit, etc.) in an embodiment of the present invention. The first processor 770 executes various functional applications and data processing of the electronic device by executing software programs, instructions and modules stored in the first memory 771, that is, implements the above-described programming method of the memory unit.
The first memory 771 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal, and the like. Further, the first memory 771 may include high speed random access memory and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or non-volatile solid state storage device. In some examples, the first memory 771 may further include memory located remotely from the first processor 770, which may be connected to electronic devices/storage media through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The first input device 772 may be used to receive input numeric or character information and generate key signal inputs related to user settings and function controls of the electronic apparatus. The first output device 773 may include a display device such as a display screen.
EXAMPLE five
An embodiment of the present invention further provides a storage medium containing computer-executable instructions, which when executed by a computer processor, perform a method of programming a storage unit, the method including:
Performing one-time programming operation on the memory cells except the memory cells passing the program verification in the programming region;
performing program verification on the memory cells except the memory cells which pass the program verification in the set memory cells;
And if the program verification is passed, continuing the programming operation on the memory cells except the set memory cell, otherwise, returning to the step of performing the one-time programming operation on the memory cells except the memory cell passed by the program verification in the programming region.
of course, the storage medium provided by the embodiment of the present invention contains computer-executable instructions, and the computer-executable instructions are not limited to the method operations described above, and may also perform operations related to programming of the storage unit provided by any embodiment of the present invention.
From the above description of the embodiments, it is obvious for those skilled in the art that the present invention can be implemented by software and necessary general hardware, and certainly, can also be implemented by hardware, but the former is a better embodiment in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which may be stored in a computer-readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, and includes several instructions for enabling a computer device (which may be a personal computer, a storage medium, or a network device) to execute the embodiments of the present invention.
it is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include more equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (10)

1. a method of programming a memory cell, comprising:
Performing a programming operation on memory cells in the programming region except for the memory cells passing the program verification;
Performing programming verification on the memory cells except the memory cells passing the programming verification in the set memory cells;
and if the program verification is passed, continuing the programming operation on the memory cells except the set memory cell, otherwise, returning to the step of performing the one-time programming operation on the memory cells except the memory cell passed by the program verification in the programming region.
2. The method of claim 1, wherein the set memory cells are memory cells in a programming region having a lower threshold voltage distribution.
3. The method of claim 1, wherein the program verifying the set memory cells except the memory cells that pass the program verifying comprises:
and performing program verification on the memory cells except the memory cells passing the program verification in the set memory cells one by one, and shielding the memory cells passing the program verification.
4. The method of claim 1, wherein the program verifying the set memory cells except the memory cells that pass the program verifying comprises:
Performing programming verification on a memory cell with the lowest grade in the set memory cells;
If the program verification is not passed, returning to the step of executing the one-time programming operation on the memory cells in the programming region except the memory cells passing the program verification;
if the program verification is passed, shielding the storage unit, and continuously performing program verification on the storage unit with the lowest grade in the rest storage units of the set storage unit;
repeating the judging operation of the programming verification until the programming verification of the set storage unit passes;
the grades of the memory cells are divided according to the distribution range of the target threshold voltage of the memory cells.
5. The method according to any one of claims 1-4, wherein continuing the programming operation on the memory cells other than the set memory cell comprises:
continuing to perform a programming operation on the memory cells except the set memory cell;
shielding the memory cell with the lowest grade in the memory cells except the set memory cells;
continuing to perform one-time programming operation on the rest memory cells in the memory cells except the set memory cell;
masking a memory cell with the lowest rank among the remaining memory cells other than the set memory cell;
Repeating the continuous programming-shielding operation until the rest memory cells in the memory cells except the set memory cell are zero, and ending the process;
the grades of the memory cells are divided according to the distribution range of the target threshold voltage of the memory cells.
6. the method according to any one of claims 1-4, wherein performing a program operation on the memory cell comprises:
the corresponding programming voltages are applied to the gate and the drain of the memory cell, respectively.
7. The method of any of claims 1-4, wherein performing program verification on the memory cell comprises:
applying a corresponding read voltage to a gate of a memory cell;
And determining whether the result of the programming verification is passed or not according to the voltage value at the set node of the sensitive amplifier matched with the memory cell.
8. an apparatus for programming a memory cell, the apparatus comprising:
The first programming module is used for carrying out one-time programming operation on the memory cells except the memory cells passing the program verification in the programming region;
the verification module is used for performing programming verification on the memory units except the memory units which pass the programming verification in the set memory units;
The second programming module is used for continuing programming operation on the storage units except the set storage unit if the programming verification is passed;
And the return module is used for returning to the step of carrying out one-time programming operation on the memory cells in the programming area except the memory cells passing the programming verification if the results of the programming verification are not all passed.
9. An electronic device comprising a first memory, a first processor and a computer program stored on the memory and executable on the first processor, characterized in that the first processor implements the method of programming a memory unit according to any of claims 1-7 when executing the computer program.
10. a storage medium containing computer-executable instructions which, when executed by a computer processor, implement a method of programming a storage unit according to any one of claims 1-7.
CN201810554755.4A 2018-06-01 2018-06-01 Programming method and device of storage unit, electronic equipment and storage medium Pending CN110556145A (en)

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CN113409851B (en) * 2021-06-29 2024-03-15 芯天下技术股份有限公司 Method and device for programming multiple blocks simultaneously, electronic equipment and storage medium

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