201005742 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種記憶體讀取方法及記憶體，且特 別是有關於一種可以擴大讀取區間及降低讀取擾亂之記 憶體讀取方法及記憶體。 【先前技術】 記憶體係應用於現今之多種資料儲存之用途。記憶體 修包括多種型式，例如為多位階單元(Multi-Level Cell，MLC) 記憶體等。請參照第1A圖，其繪示傳統多位階單元之示 意圖。多位階單元100包括左半單元110及右半單元120。 依據臨界電壓分佈之不同，多位階單元100之每一個半單 元可以具有多個位元。 茲以每一個半單元具有2個位元為例做說明，請參照 第1Β圖，其繪示多位階單元100之臨界電壓分佈之分佈 圖。其中，左半單元110及右半單元120之臨界電壓分佈 ®通常係依序被定義為（11，10，01，00)，然並不限於此。 於第1Β圖中之每一個臨界電壓分佈都必須要盡可能地集 中，以保留足夠的讀取區間（read window)。 然而，因為第二位元效應（second-biteffect)，右半單 元120之臨界電壓會被左半單元110之臨界電壓所影響， 使得讀取區間變小而導致右半單元120於被讀取時產生錯 誤。此外，若用以讀取之位元線電壓或字元線電壓過高， 則可能對左半單元110之低臨界電壓產生影響，導致左半 201005742 ^ 被讀取時產生讀取擾亂(read disturbance)的現 麥〇 【發明内容】 判斷 以讀取目標半單元所儲;子=低，據以利用不同的電壓 «及降低讀取擾亂的優點身料’具有可以擴大讀取區間 根據本發明之第一方面，提出一種記憶體讀取方法， 1 己憶體包括至記憶單元，此記憶單it包括-第-半單 1第—半單％ °記憶體讀取方法包括下列步驟。施加 一第-電麼於記憶單元以判斷第一半單元之臨界電壓是 ^於-特定值。若第—半單元之臨界電壓高於特定值， $加-第二電麼於記憶單元以讀取第二半單元所儲存之 參^:第:電壓高於第一電壓，否則施加一第三電壓於記 ‘、、2以Λ取第二半單元所儲存之資料，第三電壓 一電壓。 一 ^根，本發明之第二方面，提出—種記憶體，包括至少 一記憶單元以及-錢電路。此記憶單元包括—第一半單 ，及-第二半單元。偏壓電路用以施加電壓於記憶單元。 j中’偏壓電路施加-第-電壓於記憶單元以判斷第一半 :二之臨界電壓是否高於一特定值。若第一半單元之臨界 電麼高於特定值，偏Μ電路施加-第二電壓於記憶單元以 6 201005742 讀取第二半單元所儲存之資料，第二電壓高於第一電壓， 否則偏壓電路施加一第三電壓於記憶單元以讀取第二半 單元所儲存之資料，第三電壓低於該第一電壓。 為讓本發明之上述内容能更明顯易懂，下文特舉一較 佳實施例，並配合所附圖式，作詳細說明如下： 【實施方式】 本發明係提供一種記憶體讀取方法及記憶體，藉由判 β斷相鄰半單元之臨界電壓之高低，據以利用不同的電壓以 讀取目標半單元所儲存之資料，故可以擴大（enlarge)讀取 區間（read window)及降低讀取擾亂（read disturbance)。 於本發明下述之實施例中，茲舉記憶體為一多位階單 元記憶體，及記憶單元為多位階單元為例做說明，然並不 限於此。 請參照第2圖，其繪示依照本發明較佳實施例之記憶 體讀取方法之流程圖。本實施例所揭露之記憶體讀取方 ®法，實質上係應用於一多位階單元（MLC)記憶體，此多位 階單元記憶體包括多個記憶單元區塊，每一個記憶單元區 塊包括多個多位階單元，每一個多位階單元包括一左半單 元及一右半單元。此多位階單元記憶體例如為一電荷補捉 記憶體（charge trapped memory)。 茲以一多位階單元之右半單元為所欲讀取之目標單 元，左半單元為相鄰單元為例做說明。首先，於步驟S200 中，施加一第一電壓於多位階單元之汲極端之位元線，以 7 判斷相鄰的左半單元之臨界電壓是否高於一特定值。其 中，特疋值實質上係為4伏特。其中，第一電屢為不會造 成讀取擾亂之多㈣單元的祕端電壓的上限，例如為16 伏特，但不限於此，可能隨著製程演進而有所改變。步驟 fOO實質上係用以判斷相鄰的左半單元之臨界電壓屬於 高臨界電壓或低臨界電！。 若左半單元之臨界電壓高於特定值，亦即左半單元之 臨界電壓屬於高臨界電壓，則於步驟S21〇中，施加一第 壓於多位階單元之汲極端之位元線，以讀取目標的右 半早7〇所儲存之資料，其中第二電壓高於第一電壓。第二 f壓係為-高位元線電壓，例如為18伏特。對於多位階 單元而^，若汲極端之偏壓為高電壓準位，則多位階單元 之左半單元及右半單元之臨界電壓比較不會受影響。故於 步驟S210中，利用高位元線電壓以讀取右半單元所儲存 之資料，可以降低第二位元效應對於右半單元之臨界電壓 談的影響，使得讀取區間擴大。此外，因為左半單元之臨界 電㈣於高臨界電壓而不會受位元線之電壓影響，可 讀取擾亂的現象。 _ 若左半單元之臨界電壓低於特定值，亦即左半單元之 L界電㈣於低臨界㈣，則於步驟S22Q中，施加 三電壓於多位階單元之汲極端之位元線，以讀取右半單元 存之資料，其中第三低於第，。第三電虔係 為一低位元線，例如為M伏特。因為左半 臨 界電虔屬於低臨界電壓，若利用高位元線電壓以讀取右半 201005742 單元所儲存之資料’則高位元線電壓會影響到左半單元之 低臨界電壓而趨向高臨界電壓，導致左半單元於被讀取時 產生讀取擾亂的現象。故利用低位元線電壓以讀取右半單 元所儲存之資料，可以避免影響到左半單元之低臨界電 壓’降低讀取擾亂的現象。 此外，上述之記憶體讀取方法中，係以第一電壓、第 二電壓及第三電壓被施加於多位階單元之汲極端為例做 說明，然並不限於此。第一電壓、第二電壓及第三電壓亦 罾可被施加於多位階單元所對應之字元線，亦可達到同樣的 效果。 一此外，本發明亦提供一種記憶體。請參照第3圖，其 繪示依照本發明較佳實施例之記憶體之部份電路圖。記憶 體300例如為一電荷補捉記憶體，其包括多個多位階單元 及一偏壓電路320。於第3圖中，係僅以多位階單元31〇 為例做說明，然並不限於此。多位階單元31〇包括一第一 半單元312及-第二半單元314。偏麗電路32〇用以施加 電壓於多位階單元31〇β偏壓電路32〇施加一第一電壓於 多位階單元3Η)以判斷第一半單元312之臨界電壓是否高 於一特 +定值^其中，此特定值實質上例如為4伏特。 若第半單元312之臨界電壓高於特定值，偏壓電路 320施加-第二電壓於多位階單a 3ι〇以讀取第二半單元 所儲存之負料，第二電壓高於第一電麼，否則偏虔電 路320施加第二電壓於多位階單元31〇以讀取第二半單 το 314所儲存之資料，第三電屢低於第一電麼。其中，第 201005742 一電壓、第二電壓及第三電壓例如被施加於多位階單元 310之汲極端，且第一電壓實質上例如為1.6伏特。然並 不限於此，第一電壓、第二電壓及第三電壓亦可被施加於 多位階單元310所對應之字元線WL。 此外，偏壓電路320包括一第一偏壓產生器330及一 第二偏壓產生器340、一第一電晶體Ml、一第二電晶體 M2、一第三電晶體M3以及一第四電晶體M4。第一電晶 體Ml之第一端耦接至一電源VDD，第一電晶體Ml之第 _二端耦接至多位階單元310之第一端，第一電晶體Ml之 控制端耦接至第一偏壓產生器330。第二電晶體M2之第 一端耦接至多位階單元310之第一端，第二電晶體M2之 第二端耦接至一地電壓GND，第二電晶體M2之控制端接 收一第一控制訊號Ctrll。 第三電晶體M3之第一端耦接至電源VDD，第三電 晶體M3之第二端耦接至多位階單元310之第二端，第三 電晶體M3之控制端耦接至第二偏壓產生器340。第四電 ❹晶體M4之第一端耦接至多位階單元310之第二端，第四 電晶體M4之第二端耦接至地電壓GND，第四電晶體M4 之控制端接收一第二控制訊號Ctrl2。 第一偏壓產生器330以第一電壓加上第一電晶體Ml 之臨界電壓導通第一電晶體Ml，第一控制訊號Ctrll截止 第二電晶體M2，第二偏壓產生器340截止第三電晶體 M3，第二控制訊號Ctrl2導通第四電晶體M4。如此一來， 多位階單元310之第一端之電壓被第一電晶體Ml箝位在 201005742 第一電壓，多位階單元310之第二端耦接至地電壓GND， 使得偏壓電路320得以判斷第一半單元312之臨界電壓是 否高於特定值。 若第一半單元312之臨界電壓高於特定值，則第一偏 壓產生器330截止第一電晶體Μ卜第一控制訊號Ctrll導 通第二電晶體M2，第二偏壓產生器340以高於第一電壓 之第二電壓加上第三電晶體M3之臨界電壓導通第三電晶 體M3，第二控制訊號Ctrl2截止第四電晶體M4。如此一 參來，多位階單元310之第二端之電壓被第三電晶體M3箝 位在第二電壓，多位階單元310之第一端耦接至地電壓 GND，使得偏壓電路320得以讀取第二半單元314所儲存 之資料。 若第一半單元312之臨界電壓低於特定值，則第一偏 壓產生器330戴止第一電晶體Ml，第一控制訊號Ctrll導 通第二電晶體M2，第二偏壓產生器340以低於第一電壓 之第三電壓加上第三電晶體M3之臨界電壓導通第三電晶 ®體M3，第二控制訊號Ctrl2截止第四電晶體M4。如此一 來，多位階單元310之第二端之電壓被第三電晶體M3箝 位在第三電壓，多位階單元310之第一端耦接至地電壓 GND，使得偏壓電路320得以用來讀取第二半單元314所 儲存之資料。 上述之記憶體300之操作原理係已詳述於本發明實 施例所揭露之記憶體讀取方法中，故於此不再重述。 本發明上述實施例所揭露之記憶體讀取方法及記憶 11 201005742 體，係藉由判斷所要讀取之目標單元其相鄰半單元之臨界 電壓為高臨界電壓或低臨界電壓。若相鄰半單元之臨界電 壓為高臨界電壓，則以高位元線電壓或高字元線電壓讀取 目標半單元所儲存之資料，而得以擴大讀取區間並降低第 二位元效應。若相鄰半單元之臨界電壓為低臨界電壓，則 以低位元線電壓或低字元線電壓讀取目標半單元所儲存 之資料，而得以降低讀取擾亂。 綜上所述，雖然本發明已以一較佳實施例揭露如上， ®然其並非用以限定本發明。本發明所屬技術領域中具有通 常知識者，在不脫離本發明之精神和範圍内，當可作各種 之更動與潤飾。因此，本發明之保護範圍當視後附之申請 專利範圍所界定者為準。 參 12 201005742 【圖式簡單說明】 第1A圖繪示傳統多位階單元之示意圖。 第1Β ϋ繪τρ多位階單元之臨界電壓分佈之分佈圖。 第2圖繪不依照本發明較佳實施例之記憶體讀取方 法之流程圖。 第3圖繪示依照本發明較佳實施例之記憶體之部份 電路圖。 ®【主要元件符號說明】 100 、310 :多位階單元 110 左半單元 120 右半單元 300 記憶體 312 第一半單元 314 第二半單元 320 偏壓電路 330 第一偏壓產生器 340 第二偏壓產生器 13201005742 IX. Description of the Invention: [Technical Field] The present invention relates to a memory reading method and a memory, and more particularly to a memory reading method capable of expanding a reading interval and reducing reading disturbance And memory. [Prior Art] Memory systems are used in a variety of data storage applications today. Memory repairs include a variety of types, such as Multi-Level Cell (MLC) memory. Please refer to FIG. 1A, which illustrates the schematic of a conventional multi-level cell. The multi-level unit 100 includes a left half unit 110 and a right half unit 120. Each half unit of the multi-level unit 100 may have a plurality of bits depending on the critical voltage distribution. For example, each half unit has 2 bits as an example. Please refer to the first figure, which shows the distribution of the threshold voltage distribution of the multi-level unit 100. The threshold voltage distributions of the left half unit 110 and the right half unit 120 are generally defined as (11, 10, 01, 00) in sequence, but are not limited thereto. Each of the threshold voltage distributions in Figure 1 must be concentrated as much as possible to preserve enough read window. However, because of the second-bit effect, the threshold voltage of the right half cell 120 is affected by the threshold voltage of the left half cell 110, causing the read interval to become smaller and causing the right half cell 120 to be read. An error has occurred. In addition, if the bit line voltage or the word line voltage used for reading is too high, the low threshold voltage of the left half unit 110 may be affected, resulting in read disturbance when the left half 201005742 ^ is read (read disturbance) The current wheat 〇 【 发明 发明 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 】 In a first aspect, a memory reading method is proposed, wherein the memory unit includes a memory cell, and the memory sheet includes a first-semi-single 1st-semi-single-% memory reading method including the following steps. A first-electrode is applied to the memory cell to determine that the threshold voltage of the first half-cell is ^--specific value. If the threshold voltage of the first half unit is higher than a specific value, $plus-second power is stored in the memory unit to read the parameter stored in the second half unit: the first voltage is higher than the first voltage, otherwise a third is applied. The voltage is recorded in ', 2 to capture the data stored in the second half of the unit, and the third voltage is a voltage. In a second aspect of the invention, a memory is provided, comprising at least one memory unit and a money circuit. The memory unit includes a first half single and a second half unit. A bias circuit is used to apply a voltage to the memory unit. The 'biasing circuit' applies a -first voltage to the memory cell to determine whether the first half: the threshold voltage of the second is higher than a specific value. If the critical voltage of the first half unit is higher than a specific value, the bias circuit applies a second voltage to the memory unit to read the data stored in the second half unit at 6 201005742, and the second voltage is higher than the first voltage, otherwise The voltage circuit applies a third voltage to the memory unit to read the data stored in the second half unit, and the third voltage is lower than the first voltage. In order to make the above description of the present invention more comprehensible, a preferred embodiment will be described below in detail with reference to the accompanying drawings. The present invention provides a memory reading method and memory. Body, by judging the level of the threshold voltage of the adjacent half unit, according to the use of different voltages to read the data stored in the target half unit, so you can enlarge the read window and reduce the read Read disturbance. In the following embodiments of the present invention, the memory is a multi-level cell memory, and the memory cell is a multi-level cell as an example, but is not limited thereto. Referring to FIG. 2, a flow chart of a memory reading method in accordance with a preferred embodiment of the present invention is shown. The memory reading method of the present embodiment is substantially applied to a multi-level cell (MLC) memory. The multi-level cell memory includes a plurality of memory cell blocks, and each memory cell block includes A plurality of multi-level cells, each multi-level cell comprising a left half unit and a right half unit. The multi-level cell memory is, for example, a charge trapped memory. The right half of a multi-level cell is the target cell to be read, and the left half is an adjacent cell. First, in step S200, a first voltage is applied to the bit line of the 汲 extreme of the multi-level cell, and 7 is used to determine whether the threshold voltage of the adjacent left half cell is higher than a specific value. Among them, the characteristic value is substantially 4 volts. Among them, the first power is not the upper limit of the secret voltage of the unit (4) which does not cause the disturbance to be disturbed, for example, 16 volts, but is not limited thereto, and may change as the process evolves. Step fOO is essentially used to determine that the threshold voltage of the adjacent left half unit belongs to a high threshold voltage or a low critical power! . If the threshold voltage of the left half unit is higher than a specific value, that is, the threshold voltage of the left half unit belongs to a high threshold voltage, then in step S21, a bit line that is pressed to the 汲 extreme of the multi-level unit is applied to read The data stored in the right half of the target is 7 早, wherein the second voltage is higher than the first voltage. The second f voltage is a high bit line voltage, for example 18 volts. For a multi-level cell, if the bias voltage of the 汲 terminal is a high voltage level, the threshold voltages of the left half cell and the right half cell of the multi-level cell are not affected. Therefore, in step S210, by using the high bit line voltage to read the data stored in the right half cell, the influence of the second bit effect on the threshold voltage of the right half cell can be reduced, so that the read interval is expanded. In addition, because the criticality of the left half cell (4) is at a high threshold voltage and is not affected by the voltage of the bit line, the disturbing phenomenon can be read. _ If the threshold voltage of the left half unit is lower than a specific value, that is, the L boundary of the left half unit (4) is at the low threshold (4), then in step S22Q, three voltages are applied to the bit line of the 汲 extreme of the multi-level unit to Read the data stored in the right half of the cell, where the third is lower than the first. The third electrical system is a low bit line, for example, M volts. Because the left semi-critical 虔 is a low threshold voltage, if the high bit line voltage is used to read the data stored in the right half of the 201005742 unit, the high bit line voltage will affect the low threshold voltage of the left half cell and tend to a high threshold voltage. This causes the left half unit to produce read disturb when it is read. Therefore, by using the low bit line voltage to read the data stored in the right half unit, it is possible to avoid the phenomenon that the low critical voltage of the left half unit is reduced to reduce the reading disturbance. Further, in the above-described memory reading method, the first voltage, the second voltage, and the third voltage are applied to the 汲 extremes of the multi-level unit as an example, but are not limited thereto. The first voltage, the second voltage, and the third voltage can also be applied to the word lines corresponding to the multi-level cells, and the same effect can be achieved. In addition, the present invention also provides a memory. Please refer to FIG. 3, which is a partial circuit diagram of a memory according to a preferred embodiment of the present invention. The memory 300 is, for example, a charge trapping memory comprising a plurality of multi-level cells and a bias circuit 320. In the third figure, the description is made only by taking the multi-level unit 31〇 as an example, but it is not limited thereto. The multi-level unit 31A includes a first half unit 312 and a second half unit 314. The bias circuit 32 is configured to apply a voltage to the multi-level unit 31 〇β bias circuit 32 〇 to apply a first voltage to the multi-level unit 3 Η) to determine whether the threshold voltage of the first half unit 312 is higher than a special value The value ^ where this particular value is substantially, for example, 4 volts. If the threshold voltage of the first half unit 312 is higher than a specific value, the bias circuit 320 applies a second voltage to the multi-level single a 3 〇 读取 to read the negative material stored in the second half unit, and the second voltage is higher than the first Otherwise, the bias circuit 320 applies a second voltage to the multi-level unit 31 〇 to read the data stored in the second half το 314, which is lower than the first power. Wherein, a voltage, a second voltage, and a third voltage are applied to the 汲 terminal of the multi-level unit 310, for example, and the first voltage is substantially 1.6 volts, for example. However, the first voltage, the second voltage, and the third voltage may be applied to the word line WL corresponding to the multi-level unit 310. In addition, the bias circuit 320 includes a first bias generator 330 and a second bias generator 340, a first transistor M1, a second transistor M2, a third transistor M3, and a fourth Transistor M4. The first end of the first transistor M1 is coupled to a power supply VDD, and the second end of the first transistor M1 is coupled to the first end of the multi-level unit 310, and the control end of the first transistor M1 is coupled to the first end. Bias generator 330. The first end of the second transistor M2 is coupled to the first end of the multi-level cell 310, the second end of the second transistor M2 is coupled to a ground voltage GND, and the control end of the second transistor M2 receives a first control. Signal Ctrll. The first end of the third transistor M3 is coupled to the power supply VDD, the second end of the third transistor M3 is coupled to the second end of the multi-level unit 310, and the control end of the third transistor M3 is coupled to the second bias Generator 340. The first end of the fourth electric crystal M4 is coupled to the second end of the multi-level unit 310, the second end of the fourth transistor M4 is coupled to the ground voltage GND, and the control end of the fourth transistor M4 receives a second control. Signal Ctrl2. The first bias generator 330 turns on the first transistor M1 with the first voltage plus the threshold voltage of the first transistor M1, the first control signal Ctrl1 turns off the second transistor M2, and the second bias generator 340 turns off the third The transistor M3, the second control signal Ctrl2 turns on the fourth transistor M4. As a result, the voltage of the first end of the multi-level cell 310 is clamped by the first transistor M1 at the first voltage of 201005742, and the second end of the multi-level cell 310 is coupled to the ground voltage GND, so that the bias circuit 320 can be It is determined whether the threshold voltage of the first half unit 312 is higher than a specific value. If the threshold voltage of the first half unit 312 is higher than a specific value, the first bias generator 330 turns off the first transistor, the first control signal Ctrl1 turns on the second transistor M2, and the second bias generator 340 turns high. The second voltage of the third voltage plus the threshold voltage of the third transistor M3 turns on the third transistor M3, and the second control signal Ctrl2 turns off the fourth transistor M4. As a result, the voltage of the second terminal of the multi-level cell 310 is clamped to the second voltage by the third transistor M3, and the first end of the multi-level cell 310 is coupled to the ground voltage GND, so that the bias circuit 320 can be The data stored in the second half unit 314 is read. If the threshold voltage of the first half unit 312 is lower than a specific value, the first bias generator 330 wears the first transistor M1, the first control signal Ctrl1 turns on the second transistor M2, and the second bias generator 340 The third voltage lower than the first voltage plus the threshold voltage of the third transistor M3 turns on the third transistor Q3, and the second control signal Ctrl2 turns off the fourth transistor M4. As a result, the voltage of the second terminal of the multi-level cell 310 is clamped to the third voltage by the third transistor M3, and the first terminal of the multi-level cell 310 is coupled to the ground voltage GND, so that the bias circuit 320 can be used. To read the data stored in the second half unit 314. The operation principle of the above-described memory 300 has been described in detail in the memory reading method disclosed in the embodiment of the present invention, and thus will not be repeated herein. The memory reading method and the memory disclosed in the above embodiments of the present invention determine whether the threshold voltage of the adjacent half unit of the target unit to be read is a high threshold voltage or a low threshold voltage. If the threshold voltage of the adjacent half cell is a high threshold voltage, the data stored in the target half cell is read with a high bit line voltage or a high word line voltage, thereby expanding the read interval and lowering the second bit effect. If the threshold voltage of the adjacent half cell is a low threshold voltage, the data stored in the target half cell is read at a low bit line voltage or a low word line voltage, thereby reducing read disturb. In conclusion, the present invention has been disclosed above in a preferred embodiment, and is not intended to limit the invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. Reference 12 201005742 [Simple description of the diagram] Figure 1A shows a schematic diagram of a conventional multi-level unit. The first is a distribution map of the threshold voltage distribution of the τρ multi-level cell. Figure 2 is a flow chart showing a memory reading method not according to a preferred embodiment of the present invention. Figure 3 is a partial circuit diagram of a memory in accordance with a preferred embodiment of the present invention. ® [Main component symbol description] 100, 310: multi-level cell 110 left half cell 120 right half cell 300 memory 312 half-cell 314 second half cell 320 bias circuit 330 first bias generator 340 second Bias generator 13