CN106328207B - Fascination method and apparatus for preventing data of nonvolatile storage from restoring - Google Patents

Fascination method and apparatus for preventing data of nonvolatile storage from restoring Download PDF

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CN106328207B
CN106328207B CN201610682381.5A CN201610682381A CN106328207B CN 106328207 B CN106328207 B CN 106328207B CN 201610682381 A CN201610682381 A CN 201610682381A CN 106328207 B CN106328207 B CN 106328207B
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data
programming
pressure pump
divider resistance
storage
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CN106328207A (en
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赵毅强
王佳
辛睿山
李跃辉
赵公元
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Tianjin University
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells

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Abstract

The present invention relates to the secure memory techniques of nonvolatile memory, make attacker be more difficult to guess the data of storage using the method for the corresponding relationship of analog threshold voltage and storing data to realize, that is, are effectively reduced the probability for restoring data.Fascination device of the present invention-for preventing data of nonvolatile storage from restoring, including high pressure pump circuit, R1, R2, one single-pole double throw control switches of divider resistance, control circuit, floating-gate device source;Divider resistance R1, R2 ground connection of the high pressure pump circuit through concatenating, high pressure pump circuit and divider resistance R1 tie point are 1 end, and tie point is 2 ends between divider resistance R1, R2;High-pressure pump circuit output high pressure size is Verase, and control circuit control switch connects 1 or 2 ends at random before erasing operation starts.Present invention is mainly applied to the secure storage occasions of nonvolatile memory.

Description

Fascination method and apparatus for preventing data of nonvolatile storage from restoring
Technical field
The present invention relates to the secure storages of nonvolatile memory, and in particular to prevents the data of nonvolatile memory extensive A kind of multiple fascination method, belongs to field of information security technology.
Background technique
With the fast development of information storage technology, solid state storage technologies are used widely.Solid-state memory can divide For volatile memory and nonvolatile memory.Compared with power-off loses the volatile memory of data, non-volatile memories Data therein [1] can still be maintained when power supply temporarily interrupts or the long period is in off-position in device.Currently, with non- Volatile memory is that the solid state storage technologies of core are widely used in the side such as computer, automobile, mobile device, communication and medical treatment Face.
However any memory is not perfectly safe.The application of nonvolatile memory is based on a kind of vacation If passing through erasing operation, the information in memory is irrecoverable.But it is actually really not so, in nonvolatile memory There are still data remanence problems.Nonvolatile memory is to store information in the form of a charge, and in write operation, charge is deposited Storage is in floating gate, in erasing operation, charge is allowed to flow out floating gate [2].It can not will be in write operation but execute erasing operation The electronics for flowing into floating gate is wiped clean completely, still has Partial charge to remain on floating gate, and is characterized in the devices such as threshold voltage ginseng On number [3].Even if the data in non-volatile are all logical one, attacker can still pass through the devices such as measurement threshold voltage The physical simulation amount of part parameter, the information by analyzing the relationship of threshold voltage and storing data, in recovering.
Early in 1996, by there is data remanence in research discovery semiconductor memory in Peter Gutmann [4], and the data remanence phenomenon in the storage unit to nonvolatile memory EEPROM in 2001 is further ground Study carefully, discovery programming time and unit condition etc. will affect the threshold voltage [5] of memory device.Data in nonvolatile memory It remains related with several factors, wherein utilize Silvaco TCAD simulating, verifying, non-volatile memory cells pass through write-once Operation, using an erasing operation, the case where obtained threshold voltage is with source voltage change in erasing operation, such as Fig. 1 institute Show.It can be obtained by Fig. 1, the threshold voltage in nonvolatile memory reduces, source voltage with the increase of source voltage in erasing operation Every to increase 1 volt, threshold voltage degradation is greater than 1 volt.
The manufacturing process of nonvolatile memory at present, operating voltage including the source voltage of erasing operation, and are write After the devices running parameters such as wiping time are determined by manufacturer, just it is fixed and invariable.Based on this, non-volatile deposit is attacked at present A kind of mode of data is the manufacturing process in known nonvolatile memory in reservoir, and operating voltage is grasped including erasing The source voltage of work, and on the basis of writing and wiping the devices running parameter such as time, the course of work of analog nonvolatile memory, and It compares with the threshold voltage value of the nonvolatile memory of actual measurement, to restore the data in nonvolatile memory.
Therefore, the present invention is based on the course of work of nonvolatile memory, keep the source voltage swing in erasing operation controlled In control circuit, a kind of fascination method for preventing the data of nonvolatile memory from restoring is proposed, so that effective protection is non-volatile Data in property memory.
[bibliography]
1. Zeng Ying, Wu Dong, Sun Lei etc.;Sophisticated semiconductor memory --- structure, design and application [M], Beijing: electronics work Industry publishing house, 2005,236-242.
2. Liu Yin, Su Yu, Zhu Jun;FLASH memory cell structure and functional study [J], Tsinghua University's journal (natural science Version), 1999,39 (S1): 91-94.
3.Skorobogatov S.Data remanence in flash memory devices[M] .Cryptographic Hardware and Embedded Systems–CHES 2005.Springer Berlin Heidelberg,2005:339-353。
4.Gutmann P.Secure deletion of data from magnetic and solid-state memory[C].Proceedings of the Sixth USENIX Security SympoSium,San Jose, CA.1996,14。
5.Gutmann P.Data remanence in semiconductor devices[C].Proceedings of the 10th conference on USENIX Security SympoSium-Volume 10.USENIX Association,2001:4-4。
Summary of the invention
In order to overcome the deficiencies of the prior art, the present invention is directed to the biasings in the erasing operation by making nonvolatile memory Voltage is not fixed, and then attacker is made to be more difficult to deposit using the method for the corresponding relationship of analog threshold voltage and storing data to guess The data of storage are effectively reduced the probability for restoring data.The technical solution adopted by the present invention is that for preventing non-volatile deposit The fascination device that memory data restores, including high pressure pump circuit, R1, R2, one single-pole double throw control switches of divider resistance, control Circuit, floating-gate device source and a ground terminal;Divider resistance R1, R2 ground connection of the high pressure pump circuit through concatenating, high-pressure pump electricity Road and divider resistance R1 tie point are 1 end, and tie point is 2 ends between divider resistance R1, R2;High-pressure pump circuit output high pressure size For Verase, control circuit control switch connects 1 or 2 ends at random before erasing operation starts, if control circuit control switch Connection 1, Vsource=Verase, if control circuit control switch connects 2, Vsource=R2/ (R1+R2) Verase.
Fascination method for preventing data of nonvolatile storage from restoring, step are point of the high pressure pump circuit through concatenating Piezoresistance R1, R2 ground connection, high pressure pump circuit and divider resistance R1 tie point are 1 end, and tie point is 2 between divider resistance R1, R2 End;There are two kinds of possibility for the source voltage for making in the erasing operation of nonvolatile memory, carried out in 1 storage unit 3 times with All possible programmed sequences of interior programming operation, wiping 1 indicates that the source voltage in erasing operation and erasing operation is Verase, storage Data be logic " 1 ";Wiping 2 indicates that the source voltage in erasing operation and erasing operation is R2/ (R1+R2) Verase, storage Data are logic " 1 ";Expression write operation is write, the data of storage are logic " 0 ";1 programming operation is carried out, programmed sequence Digit is 1, and all possible programmed sequence number is 3;2 programming operations are carried out, the digit of programmed sequence is 2 Position, all possible programmed sequence number are 8;3 programming operations are carried out, the digit of programmed sequence is 3, institute Possible programmed sequence number is 22, is programmed operation if be located in 1 storage unit, and programming number is j, then the The programmed sequence digit of j programming operation is j,
Nj=2*Nj-1+2*Nj-2, j >=3 (2)
Wherein, NjFor all possible programmed sequence numbers of jth time programming operation, Nj-1For the institute of (i-1)-th programming operation It is possible that sequence number, Nj-2All possible sequence numbers of the i-th -2 times programming operations, formula (2) are suitable for j and are greater than or equal to 3 The case where.
The features of the present invention and beneficial effect are:
Data remanence in nonvolatile memory is the major hidden danger for being potentially damaging to information security.Due to non-volatile Device parameters of memory during writing wiping immobilize, and attacker simulates non-on the basis of these known device parameters The course of work of easy property memory can restore non-easy according to the remaining device parameters of characterize data in nonvolatile memory The data stored in the property lost memory.The present invention makes the source voltage in the erasing operation of nonvolatile memory, and there are two kinds of possibility Property, from the point of view of erasing voltage, greatly increase programmed sequence, attacker measurement device parameters value a possibility that significantly Increase, so that the recovery probability for making attacker guess programmed sequence substantially reduces.
Detailed description of the invention:
Influence of the source voltage to threshold voltage in Fig. 1 erasing operation.
Fig. 2 non-volatile memory cells schematic diagram.
When source voltage in Fig. 3 erasing operation is fixed, programming operation is all within carrying out 3 times in 1 storage unit Possible programmed sequence.
The variable fascination method schematic diagram of source high pressure in a kind of erasing operation of Fig. 4.
Source voltage in Fig. 5 erasing operation there are two kinds it is possible when, behaviour is programmed within carrying out 3 times in 1 storage unit All possible programmed sequences made.
Specific embodiment
The basic structure of storing data is floating gate cell in nonvolatile memory, as shown in Figure 2.Non-volatile memories list Store charge in meta structure is floating gate.Floating gate is surrounded between control gate and substrate by insulating layer, the broad stopband of insulating layer A potential barrier is formd, electronics is prevented to flow in or out floating gate.The logical zero and logical one shape of non-volatile memory cells State can be distinguish according to the number of negative electrical charge on floating gate, and the number of negative electrical charge is determined by programming operation on floating gate.Programming behaviour Work is divided into write operation and erasing operation.Write operation utilizes channel hot electron injection effect, so that electronics is flowed into floating gate, on floating gate Negative electrical charge increase, the threshold voltage V of transistorthIt increases, is higher than added gate source voltage V when read operationGS, transistor cutoff, number According to saving as logical zero;Erasing operation utilizes F-N tunneling effect, and the high pressure that source is fixed, control gate ground connection, drain terminal is hanging, makes Electronics flows out floating gate, the melanoma cells on floating gate, the threshold voltage V of transistorthIt reduces, is lower than added grid source electricity when read operation Press VGS, transistor turns, data save as logical one.
By taking 1 storage unit as an example, if the data of the 1st storage are logic " 0 ", the data of the 2nd storage are logic " 1 ", it is based on 0.18umFlash EEPROM technique, using Silvaco TCAD software emulation, to non-volatile memory cells, i.e., Floating transistor first carries out write-once operation, then carries out an erasing operation, and wherein source voltage is 12V, obtained threshold value Voltage is 2.68V.Due to the manufacturing process of nonvolatile memory, operating voltage, including the source voltage of erasing operation, with And write the devices running parameters such as wiping time and immobilize, it is 12V that attacker, which can detecte the source voltage swing in erasing operation, and It is 2.68V by detection threshold value voltage, guessing the data stored originally is " 01 ".
By the data storage characteristics of nonvolatile memory NAND Flash, before carrying out write operation, it is necessary to wipe It removes.As shown in figure 3, carrying out 3 in 1 storage unit when being the source voltage fixation in the erasing operation of nonvolatile memory All possible programmed sequences of programming operation within secondary, wiping indicates erasing operation, and the data of storage are logic " 1 ";Expression is write to write Enter operation, the data of storage are logic " 0 ".As seen from the figure, 1 programming operation is carried out, the digit of programmed sequence is 1, All possible programmed sequence number is 2;2 programming operations are carried out, the digit of programmed sequence is 2, all possibility Programmed sequence number be 3;3 programming operations are carried out, the digit of programmed sequence is 3, all possible programming Column number is 5.It is programmed operation if be located in 1 storage unit, programming number is i, then the volume of i-th programming operation Program column digit is i,
Ni=Ni-3+2*Ni-2, i >=4 (1)
Wherein, NiFor all possible programmed sequence numbers of i-th programming operation, Ni-3For the institute of the i-th -3 times programming operations It is possible that sequence number, Ni-2All possible sequence numbers of the i-th -2 times programming operations, formula (1) are suitable for i and are greater than or equal to 4 The case where.
Assuming that the programming number i of 1 non-volatile memory cells known to attacker, all possible volumes known to formula (1) Program column number is Ni, the corresponding device parameters of each programmed sequence, all possible device ginsengs that attacker's measurement obtains Numerical value is NiA, then it is 1/N that attacker, which guesses the recovery probability of programmed sequence,i
Based on this, the present invention proposes a kind of fascination method that source high pressure is variable in erasing operation, such as Fig. 4, the fascination side Method schematic diagram includes high pressure pump circuit, R1, R2, one single-pole double throw control switches of divider resistance, control circuit, floating-gate device source End and a ground terminal.High-pressure pump circuit output high pressure size is Verase, and control circuit control switch is opened in erasing operation 1 or 2 ends of random connection before beginning, if control circuit control switch connection 1, Vsource=Verase, if control circuit control is opened Connection meets 2, Vsource=R2/ (R1+R2) Verase.Therefore, the source voltage in the erasing operation of nonvolatile memory exists Two kinds of possibility, i.e. Verase or R2/ (R1+R2) Verase.
As shown in figure 5, be source voltage in the erasing operation of nonvolatile memory there are two kinds it is possible when, deposited at 1 All possible programmed sequences of programming operation, wipe the source in 1 expression erasing operation and erasing operation within carrying out 3 times in storage unit Voltage is Verase, and the data of storage are logic " 1 ";Wiping 2 indicates that the source voltage in erasing operation and erasing operation is R2/ (R1 + R2) Verase, the data of storage are logic " 1 ";Expression write operation is write, the data of storage are logic " 0 ".Wherein, 1 He is wiped Wiping 2 indicates in addition to the source voltage swing in erasing operation is different, other running parameters of erasing operation, such as the erasing time etc. It is all identical.As seen from the figure, 1 programming operation is carried out, the digit of programmed sequence is 1, all possible programmed sequence Number is 3;2 programming operations are carried out, the digit of programmed sequence is 2, and all possible programmed sequence number is 8; 3 programming operations are carried out, the digit of programmed sequence is 3, and all possible programmed sequence number is 22.If be located at Operation is programmed in 1 storage unit, programming number is j, then the programmed sequence digit of jth time programming operation is j,
Nj=2*Nj-1+2*Nj-2, j >=3 (2)
Wherein, NjFor all possible programmed sequence numbers of jth time programming operation, Nj-1For -1 programming operation of jth All possibility sequence numbers, Nj-2All possible sequence numbers of -2 programming operations of jth, formula (2) are suitable for j and are greater than or wait In 3 the case where.
Assuming that the programming number j of 1 non-volatile memory cells known to attacker, all possible volumes known to formula (2) Program column number is Nj, the corresponding device parameters of each programmed sequence, all possible device ginsengs that attacker's measurement obtains Numerical value is NjA, then it is 1/N that attacker, which guesses the recovery probability of programmed sequence,j
Analytical formula (1) and formula (2), when the programming number of 1 non-volatile memory cells known to attacker the case where Under, one timing of programming number, i.e. i=j, there is always Ni-3< Nj-1, then there is always Ni-3< 2*Nj-1, and there is always Ni-2< Nj-2, that is, can be derived from that there is always Ni< Nj, 1/Ni> 1/Nj.In conclusion 1 non-volatile memory cells known to the attacker In the case where programming number, the programming timing of number one, variable using source high pressure in a kind of erasing operation proposed by the present invention Fascination method, the recovery probability for making attacker guess programmed sequence substantially reduce.
The present invention is fixed not based on the source voltage in erasing operation for the data remanence phenomenon in nonvolatile memory Become, proposes that a kind of fascination method that source high pressure is variable in erasing operation, this method obtain two kinds of voltages using electric resistance partial pressure, and Voltage value is randomly selected using control switch, to reach fascination effect, makes attacker according to device parameters to restore to deposit The probability of data substantially reduces in reservoir.

Claims (2)

1. a kind of fascination device for preventing data of nonvolatile storage from restoring, characterized in that including high pressure pump circuit, divide R1, R2, one single-pole double throw control switches of piezoresistance, control circuit, floating-gate device source and a ground terminal;High-pressure pump Divider resistance R1, R2 ground connection of the circuit through concatenating, high pressure pump circuit and divider resistance R1 tie point are 1 end, divider resistance R1, R2 Between tie point be 2 ends;High-pressure pump circuit output high pressure size is Verase, and control circuit control switch starts in erasing operation 1 or 2 ends are connected at random before, if control circuit control switch connection 1, Vsource=Verase, if control circuit control switch Connect 2, Vsource=R2/ (R1+R2) Verase.
2. a kind of fascination method for preventing data of nonvolatile storage from restoring, characterized in that non-volatile for preventing The fascination method that memory data restores, step are divider resistance R1, R2 ground connection of the high pressure pump circuit through concatenating, high-pressure pump electricity Road and divider resistance R1 tie point are 1 end, and tie point is 2 ends between divider resistance R1, R2;Make the erasing of nonvolatile memory There are two kinds of possibility for source voltage in operation, all possible programmings of programming operation within carrying out 3 times in 1 storage unit Column, wiping 1 indicates that the source voltage in erasing operation and erasing operation is Verase, and the data of storage are logic " 1 ";Wiping 2 indicates to wipe Except the source voltage in operation and erasing operation is R2/ (R1+R2) Verase, the data of storage are logic " 1 ";Write expression write-in behaviour Make, the data of storage are logic " 0 ";1 programming operation is carried out, the digit of programmed sequence is 1, all possible programming Sequence number is 3;2 programming operations are carried out, the digit of programmed sequence is 2, all possible programmed sequence number It is 8;3 programming operations are carried out, the digit of programmed sequence is 3, and all possible programmed sequence number is 22, such as Fruit, which is located in 1 storage unit, is programmed operation, and programming number is j, then the programmed sequence digit of jth time programming operation is j Position,
Nj=2*Nj-1+2*Nj-2, j >=3 (2)
Wherein, NjFor all possible programmed sequence numbers of jth time programming operation, Nj-1All for -1 programming operation of jth can Energy sequence number, Nj-2All possible sequence numbers of -2 programming operations of jth, formula (2) are suitable for the feelings that j is greater than or equal to 3 Condition.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1171600A (en) * 1996-07-23 1998-01-28 Lg半导体株式会社 Nonvolatile memory cell and method for programming same
JPH11260086A (en) * 1998-03-12 1999-09-24 Sanyo Electric Co Ltd Nonvolatile semiconductor memory
CN101101791A (en) * 2006-07-07 2008-01-09 尔必达存储器株式会社 Non-volatile memory and control method thereof
CN101636791A (en) * 2007-03-12 2010-01-27 国际商业机器公司 Apparatus and method for integrating nonvolatile memory capability within sram devices
CN103700399A (en) * 2014-01-07 2014-04-02 上海华虹宏力半导体制造有限公司 Flash memory and corresponding programming method, reading method and erasing method
CN103871471A (en) * 2012-12-10 2014-06-18 精工电子有限公司 Non-volatile memory circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1171600A (en) * 1996-07-23 1998-01-28 Lg半导体株式会社 Nonvolatile memory cell and method for programming same
JPH11260086A (en) * 1998-03-12 1999-09-24 Sanyo Electric Co Ltd Nonvolatile semiconductor memory
CN101101791A (en) * 2006-07-07 2008-01-09 尔必达存储器株式会社 Non-volatile memory and control method thereof
CN101636791A (en) * 2007-03-12 2010-01-27 国际商业机器公司 Apparatus and method for integrating nonvolatile memory capability within sram devices
CN103871471A (en) * 2012-12-10 2014-06-18 精工电子有限公司 Non-volatile memory circuit
CN103700399A (en) * 2014-01-07 2014-04-02 上海华虹宏力半导体制造有限公司 Flash memory and corresponding programming method, reading method and erasing method

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