CN106328207A - Confusing method and device for preventing data recovery of nonvolatile memory - Google Patents

Confusing method and device for preventing data recovery of nonvolatile memory Download PDF

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Publication number
CN106328207A
CN106328207A CN201610682381.5A CN201610682381A CN106328207A CN 106328207 A CN106328207 A CN 106328207A CN 201610682381 A CN201610682381 A CN 201610682381A CN 106328207 A CN106328207 A CN 106328207A
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programming
data
programmed sequence
nonvolatile memory
pump circuit
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CN201610682381.5A
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CN106328207B (en
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赵毅强
王佳
辛睿山
李跃辉
赵公元
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Tianjin University
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Tianjin University
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells

Abstract

The invention discloses a security storage technology of a nonvolatile memory. An attacker can more hardly guess saved data by means of the correspondence of analog threshold voltage and the saved data, and therefore the probability of data recovery is effectively reduced. A confusing device for preventing data recovery of the nonvolatile memory comprises a high-voltage pump circuit, a divider resistor R1, a divider resistor R2, a single-pole double-throw control switch, a control circuit and a floating-gate device source end. The high-voltage pump circuit is grounded through the divider resistor R1 and the divider resistor R2 which are connected in series. The joint of the high-voltage pump circuit and the divider resistor R1 is the first end, and the joint of the divider resistor R1 and the divider resistor R2 is the end 2. The magnitude of the output high voltage of the high-voltage pump circuit is Verase. A control circuit control switch is alternately connected with the end 1 or 2 before wiping operation starts. The device is mainly applied to the security storage occasions of the nonvolatile memory.

Description

For the fascination method and apparatus preventing data of nonvolatile storage from recovering
Technical field
The present invention relates to the safety storage of nonvolatile memory, the data being specifically related to prevent nonvolatile memory are extensive A kind of multiple fascination method, belongs to field of information security technology.
Background technology
Along with the fast development of information storage technology, solid state storage technologies is used widely.Solid-state memory can divide For volatile memory and nonvolatile memory.Compared with the volatile memory that data are i.e. lost in power-off, non-volatile memories Device, when power supply temporarily interrupts or the long period is in off-position, is maintained to data therein [1].At present, with non- Volatile memory is that the solid state storage technologies of core is widely used in the sides such as computer, automobile, mobile device, communication and medical treatment Face.
But any one memorizer is not perfectly safe.The application of nonvolatile memory is based on a kind of false If i.e. through erasing operation, the information in memorizer is irrecoverable.But, the most really not so, in nonvolatile memory Still suffer from data remanence problem.Nonvolatile memory is the information that stores in the form of a charge, when write operation, is deposited by electric charge Storage, in floating boom, when erasing operation, allows electric charge flow out floating boom [2].But being carried out wiping operation can not be by write operation The electronics flowing into floating boom is wiped clean completely, still has Partial charge to remain on floating boom, and is characterized in the device ginsengs such as threshold voltage On number [3].Even if the data in non-volatile are all logical one, assailant still can be by measuring the devices such as threshold voltage The physical simulation amount of part parameter, by analyzing threshold voltage and the relation of storage data, the information in recovering.
As far back as 1996, Peter Gutmann found to there is data remanence problem in semiconductor memory by research [4], the data remanence phenomenon and in the calendar year 2001 memory element to nonvolatile memory EEPROM has carried out grinding further Study carefully, find that programming time and unit condition etc. can affect the threshold voltage [5] of memory device.Data in nonvolatile memory Remaining relevant with several factors, wherein, utilize Silvaco TCAD simulating, verifying, non-volatile memory cells is through write-once Operation, then through once wiping operation, the threshold voltage obtained is with the situation of the source change in voltage in erasing operation, such as Fig. 1 institute Show.Can be obtained by Fig. 1, the threshold voltage in nonvolatile memory reduces, source voltage with the increase wiping source voltage in operation Often increasing 1 volt, threshold voltage degradation is more than 1 volt.
The manufacturing process of nonvolatile memory at present, running voltage, including the source voltage of erasing operation, and write After the device running parameters such as wiping time are determined by manufacturer, it is simply that changeless.Based on this, attack non-volatile depositing at present In reservoir, a kind of mode of data is the manufacturing process at known nonvolatile memory, running voltage, including erasing behaviour The source voltage made, and on the basis of writing the device running parameters such as wiping time, the work process of analog nonvolatile memorizer, and Compare with the threshold voltage value of the nonvolatile memory of reality measurement, thus recover the data in nonvolatile memory.
Therefore, present invention work process based on nonvolatile memory, make the source voltage swing in erasing operation controlled In control circuit, propose a kind of fascination method preventing the data of nonvolatile memory from recovering, thus effectively protect non-volatile Data in property memorizer.
[list of references]
1. Zeng Ying, Wu Dong, Sun Lei etc.;Sophisticated semiconductor memory construction, design and apply [M], Beijing: electronics work Industry publishing house, 2005,236-242.
2. Liu Yin, Su Yu, Zhu Jun;FLASH memory cell structure and functional study [J], Tsing-Hua University's journal (natural science Version), 1999,39 (S1): 91-94.
3.Skorobogatov S.Data remanence in flash memory devices[M] .Cryptographic Hardware and Embedded Systems–CHES 2005.Springer Berlin Heidelberg,2005:339-353。
4.Gutmann P.Secure deletion of data from magnetic and solid-state memory[C].Proceedings of the Sixth USENIX Security SympoSium,San Jose, CA.1996,14。
5.Gutmann P.Data remanence in semiconductor devices[C].Proceedings of the 10th conference on USENIX Security SympoSium-Volume 10.USENIX Association,2001:4-4。
Summary of the invention
For overcoming the deficiencies in the prior art, it is contemplated that by the biasing in making the erasing of nonvolatile memory operate Voltage is not fixed, and then makes assailant be more difficult to use the method for corresponding relation of analog threshold voltage and storage data to guess to deposit The data of storage, are i.e. effectively reduced the probability recovering data.The technical solution used in the present invention is, is used for preventing non-volatile depositing The fascination device that memory data recovers, including high-pressure pump circuit, divider resistance R1, R2, one single-pole double throw controls switch, controls Circuit, floating-gate device source, and an earth terminal;High-pressure pump circuit is through divider resistance R1, R2 ground connection of concatenation, high-pressure pump electricity Road and divider resistance R1 junction point are 1 end, and between divider resistance R1, R2, junction point is 2 ends;High-pressure pump circuit output high pressure size For Verase, control circuit controls switch random connection 1 or 2 ends before erasing operation starts, if control circuit controls switch Connect 1, Vsource=Verase, if control circuit controls switch connection 2, Vsource=R2/ (R1+R2) Verase.
For the fascination method preventing data of nonvolatile storage from recovering, step is, high-pressure pump circuit is through dividing of concatenating Piezoresistance R1, R2 ground connection, high-pressure pump circuit and divider resistance R1 junction point are 1 end, and between divider resistance R1, R2, junction point is 2 End;Make the source voltage in the erasing operation of nonvolatile memory exist two kinds may, carry out in 1 memory element 3 times with Institute's likely programmed sequence of interior programming operation, the source voltage wiped in 1 expression erasing operation and erasing operation is Verase, storage Data be logic " 1 ";The source voltage wiped in 2 expression erasing operations and erasing operation is R2/ (R1+R2) Verase, storage Data be logic " 1 ";Write expression write operation, the data of storage be logic " 0 ";Carry out 1 programming operation, its programmed sequence Figure place is 1, and its all possible programmed sequence number is 3;Carrying out 2 programming operations, the figure place of its programmed sequence is 2 Position, its all possible programmed sequence number is 8;Carrying out 3 programming operations, the figure place of its programmed sequence is 3, and it owns Possible programmed sequence number is 22, is programmed operation if be located in 1 memory element, and programming number of times is j, then jth The programmed sequence figure place of secondary programming operation is j position,
Nj=2*Nj-1+2*Nj-2, j >=3 (2)
Wherein, NjInstitute likely programmed sequence number, N for jth time programming operationj-1It it is the institute of the i-th-1 time programming operation Likely sequence number, Nj-2Institute's likely sequence number of the i-th-2 times programming operations, formula (2) is applicable to j more than or equal to 3 Situation.
The feature of the present invention and providing the benefit that:
Data remanence in nonvolatile memory is the major hidden danger being potentially damaging to information security.Due to non-volatile Memorizer device parameters during writing wiping immobilizes, and assailant, on the basis of these device parameters known, simulates non- The easily work process of property memorizer, according to nonvolatile memory characterizes the device parameters of data remanence, can recover non-easily The data of storage in the property lost memorizer.The present invention makes the source voltage in the erasing operation of nonvolatile memory have two kinds may Property, from the point of view of erasing voltage, make programmed sequence be greatly increased, the probability of the device parameters value that assailant measures is significantly Increase, so that the recovery probability that assailant guesses programmed sequence is substantially reduced.
Accompanying drawing illustrates:
Fig. 1 wipes the impact on threshold voltage of the source voltage in operation.
Fig. 2 non-volatile memory cells schematic diagram.
Fig. 3 wipes the source voltage in operation when fixing, and carries out all of programming operation within 3 times in 1 memory element Possible programmed sequence.
Fig. 4 is a kind of wipes the fascination method schematic diagram that source high pressure in operation is variable.
When Fig. 5 wipes the source voltage two kinds of possibilities of existence in operation, programming behaviour within carrying out 3 times in 1 memory element The institute's likely programmed sequence made.
Detailed description of the invention
The basic structure storing data in nonvolatile memory is floating gate cell, as shown in Figure 2.Non-volatile memories list Store electric charge in meta structure is floating boom.Floating boom, between control gate and substrate, is surrounded by insulating barrier, the broad stopband of insulating barrier Define a potential barrier, prevent electronics to flow in or out floating boom.The logical zero of non-volatile memory cells and logical one shape State can be distinguish between according to the number of negative charge on floating boom, and on floating boom, the number of negative charge is determined by programming operation.Programming behaviour Make to be divided into write operation and erasing operation.Write operation utilizes channel hot electron injection effect, makes electronics flow into floating boom, on floating boom Negative charge increase, the threshold voltage V of transistorthRaise, the added gate source voltage V higher than during read operationGS, transistor cutoff, number According to saving as logical zero;Erasing operation utilizes F-N tunneling effect, and the high pressure that source is fixed, control gate ground connection, drain terminal is unsettled, makes Electronics flows out floating boom, the melanoma cells on floating boom, the threshold voltage V of transistorthReduce, the added grid source electricity less than during read operation Pressure VGS, transistor turns, data save as logical one.
As a example by 1 memory element, if the 1st time storage data be logic " 0 ", the 2nd time storage data be logic " 1 ", based on 0.18umFlash EEPROM technique, utilize Silvaco TCAD software emulation, to non-volatile memory cells, i.e. Floating transistor, first carries out write-once operation, more once wipes operation, and wherein source voltage is 12V, obtained threshold value Voltage is 2.68V.Due to the manufacturing process of nonvolatile memory, running voltage, including the source voltage of erasing operation, with And write the device running parameters such as wiping time and immobilize, the source voltage swing that assailant can detect in erasing operation is 12V, and Being 2.68V by detection threshold threshold voltage, guessing the data originally stored is " 01 ".
By the data storage characteristics of nonvolatile memory NAND Flash, before carrying out write operation, it is necessary to wipe Remove.As it is shown on figure 3, be the source voltage in the erasing operation of nonvolatile memory when fixing, 1 memory element carries out 3 Within secondary, institute's likely programmed sequence of programming operation, wipes and represents erasing operation, the data of storage be logic " 1 ";Write expression to write Enter operation, the data of storage be logic " 0 ".As seen from the figure, carrying out 1 programming operation, the figure place of its programmed sequence is 1, its All possible programmed sequence number is 2;Carrying out 2 programming operations, the figure place of its programmed sequence is 2, and its institute is likely Programmed sequence number be 3;Carrying out 3 programming operations, the figure place of its programmed sequence is 3, its all possible programming Row number is 5.Being programmed operation if be located in 1 memory element, programming number of times is i, then the volume of i & lt programming operation Program row figure place is i position,
Ni=Ni-3+2*Ni-2, i >=4 (1)
Wherein, NiInstitute likely programmed sequence number, N for i & lt programming operationi-3It it is the institute of the i-th-3 times programming operations Likely sequence number, Ni-2Institute's likely sequence number of the i-th-2 times programming operations, formula (1) is applicable to i more than or equal to 4 Situation.
Assume the programming number of times i of known 1 non-volatile memory cells of assailant, formula (1) understand and likely compile Program row number is Ni, the corresponding device parameters of each programmed sequence, institute's likely device ginseng that assailant's measurement obtains Numerical value is NiIndividual, then assailant guesses the recovery probability of programmed sequence is 1/Ni
Based on this, the present invention proposes a kind of to wipe the fascination method that source high pressure in operation is variable, such as Fig. 4, this fascination side Method schematic diagram includes high-pressure pump circuit, and divider resistance R1, R2, one single-pole double throw controls switch, control circuit, floating-gate device source End, and an earth terminal.High-pressure pump circuit output high pressure size is Verase, and control circuit controls switch and opens in erasing operation Random connection 1 or 2 ends before beginning, if control circuit controls switch connection 1, Vsource=Verase, if control circuit controls to open Close connection 2, Vsource=R2/ (R1+R2) Verase.Therefore, the source voltage in the erasing operation of nonvolatile memory exists Two kinds possible, i.e. Verase or R2/ (R1+R2) Verase.
During as it is shown in figure 5, be the source voltage two kinds of possibilities of existence in the erasing operation of nonvolatile memory, deposit at 1 Storage unit carries out institute's likely programmed sequence of programming operation within 3 times, wipes the source in 1 expression erasing operation and erasing operation Voltage is Verase, the data of storage be logic " 1 ";The source voltage wiped in 2 expression erasing operations and erasing operation is R2/ (R1+ R2) Verase, the data of storage be logic " 1 ";Write expression write operation, the data of storage be logic " 0 ".Wherein, wipe 1 and wipe 2 represent that, in addition to the source voltage swing difference in erasing operation, other running parameter of erasing operation, such as the erasing time etc. are all Identical.As seen from the figure, carrying out 1 programming operation, the figure place of its programmed sequence is 1, its all possible programmed sequence number It it is 3;Carrying out 2 programming operations, the figure place of its programmed sequence is 2, and its all possible programmed sequence number is 8;Enter 3 programming operations of row, the figure place of its programmed sequence is 3, and its all possible programmed sequence number is 22.If being located at 1 Being programmed operation in individual memory element, programming number of times is j, then the programmed sequence figure place of jth time programming operation is j position,
Nj=2*Nj-1+2*Nj-2, j >=3 (2)
Wherein, NjInstitute likely programmed sequence number, N for jth time programming operationj-1It it is the institute of the i-th-1 time programming operation Likely sequence number, Nj-2Institute's likely sequence number of the i-th-2 times programming operations, formula (2) is applicable to j more than or equal to 3 Situation.
Assume the programming number of times j of known 1 non-volatile memory cells of assailant, formula (2) understand and likely compile Program row number is Nj, the corresponding device parameters of each programmed sequence, institute's likely device ginseng that assailant's measurement obtains Numerical value is NjIndividual, then assailant guesses the recovery probability of programmed sequence is 1/Nj
Analytical formula (1) and formula (2), when the situation of the programming number of times of known 1 non-volatile memory cells of assailant Under, programming number of times one timing, i.e. i=j, always there is Ni-3< Nj-1, the most always there is Ni-3< 2*Nj-1, and always there is Ni-2< Nj-2, i.e. can be derived from and always there is Ni< Nj, 1/Ni> 1/Nj.In sum, when known 1 non-volatile memory cells of assailant In the case of programming number of times, programming number of times one timing, use that the present invention proposes a kind of to wipe source high pressure in operation variable Fascination method, the recovery probability making assailant guess programmed sequence is substantially reduced.
The present invention is directed to the data remanence phenomenon in nonvolatile memory, fixing not based on the source voltage in erasing operation Becoming, propose a kind of to wipe the fascination method that source high pressure in operation is variable, the method uses electric resistance partial pressure to obtain two kinds of voltages, and Use to control to switch and magnitude of voltage is randomly selected, to reach to confuse effect, make assailant recover to deposit according to device parameters In reservoir, the probability of data is substantially reduced.

Claims (2)

1., for the fascination device preventing data of nonvolatile storage from recovering, it is characterized in that, including high-pressure pump circuit, point Piezoresistance R1, R2, one single-pole double throw controls switch, control circuit, floating-gate device source, and an earth terminal;High-pressure pump Circuit is through divider resistance R1, R2 ground connection of concatenation, and high-pressure pump circuit and divider resistance R1 junction point are 1 end, divider resistance R1, R2 Between junction point be 2 ends;High-pressure pump circuit output high pressure size is Verase, and control circuit controls switch and starts in erasing operation Connect 1 or 2 ends the most at random, if control circuit controls switch connection 1, Vsource=Verase, if control circuit controls switch Connect 2, Vsource=R2/ (R1+R2) Verase.
2. for preventing the fascination method that data of nonvolatile storage recovers, it is characterized in that, be used for preventing non-volatile The fascination method that memory data recovers, step is, high-pressure pump circuit is through divider resistance R1, R2 ground connection of concatenation, high-pressure pump electricity Road and divider resistance R1 junction point are 1 end, and between divider resistance R1, R2, junction point is 2 ends;Make the erasing of nonvolatile memory Source voltage in operation exist two kinds may, 1 memory element carries out likely programming of programming operation within 3 times Row, wipe 1 expression erasing operation and erasing operation in source voltage be Verase, the data of storage be logic " 1 ";Wipe 2 expressions to wipe Division operation and erasing operation in source voltage be R2/ (R1+R2) Verase, the data of storage be logic " 1 ";Write expression write behaviour Make, the data of storage be logic " 0 ";Carrying out 1 programming operation, the figure place of its programmed sequence is 1, its all possible programming Sequence number is 3;Carrying out 2 programming operations, the figure place of its programmed sequence is 2, its all possible programmed sequence number It it is 8;Carrying out 3 programming operations, the figure place of its programmed sequence is 3, and its all possible programmed sequence number is 22, as Fruit is located in 1 memory element and is programmed operation, and programming number of times is j, then the programmed sequence figure place of jth time programming operation is j Position,
Nj=2*Nj-1+2*Nj-2, j >=3 (2)
Wherein, NjInstitute likely programmed sequence number, N for jth time programming operationj-1It is that all of the i-th-1 time programming operation can Energy sequence number, Nj-2Institute's likely sequence number of the i-th-2 times programming operations, formula (2) is applicable to the j feelings more than or equal to 3 Condition.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110660446A (en) * 2019-09-10 2020-01-07 电子科技大学 Device for evaluating data residue of nonvolatile memory in single chip microcomputer

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1171600A (en) * 1996-07-23 1998-01-28 Lg半导体株式会社 Nonvolatile memory cell and method for programming same
JPH11260086A (en) * 1998-03-12 1999-09-24 Sanyo Electric Co Ltd Nonvolatile semiconductor memory
CN101101791A (en) * 2006-07-07 2008-01-09 尔必达存储器株式会社 Non-volatile memory and control method thereof
CN101636791A (en) * 2007-03-12 2010-01-27 国际商业机器公司 Apparatus and method for integrating nonvolatile memory capability within sram devices
CN103700399A (en) * 2014-01-07 2014-04-02 上海华虹宏力半导体制造有限公司 Flash memory and corresponding programming method, reading method and erasing method
CN103871471A (en) * 2012-12-10 2014-06-18 精工电子有限公司 Non-volatile memory circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1171600A (en) * 1996-07-23 1998-01-28 Lg半导体株式会社 Nonvolatile memory cell and method for programming same
JPH11260086A (en) * 1998-03-12 1999-09-24 Sanyo Electric Co Ltd Nonvolatile semiconductor memory
CN101101791A (en) * 2006-07-07 2008-01-09 尔必达存储器株式会社 Non-volatile memory and control method thereof
CN101636791A (en) * 2007-03-12 2010-01-27 国际商业机器公司 Apparatus and method for integrating nonvolatile memory capability within sram devices
CN103871471A (en) * 2012-12-10 2014-06-18 精工电子有限公司 Non-volatile memory circuit
CN103700399A (en) * 2014-01-07 2014-04-02 上海华虹宏力半导体制造有限公司 Flash memory and corresponding programming method, reading method and erasing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110660446A (en) * 2019-09-10 2020-01-07 电子科技大学 Device for evaluating data residue of nonvolatile memory in single chip microcomputer
CN110660446B (en) * 2019-09-10 2021-03-30 电子科技大学 Device for evaluating data residue of nonvolatile memory in single chip microcomputer

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