CN103700399A - Flash memory and corresponding programming method, reading method and erasing method - Google Patents
Flash memory and corresponding programming method, reading method and erasing method Download PDFInfo
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- CN103700399A CN103700399A CN201410006647.5A CN201410006647A CN103700399A CN 103700399 A CN103700399 A CN 103700399A CN 201410006647 A CN201410006647 A CN 201410006647A CN 103700399 A CN103700399 A CN 103700399A
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Abstract
The invention discloses a flash memory and corresponding programming method, reading method and erasing method. A storage unit of the flash memory is a split-gate flash memory, and the word lines of the storage unit are connected with a pre-charging unit; when in pre-charging of the flash memory, the voltage on each bit line is pre-charged and maintained at the pre-charging voltage. Since the pre-charging unit can pre-charge the voltage on each bit line and maintain the pre-charging voltage, other bit lines not involved in programming operation do not experience voltage drop due to the existence of leak current; therefore, except the storage unit to be programmed, no current flows between the source region and drain region of the other storage unit, and misoperation on the storage unit not involved in programming operation in the programming process can be effectively prevented.
Description
Technical field
The present invention relates to semiconductor technology, particularly a kind of flash memory and corresponding programmed method, read method and method for deleting.
Background technology
Storer is for storing digital information.There are at present many eurypalynous storeies, such as RAM(random access memory), DRAM(dynamic RAM), ROM(ROM (read-only memory)), EPROM(Erasable Programmable Read Only Memory EPROM), Flash(flash memory) etc.Wherein, flash memory has become the main flow of non-volatile semiconductor storage technology.
Please refer to Fig. 1, is the structural representation of existing a kind of flash memory, and described flash memory comprises: several are the storage unit 10 that matrix is arranged; Described storage unit 10 comprises spaced the first storage bit unit 11 and the second storage bit unit 12, in described the first storage bit unit 11, there is the first floating boom and the first control gate, in described the second storage bit unit 12, there is the second floating boom and the second control gate, word line 20 between described the first storage bit unit 11 and the second storage bit unit 12, be positioned at source region and the drain region in described the first storage bit unit 11 and the second storage bit unit 12 outsides, the bit line 30 being electrically connected to described source region and drain region; The corresponding word line 20 of each line storage unit 10 and the first control gate select lines 40 and the second control gate select lines 50, the corresponding bit lines 30 of each array storage unit 10.
But the flash memory with described storage unit is to the first storage bit unit 11 and the second storage bit unit 12 is programmed, read or during erase operation, can produce harmful effect to another storage bit unit, produces maloperation.
Summary of the invention
The problem that the present invention solves is to provide a kind of flash memory and corresponding programmed method, read method and method for deleting, when avoiding programming, reading and wipe, can produce harmful effect to consecutive storage unit.
For addressing the above problem, the invention provides a kind of flash memory, comprising: memory cell array, word line gating unit, bit line gating unit, control gate gating unit and precharge unit, described memory cell array comprises that several are the storage unit that matrix is arranged, described storage unit is gate-division type flash memory unit, described gate-division type flash memory unit comprises and is positioned at spaced the first storage bit unit of semiconductor substrate surface and the second storage bit unit, in described the first storage bit unit, there is the first floating boom and the first control gate, in described the second storage bit unit, there is the second floating boom and the second control gate, fill the word line of groove between full described the first storage bit unit and the second storage bit unit, be positioned at source region and the drain region in described the first storage bit unit and the second storage bit unit outside, the bit line being electrically connected to described source region and drain region, described word line gating unit is connected with the word line of described storage unit, utilizes described word line gating unit select and control corresponding storage bit unit and read, programme, wipe processing, described bit line gating unit is connected with the bit line of described storage unit, utilizes described bit line gating unit select and control corresponding storage bit unit and read, programme, wipe processing, described control gate gating unit is connected with the second control gate with the first control gate of described storage unit, utilizes described control gate gating unit select and control corresponding storage bit unit and read, programme, wipe processing, described precharge unit is connected with the bit line of described storage unit, and described flash memory is when carrying out precharge, by the voltage preliminary filling on each bit lines and maintain pre-charge voltage.
Optionally, described precharge unit comprises voltage regulation unit, voltage bias unit and adjust one to one transistor with each bit lines, described adjustment transistor comprises respectively and source electrode, the first end that drain electrode is connected, the second end and the control end being connected with grid, the transistorized first end of described adjustment is connected with bit line, transistorized the second end of described adjustment is connected with voltage regulation unit, the transistorized control end of described adjustment is connected with voltage bias unit, pre-charge voltage while utilizing voltage regulation unit to stablize precharge, utilize voltage bias unit controls to adjust transistor pairs of bit line and carry out precharge.
Optionally, described voltage regulation unit comprises mirror image unit and current source, described mirror image unit comprises input PMOS transistor and a plurality of and adjustment transistor mirror image PMOS transistor one to one, the transistorized source electrode of described input PMOS is connected with working power, after the transistorized drain and gate of described input PMOS is connected, is connected with current source; The transistorized source electrode of described a plurality of mirror image PMOS is connected with working power, the transistorized grid of described a plurality of mirror image PMOS is connected with the transistorized grid of input PMOS, and the transistorized drain electrode of described mirror image PMOS is connected with corresponding transistorized the second end of adjustment.
Optionally, described voltage bias unit comprises a PMOS transistor, the first nmos pass transistor, comparer and voltage divider, and the input end in the same way of described comparer connects the output terminal of described voltage divider, and the reverse input end of described comparer is used for accepting reference voltage; The transistorized source electrode of a described PMOS is connected with working power, the transistorized grid of a described PMOS is connected with the output terminal of comparer, after the transistorized drain electrode of a described PMOS is connected with drain electrode, the grid of the first nmos pass transistor, as the output terminal of described voltage bias unit, the source electrode of described the first nmos pass transistor couples mutually with the input end of voltage divider.
The present invention also provides a kind of programmed method of flash memory, comprising: utilize precharge unit that each bit lines is precharged to pre-charge voltage; Utilize bit line gating unit that the bit line of target storage bit unit one side to be programmed is charged to the first program voltage, at least two bit lines of target storage bit unit opposite side to be programmed are charged to the second program voltage, and described the first program voltage is greater than the second program voltage; Utilize word line gating unit to apply the 3rd program voltage at word line corresponding to target storage bit unit to be programmed, and the voltage difference between the 3rd program voltage and the second program voltage is greater than threshold voltage; Utilize control gate gating unit to apply the 4th program voltage at control gate corresponding to target storage bit unit to be programmed, the electronics of the corresponding channel region of target storage bit unit to be programmed is pulled in floating boom, thereby realizes programming.
Optionally, described pre-charge voltage is 2.5V, and the first program voltage is 5.5V, and the second program voltage is 0.1V, and the 3rd program voltage is 1.5V, and the 4th program voltage is 8V.
The present invention also provides a kind of read method of flash memory, comprising: utilize bit line gating unit by the bit line ground connection of target storage bit unit one side to be read, at least two bit lines of target storage bit unit opposite side to be read are charged to first and read voltage; Utilize word line gating unit to apply second at word line corresponding to target storage bit unit to be read and read voltage; Utilize control gate gating unit by control gate ground connection corresponding to target storage bit unit to be read, the control gate corresponding to storage bit unit of the corresponding word line of target storage bit unit to be read opposite side applied to third reading power taking and press, the described first voltage difference reading between voltage and third reading power taking pressure is greater than threshold voltage; By recording the size of current of the channel region of described target storage bit unit, obtain the data of target storage bit unit storage to be read.
Optionally, first to read voltage be 1V, and second to read voltage be 4.5V, and third reading power taking is pressed as 4.5V.
The present invention also provides a kind of method for deleting of flash memory, comprising: by the floating sky of the voltage of each bit lines or ground connection; Utilize word line gating unit to apply the first erasing voltage at word line corresponding to target storage bit unit to be erased; Utilize control gate gating unit to apply the second erasing voltage at control gate corresponding to target storage bit unit to be erased, described the first erasing voltage is greater than the second erasing voltage, make the electronics in storage bit unit floating boom to be erased be pulled to word line, thereby realize, wipe.
Optionally, the first erasing voltage is 8.5V, and the second erasing voltage is-7V.
Compared with prior art, technical scheme of the present invention has the following advantages:
The storage unit of described flash memory is gate-division type flash memory, and the word line of described storage unit is connected with precharge unit, when flash memory carries out precharge, by the voltage preliminary filling on each bit lines and maintain pre-charge voltage.Because described precharge unit can and maintain pre-charge voltage by the voltage preliminary filling on each bit lines, other bit lines that do not relate to programming operation can not cause because of the existence of leakage current voltage drop, therefore except storage unit to be programmed, between other storage unit source region and drain region, do not have electric current to flow through, therefore can effectively prevent to not relating to the storage unit of programming operation, carrying out maloperation in programming process.
Accompanying drawing explanation
Fig. 1 is the structural representation of the flash memory of prior art;
Fig. 2～Fig. 6 is the structural representation of the flash memory of the embodiment of the present invention;
Fig. 7 and Fig. 8 be flash memory programming, read the working state figure with erase operation.
Embodiment
Due to utilize the formed flash memory of existing storage unit in programming, read or easily produce during erase operation maloperation, therefore, the embodiment of the present invention provides a kind of flash memory and corresponding programmed method, read method and method for deleting, the storage unit of described flash memory is gate-division type flash memory, and the word line of described storage unit is connected with precharge unit, when flash memory carries out precharge, by the voltage preliminary filling on each bit lines and maintain pre-charge voltage.Because described precharge unit can and maintain pre-charge voltage by the voltage preliminary filling on each bit lines, other bit lines that do not relate to programming operation can not cause because of the existence of leakage current voltage drop, therefore except storage unit to be programmed, between other storage unit source region and drain region, do not have electric current to flow through, therefore can effectively prevent to not relating to the storage unit of programming operation, carrying out maloperation in programming process.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
Please refer to Fig. 2, the structural representation for the flash memory of the embodiment of the present invention, comprising:
Described memory cell array 100 comprises that several are the storage unit 110 that matrix is arranged, and described storage unit 110 is gate-division type flash memory unit;
Described word line gating unit 200 is connected with the word line 140 of described storage unit 110, utilizes described word line gating unit 200 select and control corresponding storage unit and read, programme, wipe processing;
Described bit line gating unit 300 is connected with the bit line 170 of described storage unit 100, utilizes described word line gating unit 300 select and control corresponding storage unit and read, programme, wipe processing;
Described control gate gating unit 400 is connected with the second control gate 164 with the first control gate 154 of described storage unit 100, utilizes described control gate gating unit 400 select and control corresponding storage unit and read, programme, wipe processing;
Described precharge unit 500 is connected with the bit line 170 of described storage unit 110, when flash memory is carried out to precharge, by the voltage preliminary filling on each bit lines 170 and maintain pre-charge voltage.
In the present embodiment, described storage unit 110 is gate-division type flash memory unit, the concrete structure of described gate-division type flash memory unit please refer to Fig. 3, comprise: Semiconductor substrate 111, be positioned at the first storage bit unit 150 and the second storage bit unit 160 that described Semiconductor substrate 111 spaced surfaces are arranged, fill the word line 140 of groove between full described the first storage bit unit 150 and the second storage bit unit 160, described word line 140 and the first storage bit unit 150, between the second storage bit unit 160 and Semiconductor substrate 111, be formed with tunnel oxide 180, be positioned at the 125He drain region, source region 135 of the Semiconductor substrate 111 of the first storage bit unit 150 and the second storage bit unit 160 both sides, be positioned at the bit line 170 on 135 surfaces, 125He drain region, described source region.Wherein, described the first storage bit unit 150 comprises: be positioned at described the first storage bit unit 150 and be positioned at first silicon oxide layer 151 on described Semiconductor substrate 111 surfaces, be positioned at first floating boom 152 on described the first silicon oxide layer 151 surfaces, be positioned at the 3rd silicon oxide layer 153 on described the first floating boom 152 surfaces, be positioned at first control gate 154 on described the 3rd silicon oxide layer 153 surfaces, cover the monox lateral wall 155 of described the first silicon oxide layer 151, the first floating boom 152, the 3rd silicon oxide layer 153, the first control gate 154; Described the second storage bit unit 160 comprises: be positioned at described the second storage bit unit 160 and be positioned at second silicon oxide layer 161 on described Semiconductor substrate 111 surfaces, be positioned at second floating boom 162 on described the second silicon oxide layer 161 surfaces, be positioned at the 4th silicon oxide layer 163 on described the second floating boom 162 surfaces, be positioned at second control gate 164 on described the 4th silicon oxide layer 163 surfaces, cover the monox lateral wall 165 of described the second silicon oxide layer 161, the second floating boom 162, the 4th silicon oxide layer 163, the second control gate 164.
Because two of described gate-division type flash memory unit storage bit unit 150,160 shares a word line 140, can save the shared chip area of described flash memory, between between 125He drain region, described source region 135, be separated with two storage bit unit and a word line, spacing between 125He drain region, described source region 135 is larger, even the development along with semiconductor fabrication process, the size of semiconductor devices constantly reduces, and the spacing between described source region and drain region is still larger, is not easy to occur short-channel effect.
In the present embodiment, utilize described word line gating unit 200, bit line gating unit 300 and control gate gating unit 400 to select storage bit unit to be programmed, that wipe and read.
In the present embodiment, please refer to Fig. 4, described precharge unit 500 comprises voltage regulation unit 510, voltage bias unit 520 and adjust one to one transistor 530 with each bit lines 170, described adjustment transistor 530 comprises respectively and the source electrode of adjusting transistor 530, the first end that drain electrode is connected, the control end that the second end is connected with grid with adjusting transistor 530, the transistorized first end of described adjustment is connected with bit line 170, transistorized the second end of described adjustment is connected with voltage regulation unit 510, the adjustment transistor AND gate voltage bias unit 520 of described control end is connected, bit line 170 voltages while utilizing voltage regulation unit 510 to stablize precharge, utilize voltage bias unit 520 to control adjustment transistor pairs of bit line and carry out precharge.
Please refer to Fig. 5, described voltage regulation unit 510 comprises mirror image unit 511 and current source 512, described mirror image unit 511 comprises that input PMOS transistor 513 and a plurality of and adjustment transistor 530(are as shown in Figure 4) mirror image PMOS transistor mp<k> one to one, the source electrode of described input PMOS transistor 513 is connected with working power Vdd, after the drain and gate of described input PMOS transistor 513 is connected, is connected with current source 512; The source electrode of described a plurality of mirror image PMOS transistor mp<k> is connected with working power Vdd, the grid of described a plurality of mirror image PMOS transistor mp<k> is connected with the grid of input PMOS transistor 513, and the drain electrode of described mirror image PMOS transistor mp<k> is connected with the second end of corresponding adjustment transistor 530.
When carrying out programming operation, the electric current that the mirror image unit 511 of described voltage regulation unit 510 provides described current source 512 carries out mirror image, and obtains image current; Described image current is flowed through, and each is adjusted after transistor (mp<0>～mp<k>) the voltage stabilization on each bit line in the pre-charge voltage of preliminary filling.
Please refer to Fig. 6, described voltage bias unit 520 comprises a PMOS transistor 521, the first nmos pass transistor 522, comparer 523 and voltage divider 524, the input end in the same way of described comparer 523 connects the output terminal of described voltage divider 524, and reverse input end is used for accepting reference voltage V ref; The source electrode of a described PMOS transistor 521 is connected with working power VDD, the grid of a described PMOS transistor 521 is connected with the output terminal of comparer 523, after the drain electrode of a described PMOS transistor 521 is connected with drain electrode, the grid of the first nmos pass transistor 522, as the output end vo ut of described voltage bias unit 520, the source electrode of described the first nmos pass transistor 522 couples mutually with the input end of voltage divider 524.In the present embodiment, described voltage divider 524 is two series connection resistance R 1 and R2.In other embodiments, described voltage divider can be also other structures.
Based on above-mentioned flash memory, the embodiment of the present invention also provides a kind of programmed method of described flash memory, comprising:
Utilize precharge unit that each bit lines is precharged to pre-charge voltage;
Utilize bit line gating unit that the bit line of target storage bit unit one side to be programmed is charged to the first program voltage, at least two bit lines of target storage bit unit opposite side to be programmed are charged to the second program voltage, and described the first program voltage is greater than the second program voltage;
Utilize word line gating unit to apply the 3rd program voltage at word line corresponding to target storage bit unit to be programmed, and the voltage difference between the 3rd program voltage and the second program voltage is greater than threshold voltage;
Utilize control gate gating unit to apply the 4th program voltage at control gate corresponding to target storage bit unit to be programmed, the electronics of the corresponding channel region of target storage bit unit to be programmed is pulled in floating boom, thereby realizes programming.
Concrete, please refer to Fig. 7, the embodiment of the present invention be take the target storage bit unit M1 in Fig. 7 is carried out to Programming Notes as example.
First utilize precharge unit 500 that each bit lines 170 is precharged to pre-charge voltage, described pre-charge voltage is 2.5V, and described each bit lines BL0～BLk is precharged to 2.5V.
Utilize bit line gating unit 300 that the bit line BL1 of target storage bit unit M1 mono-side to be programmed is charged to the first program voltage, the bit line BL2 of target storage bit unit M1 opposite side, bit line BL3 are charged to the second program voltage, and described the first program voltage is greater than the second program voltage.In the present embodiment, described the first program voltage 5.5V, described the second program voltage is 0.1V, the voltage of all the other bit lines still remains on pre-charge voltage, is 2.5V.Because voltage difference between the first bit line BL1 and the second bit line BL2 is maximum, and the second program voltage is 0.1V, and open channel region, makes to utilize bit line gating unit 300 to select the storage bit unit of the row longitudinal arrangement between bit line BL1 and bit line BL2.Voltage due to bit line BL2 and bit line BL3 equates simultaneously, and the storage bit unit of the longitudinal arrangement between bit line BL2 and bit line BL3 can gating.Simultaneously because being still precharged, bit line BL0 and BL4 remain on 2.5V, between adjacent two bit lines, voltage difference is less, therefore the storage bit unit of corresponding longitudinal arrangement can not be strobed yet, and can not make to not relating to the storage unit of programming operation, to carry out maloperation in programming process.In other embodiments, the bit line BL4 of the opposite side of bit line BL3 can also be charged to 1.5V, because the voltage of bit line BL3, bit line BL4, bit line BL5 is followed successively by 0.1V, 1.5V and 2.5V, between adjacent two bit lines, voltage difference is less, therefore the storage bit unit of the longitudinal arrangement between described bit line BL3, bit line BL4, bit line BL5 can not be switched on yet, the maloperation of can not programming.
Utilize word line gating unit 200 to apply the 3rd program voltage at word line WL0 corresponding to target storage bit unit M1 to be programmed.In the present embodiment, the 3rd program voltage that described word line WL0 applies is 1.5V, and remaining word line ground connection all.Utilize word line gating unit 200 to select the transversely arranged storage bit unit of a line that target storage bit unit M1 to be programmed is corresponding, thereby selected target storage bit unit M1.
Utilize control gate gating unit 400 to apply the 4th program voltage at control gate CG02 corresponding to target storage bit unit M1 to be programmed, the electronics of the corresponding channel region of storage bit unit M1 to be programmed is pulled in floating boom, thereby realizes programming.In the present embodiment, the 4th program voltage that the control gate CG02 that described storage bit unit M1 to be programmed is corresponding applies is 8V, and the voltage that the control gate CG01 of another adjacent storage bit unit applies is 5V, and the control gate ground connection of remaining storage bit unit.Because described the 4th program voltage is greater than the first program voltage, and the voltage that control gate CG01 applies equals the first program voltage, therefore only target storage bit unit M1 corresponding to control gate CG02 programmed, the electronics of the corresponding channel region of target storage bit unit M1 to be programmed is pulled in floating boom, thereby realizes programming.
The embodiment of the present invention also provides a kind of read method of described flash memory, comprising:
Utilize bit line gating unit by the bit line ground connection of target storage bit unit one side to be read, at least two bit lines of target storage bit unit opposite side to be read are charged to first and read voltage;
Utilize word line gating unit to apply second at word line corresponding to target storage bit unit to be read and read voltage;
Utilize control gate gating unit by control gate ground connection corresponding to target storage bit unit to be read, the control gate corresponding to storage bit unit of the corresponding word line of target storage bit unit to be read opposite side applied to third reading power taking and press, the described first voltage difference reading between voltage and third reading power taking pressure is greater than threshold voltage;
By recording the size of current of the channel region of described target storage bit unit, obtain the data of target storage bit unit storage to be read.
Concrete, still please refer to Fig. 7, the embodiment of the present invention be take the target storage bit unit M1 in Fig. 7 is read to explanation as example.
Utilize bit line gating unit 300 by the bit line BL1 ground connection of target storage bit unit M1 mono-side to be read, three bit line BL2, BL3, BL4 of target storage bit unit M1 opposite side to be read are charged to first and read voltage.In the present embodiment, described first to read voltage be 1V.
Utilize word line gating unit 200 to apply second at word line WL0 corresponding to target storage bit unit M1 to be read and read voltage.In the present embodiment, described word line WL0 apply second to read voltage be 4.5V, and remaining word line ground connection all.
Utilize control gate gating unit 400 by control gate CG02 ground connection corresponding to target storage bit unit M1 to be read, the control gate CG01 corresponding to storage bit unit of the corresponding word line of target storage bit unit M1 to be read opposite side applied to third reading power taking and press, the described first voltage difference reading between voltage and third reading power taking pressure is greater than threshold voltage.In the present embodiment, described third reading power taking is pressed as 4.5V.
Owing to utilizing bit line gating unit 300, selected the storage bit unit of the row longitudinal arrangement that target storage bit unit M1 to be read is corresponding, and utilize word line gating unit 200 and control gate gating unit 400 to select the transversely arranged storage bit unit of a line that target storage bit unit M1 to be read is corresponding, thereby selected target storage bit unit M1.Because the described first voltage difference reading between voltage and third reading power taking pressure is greater than threshold voltage, the channel region that control gate CG01 is corresponding is opened.And according to the electron amount in the floating boom of target storage bit unit M1, electron amount in described floating boom is enough to channel region corresponding to target storage bit unit M1 to be opened, the channel region of target storage bit unit M1 has electric current to flow through, therefore by recording the size of current of the channel region of described target storage bit unit, the data that can obtain storage bit unit storage to be read are " 0 " still " 1 ".
The embodiment of the present invention also provides a kind of method for deleting of described flash memory, comprising:
By the floating sky of the voltage of each bit lines or ground connection;
Utilize word line gating unit to apply the first erasing voltage at word line corresponding to target storage bit unit to be erased;
Utilize control gate gating unit to apply the second erasing voltage at control gate corresponding to target storage bit unit to be erased, described the first erasing voltage is greater than the second erasing voltage, make the electronics in storage bit unit floating boom to be erased be pulled to word line, thereby realize, wipe.
Concrete, please refer to Fig. 8, the embodiment of the present invention be take the target storage bit unit M2 in Fig. 8 is carried out to Programming Notes as example, and described target storage bit unit M2 comprises the storage bit unit that two row are transversely arranged.In other embodiments, by the gating to control gate gating unit 400, the line number of described storage bit unit also can be worth for other.
In the present embodiment, first by all bit line BL0～BLk ground connection.In other embodiments, also can all bit line BL0～BLk is unsettled.
Utilize word line gating unit 200 to apply the first erasing voltage at word line WL0 corresponding to target storage bit unit M2 to be erased, and remaining word line ground connection, thereby the transversely arranged storage bit unit of two row that target storage bit unit M2 to be erased is corresponding selected.In the present embodiment, described the first erasing voltage is 8.5V.
Utilize control gate gating unit 400 to apply the second erasing voltage at control gate CG01 corresponding to target storage bit unit M2 to be erased and control gate CG02, described the first erasing voltage is greater than the second erasing voltage.In the present embodiment, two control gate CG01 and CG02 are applied to the second erasing voltage, thereby the transversely arranged storage bit unit of two row is wiped.In other embodiments, by control, apply the number of the control gate of the second erasing voltage, also can be simultaneously one or some transversely arranged storage bit unit be wiped.
In the present embodiment, described the second erasing voltage is-7V.Because the voltage difference between described the first erasing voltage and the second erasing voltage is very large, be conventionally greater than 10V, therefore the electronics in target storage bit unit M2 floating boom to be erased can be pulled to word line WL0, thereby realize, wipe.In other embodiments, described the first erasing voltage and the second erasing voltage can be also other suitable values.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a flash memory, is characterized in that, comprising: memory cell array, word line gating unit, bit line gating unit, control gate gating unit and precharge unit;
Described memory cell array comprises that several are the storage unit that matrix is arranged, described storage unit is gate-division type flash memory unit, described gate-division type flash memory unit comprises and is positioned at spaced the first storage bit unit of semiconductor substrate surface and the second storage bit unit, in described the first storage bit unit, there is the first floating boom and the first control gate, in described the second storage bit unit, there is the second floating boom and the second control gate, fill the word line of groove between full described the first storage bit unit and the second storage bit unit, be positioned at source region and the drain region in described the first storage bit unit and the second storage bit unit outside, the bit line being electrically connected to described source region and drain region,
Described word line gating unit is connected with the word line of described storage unit, utilizes described word line gating unit select and control corresponding storage bit unit and read, programme, wipe processing;
Described bit line gating unit is connected with the bit line of described storage unit, utilizes described bit line gating unit select and control corresponding storage bit unit and read, programme, wipe processing;
Described control gate gating unit is connected with the second control gate with the first control gate of described storage unit, utilizes described control gate gating unit select and control corresponding storage bit unit and read, programme, wipe processing;
Described precharge unit is connected with the bit line of described storage unit, and described flash memory is when carrying out precharge, by the voltage preliminary filling on each bit lines and maintain pre-charge voltage.
2. flash memory as claimed in claim 1, it is characterized in that, described precharge unit comprises voltage regulation unit, voltage bias unit and adjust one to one transistor with each bit lines, described adjustment transistor comprises respectively and source electrode, the first end that drain electrode is connected, the second end and the control end being connected with grid, the transistorized first end of described adjustment is connected with bit line, transistorized the second end of described adjustment is connected with voltage regulation unit, the transistorized control end of described adjustment is connected with voltage bias unit, pre-charge voltage while utilizing voltage regulation unit to stablize precharge, utilize voltage bias unit controls to adjust transistor pairs of bit line and carry out precharge.
3. flash memory as claimed in claim 2, it is characterized in that, described voltage regulation unit comprises mirror image unit and current source, described mirror image unit comprises input PMOS transistor and a plurality of and adjustment transistor mirror image PMOS transistor one to one, the transistorized source electrode of described input PMOS is connected with working power, after the transistorized drain and gate of described input PMOS is connected, is connected with current source; The transistorized source electrode of described a plurality of mirror image PMOS is connected with working power, the transistorized grid of described a plurality of mirror image PMOS is connected with the transistorized grid of input PMOS, and the transistorized drain electrode of described mirror image PMOS is connected with corresponding transistorized the second end of adjustment.
4. flash memory as claimed in claim 1, it is characterized in that, described voltage bias unit comprises a PMOS transistor, the first nmos pass transistor, comparer and voltage divider, the input end in the same way of described comparer connects the output terminal of described voltage divider, and the reverse input end of described comparer is used for accepting reference voltage; The transistorized source electrode of a described PMOS is connected with working power, the transistorized grid of a described PMOS is connected with the output terminal of comparer, after the transistorized drain electrode of a described PMOS is connected with drain electrode, the grid of the first nmos pass transistor, as the output terminal of described voltage bias unit, the source electrode of described the first nmos pass transistor couples mutually with the input end of voltage divider.
5. a programmed method for flash memory as claimed in claim 1, is characterized in that, comprising:
Utilize precharge unit that each bit lines is precharged to pre-charge voltage;
Utilize bit line gating unit that the bit line of target storage bit unit one side to be programmed is charged to the first program voltage, at least two bit lines of target storage bit unit opposite side to be programmed are charged to the second program voltage, and described the first program voltage is greater than the second program voltage;
Utilize word line gating unit to apply the 3rd program voltage at word line corresponding to target storage bit unit to be programmed, and the voltage difference between the 3rd program voltage and the second program voltage is greater than threshold voltage;
Utilize control gate gating unit to apply the 4th program voltage at control gate corresponding to target storage bit unit to be programmed, the electronics of the corresponding channel region of target storage bit unit to be programmed is pulled in floating boom, thereby realizes programming.
6. the programmed method of flash memory as claimed in claim 5, is characterized in that, described pre-charge voltage is 2.5V, and the first program voltage is 5.5V, and the second program voltage is 0.1V, and the 3rd program voltage is 1.5V, and the 4th program voltage is 8V.
7. a read method for flash memory as claimed in claim 1, is characterized in that, comprising:
Utilize bit line gating unit by the bit line ground connection of target storage bit unit one side to be read, at least two bit lines of target storage bit unit opposite side to be read are charged to first and read voltage;
Utilize word line gating unit to apply second at word line corresponding to target storage bit unit to be read and read voltage;
Utilize control gate gating unit by control gate ground connection corresponding to target storage bit unit to be read, the control gate corresponding to storage bit unit of the corresponding word line of target storage bit unit to be read opposite side applied to third reading power taking and press, the described first voltage difference reading between voltage and third reading power taking pressure is greater than threshold voltage;
By recording the size of current of the channel region of described target storage bit unit, obtain the data of target storage bit unit storage to be read.
8. the read method of flash memory as claimed in claim 7, is characterized in that, first to read voltage be 1V, and second to read voltage be 4.5V, and third reading power taking is pressed as 4.5V.
9. a method for deleting for flash memory as claimed in claim 1, is characterized in that, comprising:
By the floating sky of the voltage of each bit lines or ground connection;
Utilize word line gating unit to apply the first erasing voltage at word line corresponding to target storage bit unit to be erased;
Utilize control gate gating unit to apply the second erasing voltage at control gate corresponding to target storage bit unit to be erased, described the first erasing voltage is greater than the second erasing voltage, make the electronics in storage bit unit floating boom to be erased be pulled to word line, thereby realize, wipe.
10. the method for deleting of flash memory as claimed in claim 9, is characterized in that, the first erasing voltage is 8.5V, and the second erasing voltage is-7V.
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