CN109445365A - A kind of screening test method of the embedded multiplier of FPGA - Google Patents
A kind of screening test method of the embedded multiplier of FPGA Download PDFInfo
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- CN109445365A CN109445365A CN201811616299.8A CN201811616299A CN109445365A CN 109445365 A CN109445365 A CN 109445365A CN 201811616299 A CN201811616299 A CN 201811616299A CN 109445365 A CN109445365 A CN 109445365A
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0428—Safety, monitoring
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
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Abstract
The present invention relates to a kind of performance test methods of the embedded multiplier of FPGA, include the following steps: (1) embedded multiplier IP kernel Functional Design；(2) pseudo-random sequence test vector designs；(3) rtl code emulates；(4) test result analysis circuit design；(5) module duplication and output logical design.The screening test method of the embedded multiplier of FPGA provided by the invention solves the disadvantage that ATE testing expense is high, measuring technology difficulty is big using the test method based on BIST；It is inputted simultaneously using pseudo-random sequence as excitation, reduces the testing time, improve testing efficiency.This method takes full advantage of the programmable feature of fpga chip and chip interior programmable logic cells abundant and embedded memory cell (Block Random Access Memory, BRAM).The implementation steps of the invention is simple, portable strong, has certain engineering application value.
Description
Technical field
The present invention relates to a kind of screening test methods of the embedded multiplier of FPGA, belong to technical field of integrated circuits.
Background technique
With the development of the technical fields such as computer, information technology and IC design, Digital Signal Processing due to
With precision height, flexibility is big, be easy to large-scale integrated and can carry out the advantages such as multidimensional data processing, and importance increasingly exists
It is showed in every field.Carrier of the digital information processing system as Digital Signal Processing, core component are digital letters
Number processing unit, Typical Representative of the FPGA as restructural digital processing element, with its very powerful computing capability and flexibility,
The advantages that inexpensive, shows one's talent in numerous digital processing elements, by more and more users parent rely.
Field programmable gate array (Field Programmable Gate Arrays, FPGA) is internal to be generally integrated with number
Ten embedded multiplication modules even up to a hundred, embedded multiplier function multiplicity, internal structure are complicated, the tested person time with
The limitation of testing cost, FPGA manufacturer generally will not carry out comprehensive functional test to general commercial fpga chip.Height can
By application field, user needs to carry out the additional screening test to the commercial chip of buying, to meet use of the complete machine to component
Reliability requirement.
Embedded multiplier is a kind of important IP stone inside FPGA, is mainly used for Digital Signal Processing.Compared to looking into
Table is looked for, has many advantages, such as that speed is fast, low in energy consumption, resource occupation is few.Some researches show that real using embedded multiplier IP stone
Existing multiplying realizes that area is about 1/10th of LUT table, and speed is then 5 times of LUT table compared to LUT table.Therefore,
Embedded multiplier is integrated for realizing that Digital Signal Processing is of great significance using FPGA.
Currently, embedded multiplication module mainly passes through ATE(Automatic Test Equipment, auto testing instrument)
Tester table carries out functional test, and ATE equipment is by dividing test output result fpga chip input test vector sum
Analysis, to diagnose FPGA internal fault.There are two main problems for ATE test method:
(1) it incurs great expense and purchases or rent ATE equipment, and need to develop specific ATE test program, this is certain
The cost that user needs to bear is increased in degree.
(2) being continuously increased with FPGA integrated level, chip functions become increasingly complex, and encapsulate I/O port number and be limited,
The difficulty tested comprehensively using ATE equipment FPGA internal resource is increasing.
Summary of the invention
The invention solves technical problems to be: the shortcomings that overcoming above-mentioned technology, provides a kind of based on built-in self-test
The embedded multiplier screening test method of FPGA of (Built-in Self Test, BIST).
In order to solve the above-mentioned technical problem, technical solution proposed by the present invention is: a kind of sieve of the embedded multiplier of FPGA
Test method is selected, is included the following steps:
(1) embedded multiplier IP kernel Functional Design；Symbolization number, have input deposit, have viewing pipeline deposit, 18b ×
The operating mode of 18b；
(2) pseudo-random sequence test vector designs；Pseudo-random sequence is produced by seed, clock, reset signal by deterministic algorithm
It is raw；
(3) rtl code emulates；Expected correct output is obtained by ModelSim emulation as a result, generating FPGA insertion
Initialization ROM file needed for formula memory module；By the corresponding BRAM IP kernel module of exampleization, correct output knot is completed
Storage；
(4) test result analysis circuit design；After test starts, believed by clock address corresponding with reset signal generation
Number, and then read the storing data of appropriate address in BRAM module；Pass through the comparison with embedded multiplier calculated result, judgement
Whether function is correct, and then exports to state；
(5) module duplication and output logical design；Each test module includes the multiplication arithmetic operation list of 4 18b × 18b
Member, the pseudo-random sequence of 2 18b, memory, test result comparator, and by reset signal and symbol-bit groupings at control
Signal；Xor operation is carried out to the output result of each test module, mistake occurs in certain test module, and output signal is by low change
Height then issues alarm signal and reminds user.
Above scheme is further improvement is that in the step (4), the calculating knot of a certain period built-in type multiplier
There is mistake in fruit, and status signal is got higher by low, then issues alarm signal and remind user.
The screening test method of the embedded multiplier of FPGA provided by the invention, using the test method based on BIST,
Solves the disadvantage that ATE testing expense is high, measuring technology difficulty is big；It inputs, reduces using pseudo-random sequence as excitation simultaneously
Testing time improves testing efficiency.This method takes full advantage of the programmable feature of fpga chip and chip interior is abundant
Programmable logic cells and embedded memory cell (Block Random Access Memory, BRAM).The present invention is real
It is simple to apply step, it is portable strong, there is certain engineering application value.
Detailed description of the invention
The present invention will be further explained below with reference to the attached drawings.
Fig. 1 is that test implementation process is surveyed in one preferred embodiment screening of the present invention.
Fig. 2 is pseudo-random sequence production principle block diagram.
Fig. 3 is test schematic block circuit diagram.
Specific embodiment
Embodiment
The performance test methods of the embedded multiplier of the FPGA of the present embodiment, as shown in Figure 1, including the following steps:
(1) embedded multiplier IP kernel Functional Design；
(2) pseudo-random sequence test vector designs；
(3) rtl code emulates；
(4) test result analysis circuit design；
(5) module duplication and output logical design.
Traversal test is the survey for inputting all possible test and excitation to circuit-under-test, and observing circuit-under-test output result
Method for testing.If circuit-under-test is combinational logic circuit, it is assumed that share n data in pin, then test vector has 2n kind.If
The unit time for testing and completing observation every time is t, then completing the total time that test needs is 2nt.And for sequence circuit,
Then testing total time can also be longer.Therefore, traversal test applies in general to the less circuit of input terminal.For embedded multiplier
For, which needs to consume a large amount of testing time, and testing cost is high.
Have the characteristics that reconfigurability in view of fpga chip, can be used built-in self-test (Built in Self Test,
BIST method) detects the failure of FPGA, is diagnosed.By programming by a part of logical resource of FPGA be used as test to
It measures generator (Test Pattern Generation, TPG), TPG can be tested module (Block Under Test, BUT)
There is provided excitation input, another part logical resource be used as output response analyzer (Output Response Analyzer,
ORA), ORA can the output result to BUT analyse and compare, and then judge BUT with the presence or absence of failure.Therefore, the present invention draws
The test thinking based on BIST is entered.
For general fpga chip, embedded multiplier can realize that 9b × 9b, 18b × 18b, 36b × 36b multiply
Method operation.According to the difference of data bit width, an embedded multiplication module can the multiple multiplyings of parallel processing.One insertion
Formula multiplication module can be completed at the same time: the multiplication of 8 9b × 9b；Or the multiplication of 4 18b × 18b；Or 1 36b × 36b multiplies
Method.
The operand of multiplication can be unsigned number and signed number, and signa and signb are respectively intended to indicate two operations
Whether number is signed number, and usual logic 1 indicates signed number, and 0 indicates unsigned number.If any one operand is that have symbol
Number, then result is also signed number.The entire embedded multiplication module of the two effect of signals, i.e., embedded multiplication module
In all operand (A or B) have identical symbolic number characteristic.
The data entry mode of the embedded multiplier of FPGA may be configured to deposit and without two kinds of deposit, with regard to test
Speech is included in register mode without deposit mode, therefore need to only test verifying has deposit mode.Entire embedded multiplication
Device is equivalent to a combined logic block, and the variation of A, B value can all be reflected in output OUT, and output result can be sent to flowing water
Line register directly bypasses away.
To sum up, in order to improve testing efficiency and test coverage, signed number can be used in step (1), has input to post
Deposit, have the operating mode of viewing pipeline deposit, 18b × 18b.
As shown in Fig. 2, pseudo-random sequence is generated by seed, clock, reset signal by deterministic algorithm.By using puppet
Random sequence can not test all possible test vector one by one, the time needed for thus can be shortened test.
After the operating mode and pseudo-random sequence of embedded multiplier determine, so that it may be emulated and be obtained by ModelSim
Expected correct output is as a result, initialization ROM file needed for generating FPGA embedded memory module in turn.Pass through example phase
The BRAM IP kernel module answered, can complete the storage of correct result.
After test starts, by clock address signal corresponding with reset signal generation, and then read in BRAM module
The storing data of appropriate address.Pass through the comparison with embedded multiplier calculated result, it can be determined that whether function is correct, in turn
State (correct/error) is exported.Once there is mistake, state letter in the calculated result of a certain period built-in type multiplier
It number is got higher by low, illuminating state indicator light reminds user.
It is each since an embedded multiplication module can be completed at the same time the multiplication arithmetic operation of 4 18b × 18b
Test module includes the multiplication arithmetic arithmetic element of 4 18b × 18b, the pseudo-random sequence of 2 18b, memory, test knot
Fruit comparator, and by reset signal and symbol-bit groupings at control signal, as shown in Figure 3.In general, each fpga chip
Internal includes multiple embedded multiplication modules, needs to replicate test module, guarantees the resource of embedded multiplier
Utilization rate reaches 100%, while carrying out xor operation to the output result of each test module, once so that certain test module goes out
Existing mistake, output signal are got higher by low, and illuminating state indicator light reminds user.
The present invention is not limited to the above embodiment.All technical solutions formed using equivalent replacement, are all fallen within the present invention and wanted
The protection scope asked.
Claims (2)
1. a kind of screening test method of the embedded multiplier of FPGA, it is characterised in that include the following steps:
(1) embedded multiplier IP kernel Functional Design；Symbolization number, have input deposit, have viewing pipeline deposit, 18b ×
The operating mode of 18b；
(2) pseudo-random sequence test vector designs；Pseudo-random sequence is produced by seed, clock, reset signal by deterministic algorithm
It is raw；
(3) rtl code emulates；Expected correct output is obtained by ModelSim emulation as a result, generating FPGA insertion
Initialization ROM file needed for formula memory module；By the corresponding BRAM IP kernel module of exampleization, correct output knot is completed
Storage；
(4) test result analysis circuit design；After test starts, believed by clock address corresponding with reset signal generation
Number, and then read the storing data of appropriate address in BRAM module；Pass through the comparison with embedded multiplier calculated result, judgement
Whether function is correct, and then exports to state；(5) module duplication and output logical design；Each test module includes 4
The multiplication arithmetic arithmetic element of a 18b × 18b, the pseudo-random sequence of 2 18b, memory, test result comparator, Yi Jiyou
Reset signal and symbol-bit groupings at control signal；Xor operation is carried out to the output result of each test module, certain test mould
There is mistake in block, and output signal is got higher by low, then issues alarm signal and remind user.
2. the performance test methods of the embedded multiplier of FPGA according to claim 1, it is characterised in that: the step
(4) in, there is mistake in the calculated result of a certain period built-in type multiplier, and status signal is got higher by low, then issues alarm signal
Number remind user.
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| CN109976707A (en) * | 2019-03-21 | 2019-07-05 | 西南交通大学 | A kind of variable bit width multiplier automatic generating method |
| CN111025133A (en) * | 2019-10-24 | 2020-04-17 | 北京时代民芯科技有限公司 | Test method of second-order Booth coding Wallace tree multiplier circuit |
| CN113985256A (en) * | 2021-11-01 | 2022-01-28 | 北京中科胜芯科技有限公司 | FPGA life test method |
| TWI771252B (en) * | 2021-12-21 | 2022-07-11 | 南亞科技股份有限公司 | Electronic test system and electronic test method |
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| TWI771252B (en) * | 2021-12-21 | 2022-07-11 | 南亞科技股份有限公司 | Electronic test system and electronic test method |
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