CN109976707A - A kind of variable bit width multiplier automatic generating method - Google Patents
A kind of variable bit width multiplier automatic generating method Download PDFInfo
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- CN109976707A CN109976707A CN201910215666.1A CN201910215666A CN109976707A CN 109976707 A CN109976707 A CN 109976707A CN 201910215666 A CN201910215666 A CN 201910215666A CN 109976707 A CN109976707 A CN 109976707A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
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Abstract
The present invention discloses a kind of variable bit width multiplier automatic generating method, and user creates destination folder, configures top layer multiplier parameter；According to multiplier nested layer level in the same level multiplier parameter configuration file, divide downwards step by step, and generate corresponding RTL code；Until being divided unit is stopping division after minimum particle size unit, the generation work of multiplier RTL code needed for completing.The present invention considers the configuration of flowing water series, realizes the configurability of multiplier, keeps the multiplier flexibility of design high, universality is strong.
Description
Technical field
The present invention relates to digit chip design field, specially a kind of variable bit width multiplier automates generation side
Method.
Background technique
Multiplier be arithmetic unit important in the devices such as hard nucleus management device, DSP, filter, high-performance microcontroller it
One.High-performance multiplication also plays very in field of signal processing such as image, voice, encryptions other than being directly used in arithmetic element
Important role.Structure is complicated for multiplier, delay is big, execution cycle is longer, often in the critical path in system, because
This, the structure of design optimization multiplier will substantially improve the performance indicators such as speed, area and the power consumption of entire processor system.With
Machine learning, big data accelerate contour performance to calculate the appearance of scene, multiplier is in processing real-time video, audio and image
Very big specific gravity is accounted in signal processing.And since application scenarios are varied, all to the bit wide, data type and performance of multiplier
It has different needs, it is therefore desirable to which one kind can quickly design the multiplier hardware structure of variable amount of bits, high flexibility ratio.
Existing bibliography, such as Jiao Jiye, Mu Rong, Hao Yue quickly design the programming that high-performance has sign multiplication device circuit
Speech research electronic letters, vol .2013, Vol.41 (11): 2256-2261.Document design high-performance has the volume of sign multiplication device
Cheng Yuyan, core concept are by the basic unit of three parts such as the encoder, adder tree, mimimum adder of multiplier point
It separates out and, basic unit function and interconnecting relation are indicated using instruction.The shortcomings that document is the flexibility ratio branch to variable amount of bits
It holds not enough, and in the quick design of multiplier, not yet considers the configuration of flowing water series.
Summary of the invention
In view of the above-mentioned problems, the purpose of the present invention is to provide a kind of quick, flexible, and consider the configuration of flowing water series
Variable bit width multiplier automatic generating method.Technical solution is as follows:
Step 1: user creates destination folder, configures top layer multiplier parameter, including flowing water series；
Step 2: according to multiplier nested layer level in the same level multiplier parameter configuration file, divide downwards step by step, and
Generate corresponding RTL code；
Step 3: circulation step 2, until being divided unit is stopping division after minimum particle size unit, multiplication needed for completing
The generation work of device RTL code.
Further, the configuration file of the top layer multiplier parameter is text file, including the customized of user's input
9 multiplier parameters:
Parameter $ 1: the bit bit wide of multiplicand digit expression multiplicand A；
Parameter 2: the bit bit wide of multiplier digit expression multiplier B；
Parameter $ 3:s indicates that multiplicand A is signed number；U indicates that multiplicand A is unsigned number；
Parameter $ 4:s indicates that multiplier B is signed number；U indicates that multiplier B is unsigned number；
Parameter $ 5:rst indicates asynchronous reset；Sclr indicates synchronous reset；
Parameter $ 6: the store path for the Verilog code that file destination path representation script generates
Parameter $ 7: the file path of cell library file path expression method of least squares device cell library；
Parameter $ 8: string representation top-level module name；
Parameter 9: the flowing water series of flowing water series expression user configuration.
Further, the value range of configurable several m of the flowing water series are as follows: 0≤m≤2n, wherein n is RTL generation
Code divides the number of plies；For every layer of RTL code, there are two insertion position is optional for assembly line: after the adder of maximum number of digits, CSA
Between adder.
Further, the multiplier nested layer level using configurable digit 2,4,8,12,16,20,24,28,
32 }, for the multiplier of user configuration any combination.
Further, the step 2 specifically: after the top layer parameter for configuring the same level multiplier, judge the same level multiplication
Whether device is minimum unit multiplier, if then calling directly method of least squares device unit；Otherwise the same level multiplier is split into two
The secondary multiplier of group, and then generate RTL code, comprising: the same level multiplier top layer RTL code, CSA RTL code, final addition
Device RTL code, register group RTL code, the parameter configuration files of secondary multiplier.
The beneficial effects of the present invention are: the present invention takes full advantage of the spy that multiplier architecture has multi-layer rule structure
Then point, multiplier parameter needed for user terminal creates destination folder, configuration draw downwards step by step according to multiplier nested layer level
Divide and generate corresponding RTL code, until being divided unit is stopping division after minimum particle size unit, multiplier needed for completing
The generation work of RTL code.Therefore, it can support that the bit wide of multiplier and multiplicand is variable.Meanwhile the present invention considers flowing water series
Configuration, realize the configurability of multiplier, keep the multiplier flexibility of design high, universality is strong.
Detailed description of the invention
Fig. 1 is the overview flow chart of variable bit width multiplier automatic generating method of the present invention.
Fig. 2 is code building flow chart.
Fig. 3 is that multiplier realizes general frame.
Fig. 4 is 8bit cell library script general frame.
Specific embodiment
The present invention is described in further details in the following with reference to the drawings and specific embodiments.Fig. 1 is proposed by this patent
Multiplier quickly generates flow chart, multiplier parameter needed for creating destination folder, configuration in user, then according to table 3-4 institute
The multiplier nested layer level of column is divided downwards step by step and is generated corresponding RTL code, until being divided unit is most granule
After spending unit, stop dividing, the generation work of multiplier RTL code needed for completing.Specific step is as follows:
Step 1: creating destination folder in user terminal, configure top layer multiplier parameter.
Top layer configuration file is a text file, and the inside is the parameter of the multiplier of user's input, these parameters need
It is separated, could be correctly identified by script with space, specifically there are 9 parameters in the inside, and the meaning specifically represented is as shown in table 1.Top
Layer parameter is customized by the user, other parameters at different levels are by every layer of Software Create, and the format in file is identical, each current
Configuration stage can automatically generate the configuration file of next stage.
The requirement of table 3-6 configuration file
Step 2: according to multiplier nested layer level in the same level multiplier parameter configuration file, divide downwards step by step, and
Generate corresponding RTL code.
When method of least squares device cell library is 2bit multiplier, all even numbers that should may be implemented to be up to 32bit multiply
The multiplier of musical instruments used in a Buddhist or Taoist mass and any combination between them, it is contemplated that some multipliers and being of little use, so only using
{ 2,4,8,12,16,20,24,28,32 } these configurable digits, user can configure the multiplication of any combination between them
Device, table 3-4 show its detailed nested layer level zoned format.
Table 3-4 multiplier nested layer level divides sheet form
Segmentation composition form based on 4bit and 8bit method of least squares device cell library is identical as the segmentation principle in upper table, this
In just repeat no more.
Step 3: circulation step 2, until being divided unit is stopping division after minimum particle size unit, multiplication needed for completing
The generation work of device RTL code.
Every level-one " code generating method " is almost the same, and the format for the configuration file that every level-one generates is identical, different
Place be multiplier bit wide, the format of multiplicand and multiplier and every level-one generate the top-level module name of code.
Every grade " code generating method " can generate five parts: the same level multiplier top layer RTL code, CSA RTL code, most
Whole adder RTL code, register group RTL code, the parameter configuration files of next stage.
Fig. 2 is every grade of " code generating method " specific implementation flow chart.After the top layer parameter for configuring the same level multiplier, sentence
Whether disconnected the same level multiplier is minimum unit multiplier, if then calling directly method of least squares device unit；Otherwise by the same level multiplication
Device is split as multiplier composition form 1 and multiplier composition form 2, and then respectively generates the Verilog top document of the same level, then
Next stage configuration is respectively generated, and generates the RTL description of adder and register.
Assembly line configurability: the value range of the configurable number m of pipelining-stage are as follows: 0≤m≤2n, wherein n draws for RTL code
Hierarchy number.For every layer of RTL code, assembly line there are two insertion position it is optional: after the adder of maximum number of digits, CSA with plus
Between musical instruments used in a Buddhist or Taoist mass.
The present embodiment realizes the configurability of multiplier on the basis of optimizing multiplier performance, makes the multiplication of design
Device flexibility is high, and universality is strong, mainly includes two big aspects, i.e. the realization of the realization of cell library multiplier and script, by
It is introduced before it is known that the multiplier of big digit can be split as the multiplier of small digit, is then called step by step until cell library multiplies
Musical instruments used in a Buddhist or Taoist mass, and the work that script is completed is exactly the calling between the fractionation and multiplier of multiplier, the RTL for generating them can be comprehensive
Close file.
Fig. 3 is whole simple frame, user firstly the need of by the concrete configuration of top layer multiplier be written one it is specified
In file, then the content of this document will be read in by shell script, and instantiate relevant RTL file, multiplying including top layer
The concrete configuration of next stage after musical instruments used in a Buddhist or Taoist mass, register group, CSA compressor, ripple adder and fractionation.
There are three types of implementations, respectively 2-bit, 4-bit and 8-bit multiplication for method of least squares device unit in the present embodiment
Device, therefore user can be according to specifically requiring environment voluntarily to select.Before just it was mentioned that the invention that the work that entire method is completed is to multiply
Calling between the fractionation and multiplier of musical instruments used in a Buddhist or Taoist mass, generate they RTL can comprehensive file, with 8bit method of least squares device cell library
For, if generating the multiplier of a 32X32bit, whole realization frame is as shown in figure 4, the present embodiment the method is pressed
According to the zoned format of multiplier, the top layer VerilogHDL file of the same level is generated, then calls next stage multiplier step by step, until
Minimum unit library.
Claims (5)
1. a kind of variable bit width multiplier automatic generating method, which comprises the following steps:
Step 1: user creates destination folder, configures top layer multiplier parameter, including flowing water series；
Step 2: according to multiplier nested layer level in the same level multiplier parameter configuration file, divide downwards step by step, and generate
Corresponding RTL code；
Step 3: circulation step 2, until being divided unit is stopping division after minimum particle size unit, multiplier RTL needed for completing
The generation work of code.
2. variable bit width multiplier automatic generating method according to claim 1, which is characterized in that the top layer multiplication
The configuration file of device parameter be text file, including user input customized 9 multiplier parameters:
Parameter $ 1: the bit bit wide of multiplicand digit expression multiplicand A；
Parameter 2: the bit bit wide of multiplier digit expression multiplier B；
Parameter $ 3:s indicates that multiplicand A is signed number；U indicates that multiplicand A is unsigned number；
Parameter $ 4:s indicates that multiplier B is signed number；U indicates that multiplier B is unsigned number；
Parameter $ 5:rst indicates asynchronous reset；Sclr indicates synchronous reset；
Parameter $ 6: the store path for the Verilog code that file destination path representation script generates
Parameter $ 7: the file path of cell library file path expression method of least squares device cell library；
Parameter $ 8: string representation top-level module name；
Parameter 9: the flowing water series of flowing water series expression user configuration.
3. variable bit width multiplier automatic generating method according to claim 1, which is characterized in that the flowing water series
Configurable several m value range are as follows: 0≤m≤2n, wherein n be RTL code divide the number of plies；For every layer of RTL code, flowing water
There are two insertion position is optional for line: after the adder of maximum number of digits, between CSA and adder.
4. variable bit width multiplier automatic generating method according to claim 1, which is characterized in that the multiplier is embedding
Covering level using configurable digit is { 2,4,8,12,16,20,24,28,32 }, for the multiplier of user configuration any combination.
5. variable bit width multiplier automatic generating method according to claim 1, which is characterized in that step 2 tool
Body are as follows: after the top layer parameter for configuring the same level multiplier, judge whether the same level multiplier is minimum unit multiplier, if then straight
It connects and calls method of least squares device unit；Otherwise the same level multiplier is split into two groups of secondary multipliers, and then generates RTL code, packet
It includes: the same level multiplier top layer RTL code, CSA RTL code, final adder RTL code, register group RTL code, secondary factorial
The parameter configuration files of musical instruments used in a Buddhist or Taoist mass.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111125976A (en) * | 2019-12-06 | 2020-05-08 | 中国电子科技集团公司第五十八研究所 | Automatic generation method of RTL model |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101458617A (en) * | 2008-01-22 | 2009-06-17 | 西北工业大学 | 32 bit integer multiplier based on CISC microprocessor |
| CN101552547A (en) * | 2009-01-14 | 2009-10-07 | 西南交通大学 | Pseudo-continuous work mode switch power supply power factor correcting method and device thereof |
| CN201607731U (en) * | 2009-09-15 | 2010-10-13 | 新思科技有限公司 | Equipment used for circuit design of sequential units |
| CN102073473A (en) * | 2009-11-20 | 2011-05-25 | 杨军 | Field programmable gata array (FPGA)-based metric floating-point multiplier design |
| CN102591615A (en) * | 2012-01-16 | 2012-07-18 | 中国人民解放军国防科学技术大学 | Structured mixed bit-width multiplying method and structured mixed bit-width multiplying device |
| US20130007085A1 (en) * | 2011-06-30 | 2013-01-03 | Imagination Technologies, Ltd. | Method and Apparatus For Performing Lossy Integer Multiplier Synthesis |
| CN103699355A (en) * | 2013-12-30 | 2014-04-02 | 南京大学 | Variable-order pipeline serial multiply-accumulator |
| US20140280410A1 (en) * | 2013-03-15 | 2014-09-18 | Imagination Technologies Limited | Constant Fraction Integer Multiplication |
| CN105378651A (en) * | 2013-05-24 | 2016-03-02 | 相干逻辑公司 | Memory-network processor with programmable optimizations |
| CN108805276A (en) * | 2017-06-16 | 2018-11-13 | 上海兆芯集成电路有限公司 | Processor, method and computer usable medium for operation processing device |
| CN109445365A (en) * | 2018-12-27 | 2019-03-08 | 南京胜跃新材料科技有限公司 | A kind of screening test method of the embedded multiplier of FPGA |
-
2019
- 2019-03-21 CN CN201910215666.1A patent/CN109976707B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101458617A (en) * | 2008-01-22 | 2009-06-17 | 西北工业大学 | 32 bit integer multiplier based on CISC microprocessor |
| CN101552547A (en) * | 2009-01-14 | 2009-10-07 | 西南交通大学 | Pseudo-continuous work mode switch power supply power factor correcting method and device thereof |
| CN201607731U (en) * | 2009-09-15 | 2010-10-13 | 新思科技有限公司 | Equipment used for circuit design of sequential units |
| CN102073473A (en) * | 2009-11-20 | 2011-05-25 | 杨军 | Field programmable gata array (FPGA)-based metric floating-point multiplier design |
| US20130007085A1 (en) * | 2011-06-30 | 2013-01-03 | Imagination Technologies, Ltd. | Method and Apparatus For Performing Lossy Integer Multiplier Synthesis |
| CN102591615A (en) * | 2012-01-16 | 2012-07-18 | 中国人民解放军国防科学技术大学 | Structured mixed bit-width multiplying method and structured mixed bit-width multiplying device |
| US20140280410A1 (en) * | 2013-03-15 | 2014-09-18 | Imagination Technologies Limited | Constant Fraction Integer Multiplication |
| CN105378651A (en) * | 2013-05-24 | 2016-03-02 | 相干逻辑公司 | Memory-network processor with programmable optimizations |
| CN103699355A (en) * | 2013-12-30 | 2014-04-02 | 南京大学 | Variable-order pipeline serial multiply-accumulator |
| CN108805276A (en) * | 2017-06-16 | 2018-11-13 | 上海兆芯集成电路有限公司 | Processor, method and computer usable medium for operation processing device |
| CN109445365A (en) * | 2018-12-27 | 2019-03-08 | 南京胜跃新材料科技有限公司 | A kind of screening test method of the embedded multiplier of FPGA |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111125976A (en) * | 2019-12-06 | 2020-05-08 | 中国电子科技集团公司第五十八研究所 | Automatic generation method of RTL model |
| CN111125976B (en) * | 2019-12-06 | 2022-09-06 | 中国电子科技集团公司第五十八研究所 | Automatic generation method of RTL model |
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