CN113985262A - Programming test method of LUT6 in FPGA - Google Patents
Programming test method of LUT6 in FPGA Download PDFInfo
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- CN113985262A CN113985262A CN202111282589.5A CN202111282589A CN113985262A CN 113985262 A CN113985262 A CN 113985262A CN 202111282589 A CN202111282589 A CN 202111282589A CN 113985262 A CN113985262 A CN 113985262A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3177—Testing of logic operation, e.g. by logic analysers
Abstract
The invention relates to a programming test method of LUT6 in FPGA, belonging to the field of test technology of LUT6 in field programmable gate array (the method comprises the following steps of 1) LUT6 logic resource function design; 2) LUT6 input vector design; 3) determining a test program variable N; 4) automatically generating a LUT6 test program by programming; 5) automatically migrating the automatically generated LUT6 test program into a LUT6 test tool through programming; 6) carrying out test simulation; 7) writing the LUT6 test program into the FPGA and reading data; 8) comparing the simulation data with read data in the FPGA; 9) and determining a test result. The invention fully covers the LUT6 module, thereby improving the testing efficiency; and an online programming mode is adopted, so that the problem of multiple instantiations of Verilog in the traditional test is solved.
Description
Technical Field
The invention relates to a programming test method of an LUT6 in an FPGA (Field Programmable Gate array), belonging to the technical Field of test of an LUT6 in an FPGA (Field Programmable Gate array).
Background
The Field Programmable Gate Arrays (FPGA) is a commonly used electronic device at present, and has the characteristics of programmability, simple and convenient application and wide application range.
At present, testing of FPGA by various domestic detection mechanisms basically adopts an application-based testing technology, namely, conformity inspection is carried out on the function of the FPGA, and the testing is based on the functional verification of an automatic testing system. The test flow is shown in fig. 1.
At the heart of the programmable logic resource is a programmable logic function block (CLB), of which a look-up table (LUT) module is an important constituent. In the test, the correctness of the combination and the sequential circuit of the structure is mainly judged.
A look-up table (LUT) can be considered to be a memory array having 1-bit outputs, with the address lines of the memory being the input signal lines of the LUT, and a LUT having n inputs corresponding to a memory having 2n memory cells. In an FPGA, an LUT is usually implemented by an SRAM memory cell, and a user writes a truth table of logic functions into the LUT in a programming manner, so as to implement a combinational logic function with any n inputs. LUT6 is a 6 input look-up table with a general output.
At present, an intuitive and simple method for testing the LUT6 is to connect the input and output of the LUT6 and the IO of the FPGA device for testing, but the main problem of this method is that the number of the IO of the FPGA device is very different from that of the LUT6, and only a small number of LUTs 6 can be tested once each configuration, and the configuration times and the measurement time cost are greatly increased by testing the LUT6 module by using this method.
However, with further improvement of the system level density of the FPGA, more and more high-performance resource cores are embedded in the FPGA, the structure of the FPGA is beyond the range of the basic architecture due to continuous improvement of the performance, and the basic test method cannot meet the test of the functional modules.
In addition, the integration level of the FPGA is higher and higher, and the completeness of the test configuration of the FPGA is also a problem that the FPGA test has to be considered
Furthermore, with the continuous expansion of the scale of the FPGA, the building of an automatic test platform cannot depend on manpower in large quantity, so the development of software is also a factor of the development of the FPGA test.
In addition, effective general structure models and fault models which can adapt to various structures are researched, so that special and general test methods for various FPGA with different structures and models are realized. Not only the FPGA is divided into a plurality of parts for testing, but also a method for testing the FPGA as a whole is researched, so that the aim of reducing the programming times is fulfilled.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the programming test method of the LUT6 in the FPGA is provided, and programming and test times are reduced, so that the problems of complex flow, high cost and low production efficiency caused by manually writing a test program in the traditional test are solved.
In order to solve the technical problems, the technical scheme provided by the invention is as follows: a programming test method of LUT6 in FPGA executes the following steps:
1) LUT6 logic resource functional design;
2) LUT6 input vector design;
3) determining a test program variable N;
4) automatically generating a LUT6 test program by programming;
5) automatically migrating the automatically generated LUT6 test program into a LUT6 test tool through programming;
6) carrying out test simulation;
7) writing the LUT6 test program into the FPGA and reading data;
8) comparing the simulation data with read data in the FPGA;
9) determining a test result, comparing an expected result with the read result, and if the expected result is consistent with the read result, passing the test; if not, the test is not passed;
the LUT6 test program comprises two groups of functional circuits, a, all LUT6 modules to be tested are configured into a 64-bit 2-system input structure, and the 64-bit 2-system is changed into a 16-system input structure for displaying; b, configuring all tested LUT6 modules as a structure of inverting and inputting 64-bit 2-system data of a previous circuit, and similarly, changing the 64-bit 2-system data into a 16-system data to be displayed when inputting; inside each LUT6 module, the input vectors are I0, I1, I2, I3, I4, I5, and I5 is the output of the previous LUT6 module.
The improvement of the technical scheme is as follows: inside each LUT6 module, the outputs of the LUT6 are all registered by programmable logic flip-flops, the registered outputs are cascaded to the I5 port of the next-stage LUT6 through internal channels, and the output of the last LUT6 is connected to the outside of the module.
The improvement of the technical scheme is as follows: expected results were obtained by ModelSim behavioral level simulation.
The invention has the beneficial effects that: the invention fully covers the LUT6 module, thereby improving the testing efficiency; by adopting an online programming mode, the problem of multiple instantiations of Verilog in the traditional test is solved; the programming mode is adopted for generating the test codes and transplanting the test codes, so that the manual operation in the test process is reduced, the production efficiency is improved, and the cost is reduced. The method has simple implementation steps, strong transportability and certain engineering application value.
Drawings
FIG. 1 is a FPGA test flow diagram.
Fig. 2 is a schematic diagram of the LUT6 test provided by the present invention.
Fig. 3 is a schematic flow chart of a programming test method of the LUT6 in the FPGA according to the present invention.
Detailed Description
Example one
In the programming test method of the LUT6 in the FPGA of this embodiment, as shown in fig. 3, the following steps are performed:
1) LUT6 logic resource functional design;
2) LUT6 input vector design;
3) determining a test program variable N;
4) automatically generating a LUT6 test program by programming;
in order to cover the memory cells of the LUT6 module, the inverse of the input data to the input data is automatically generated by programming and its automatic conversion to 16-ary is achieved. The initial input vector is set manually and multiple LUT6S combinations are automatically generated by programming. N LUT6S combinations are provided depending on the number of memory cells. Automatically generating a LUT6 test program;
5) automatically migrating the automatically generated LUT6 test program into a LUT6 test tool through programming;
6) carrying out test simulation;
7) writing the LUT6 test program into the FPGA and reading data;
8) comparing the simulation data with read data in the FPGA;
9) determining a test result, comparing an expected result with the read result, and if the expected result is consistent with the read result, passing the test; if not, the test is not passed;
the LUT6 test program comprises two groups of functional circuits, a, all LUT6 modules to be tested are configured into a 64-bit 2-system input structure, and the 64-bit 2-system is changed into a 16-system input structure for displaying; b, configuring all tested LUT6 modules as a structure of inverting and inputting 64-bit 2-system data of a previous circuit, and similarly, changing the 64-bit 2-system data into a 16-system data to be displayed when inputting; inside each LUT6 module, the input vectors are I0, I1, I2, I3, I4, I5, and I5 is the output of the previous LUT6 module.
Inside each LUT6 module, the outputs of the LUT6 are all registered by programmable logic flip-flops, the registered outputs are cascaded to the I5 port of the next-stage LUT6 through internal channels, and the output of the last LUT6 is connected to the outside of the module.
Expected results were obtained by ModelSim behavioral level simulation.
In order to reduce the configuration times and save the time cost, as shown in fig. 2, the LUT6 in the FPGA device is subjected to ergodic test, and test design input can design one LUT6 of the FPGA into a minimum logic unit LUT6s, wherein the minimum logic unit can realize output equal to input, so that tracking test can be conveniently performed in the test process, and then the output of the previous LUT6s is used as the input of the next LUT6s, so that the LUT6 is cascaded for multiple times to form an array; the advantage of such cascading is that it takes up fewer I/O pins, i.e., more than 95% of the LUTs 6 that test FPGA devices.
The present invention is not limited to the specific technical solutions described in the above embodiments, and other embodiments may be made in the present invention in addition to the above embodiments. It will be understood by those skilled in the art that various changes, substitutions of equivalents, and alterations can be made without departing from the spirit and scope of the invention.
Claims (3)
1. A programming test method of LUT6 in FPGA is characterized by executing the following steps:
1) LUT6 logic resource functional design;
2) LUT6 input vector design;
3) determining a test program variable N;
4) automatically generating a LUT6 test program by programming;
5) automatically migrating the automatically generated LUT6 test program into a LUT6 test tool through programming;
6) carrying out test simulation;
7) writing the LUT6 test program into the FPGA and reading data;
8) comparing the simulation data with read data in the FPGA;
9) determining a test result, comparing an expected result with the read result, and if the expected result is consistent with the read result, passing the test; if not, the test is not passed;
the LUT6 test program comprises two groups of functional circuits, a, all LUT6 modules to be tested are configured into a 64-bit 2-system input structure, and the 64-bit 2-system is changed into a 16-system input structure for displaying; b, configuring all tested LUT6 modules as a structure of inverting and inputting 64-bit 2-system data of a previous circuit, and similarly, changing the 64-bit 2-system data into a 16-system data to be displayed when inputting; inside each LUT6 module, the input vectors are I0, I1, I2, I3, I4, I5, and I5 is the output of the previous LUT6 module.
2. The programming test method of LUT6 in an FPGA of claim 1, wherein: inside each LUT6 module, the outputs of the LUT6 are all registered by programmable logic flip-flops, the registered outputs are cascaded to the I5 port of the next-stage LUT6 through internal channels, and the output of the last LUT6 is connected to the outside of the module.
3. The programming test method of LUT6 in an FPGA of claim 1, wherein: expected results were obtained by ModelSim behavioral level simulation.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5991907A (en) * | 1996-02-02 | 1999-11-23 | Lucent Technologies Inc. | Method for testing field programmable gate arrays |
| CN102841306A (en) * | 2011-07-21 | 2012-12-26 | 北京飘石科技有限公司 | Testing and locating method for FPGA (field programmable gate array) programmable logic unit |
| CN106771991A (en) * | 2017-01-23 | 2017-05-31 | 电子科技大学 | A kind of automatization testing technique being applied to before anti-fuse FPGA programming |
| CN109445366A (en) * | 2018-12-27 | 2019-03-08 | 南京胜跃新材料科技有限公司 | A kind of screening test method of FPGA programmable logic resource |
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- 2021-11-01 CN CN202111282589.5A patent/CN113985262A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5991907A (en) * | 1996-02-02 | 1999-11-23 | Lucent Technologies Inc. | Method for testing field programmable gate arrays |
| CN102841306A (en) * | 2011-07-21 | 2012-12-26 | 北京飘石科技有限公司 | Testing and locating method for FPGA (field programmable gate array) programmable logic unit |
| CN106771991A (en) * | 2017-01-23 | 2017-05-31 | 电子科技大学 | A kind of automatization testing technique being applied to before anti-fuse FPGA programming |
| CN109445366A (en) * | 2018-12-27 | 2019-03-08 | 南京胜跃新材料科技有限公司 | A kind of screening test method of FPGA programmable logic resource |
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