CN101158706A - Large scale integrated circuit test data and method for testing power consumption cooperate optimization - Google Patents
Large scale integrated circuit test data and method for testing power consumption cooperate optimization Download PDFInfo
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Abstract
The invention relates to a method collaborating and optimizing the test data and the power consumption of testing large scale integrated circuits. The method relates to the technical field of the large scale integrated circuits and is proposed to resolve the problem that in the prior art of SOC test, no method is available to effectively reduce the test data and the power consumption of test at the same time. The method has the following steps: the compatibility of scanning units of the circuit is analyzed and accordingly the scanning units are classified into three categories; each category of scanning units are connected respectively, and a scanning chain with copying mechanism is built; a set of test vector is adjusted according to the new scanning chain structure; the test set is compressed by the method based on the compression of repeated data and a compressed test set T<SUB>E</SUB> is acquired. When in the testing process, the compressed data is fully recovered by a decompression circuit to be tested. The invention discloses a design method for the testability of integrated circuits, and reduces the power consumption of circuits in the testing process, thus ensuring the reliability and testability; furthermore, the invention can effectively reduce the quantity of test data, shorten the test process, and lessen the number of ATE channels.
Description
Technical field
What the present invention relates to is the technical field of large scale integrated circuit.
Background technology
Along with the develop rapidly of integrated circuit technique, the integrated level of integrated circuit is more and more higher, and function also becomes increasingly complex, and especially along with the appearance of SOC (system on a chip) SOC, integrated circuit testing faces increasing challenge.
These difficulties are embodied on the one hand the raisings along with the integrated circuit complexity, and the required data volume of integrated circuit testing is increasing.For example in No. 2 chips of Godson, finish the test data that a complete test probably needs the 2G position, as integrated a plurality of digital cores in the fruit chip, test data will be more huge so.Can increase the testing cost of integrated circuit undoubtedly by the increase severely memory space problem brought, many test channel demand etc. of amount of test data.On the other hand, the power consumption that integrated circuit produces in test may reach 2 times of normal when operation power consumption, producing this phenomenon is owing to generally have only a spot of circuit module work in the chip of low power dissipation design on the one hand, then wants node generation saltus step as much as possible in the circuit during test.Because circuit-under-test may be damaged because of power consumption is excessive in test process, therefore reduce power consumption in the Test Application process and become another important goal of test development, testing power consumption has become the design for Measurability that influences cmos circuit and the major issue of corresponding detection method.
At the growing test data of integrated circuit, people have proposed the method for a lot of minimizing amount of test data, mainly can be divided into three major types.First kind method is that test compression and test are generated (Automatic Test Pattern Generation, ATPG) combination in the process that test generates, subtracts approximately by fault simulation and feature, merge or the modification test vector, to reduce the quantity of actual test vector in the test set; But it is long and exist for the not high problem of the fault coverage of non-model fault that this method will cause testing the rise time.Second class methods are BIST technology, its basic thought be utilize circuit self the test maker at the inner test vector that directly generates of circuit, finish test, commonly used have based on linear feedback shift register (LFSR) with based on the method for cellular machine (CA); But because mostly the test vector that BIST generates is pseudo-random vector, therefore fault coverage is not high, cycle tests is longer, although can further improve testing efficiency by methods such as Weighted random vector test, mixed mode BIST, but expansion along with circuit scale, the difficult fault of surveying gets more and more, the hardware spending that need pay also significantly increases, therefore the BIST method has only obtained using widely at present in the test of storer, realizes that for DSP etc. the test of other circuit of logic function is still immature.The 3rd class methods are test compression (Test Compression) technology, the test vector collection compression that this method will be calculated in advance, and be stored in the automatic test equipment (ATE).Packed data during test among the ATE by circuit inside decompression circuit be reduced into original test vector, and be loaded on the corresponding circuit-under-test.This is a kind of lossless compressiong, can guarantee that fault coverage does not reduce.The more representational test data compression algorithm that has based on coding in these class methods is as Golomb coding, FDR coding, VIHC coding etc.; The broadcast type compression algorithm; And based on compression algorithm of dictionary etc., but these methods all only compress at test data, do not consider the factor that testing power consumption improves day by day.
And in the research that reduces testing power consumption, one class method relatively more commonly used is the test vector ordering techniques, this technology utilize the delay testing vector between hamming distance for test vector to ordering, thereby reduced the 0-1 level transition times of node in the circuit test, thereby reduce testing power consumption; But the resulting effect of method of this simple change test vector order is very limited.The method of the reduction testing power consumption that second class is common is the ATPG technology of low-power consumption, the test vector that utilizes this technology to generate guarantees to compare the high fault coverage except needs, another fundamental purpose is to reduce testing power consumption, but shortcoming is to have increased the test vector number.The method that the 3rd class reduces testing power consumption is to change scan chain architecture, for example long scan chain is divided into several sections, perhaps adjust the order of scanning element on the scan chain and insert method that logic gate combines etc., this method can reduce the power consumption in scanning immigration stage, but from experiment effect, this method remains more limited for the effect that reduces testing power consumption.Also there is the scholar that MTF (minimum transition filling) model is combined with coding compression algorithm in recent years, proposed to reduce simultaneously the method for amount of test data and testing power consumption, as ARL coding and mixing RL-Huffman coding etc., but comparatively speaking, it is obtaining better effect aspect the test data compression, and very limited for the reduction of testing power consumption.
In sum, in the research to test data compression and testing power consumption reduction, adopt the thinking of research respectively mostly at present, certain methods wherein is more effective in the application scenario that it was fit to.Yet how can effectively reduce testing power consumption when reducing amount of test data is the extremely urgent problem that needs solution, also is to promote must needing of SOC (system on a chip) SOC measuring technology fast development in actual applications.
Summary of the invention
The objective of the invention is in order to solve in the existing SOC (system on a chip) SOC measuring technology is single research direction with compression verification data or reduction testing power consumption mostly, also there is not the technological means that can be effectively the reduction of the minimizing of amount of test data and testing power consumption be combined, there is the problem that hinders the fast development of SOC (system on a chip) SOC measuring technology, and the method for a kind of LSI circuit test data and testing power consumption cooperate optimization is provided.
Its method step is:
Step 1: with test set T
D={ t
1, t
2... t
nBeing expressed as a two-dimensional matrix, each row is represented a test vector, is total to n test vector, the value that on behalf of a scanning element, each row composed successively, S scanning element altogether; Calculate the compatibility between the column vector, i.e. compatibility between each scanning element in the test set;
Step 2: adopt group's division methods of putting preferential combination principle fully based on isolated point and 2-that scanning element is divided into K1, K2, K3 three class groups, scanning element in each group is fully compatible, for the group that belongs to the K1 class, each group only comprises a scanning element, for the group that belongs to the K2 class, each group only comprises two scanning elements, for the group that belongs to the K3 class, comprise three scanning elements in each group, finally there be A scanning element to put K1 class group under, there be B scanning element to put K2 class group under, have C scanning element to put K3 class group under;
Step 3: the scanning element in K1, K2, the K3 class group is connected respectively, form the scan chain that three classes have " duplicating " mechanism; First kind scan chain is the same with the plain scan chain, and is only that each scanning element is connected in series; The second class scan chain comes down to a scan chain group, be formed in parallel by two scan chains, every scan chain forms by each scanning element is connected in series respectively, wherein the scan input end of article one scan chain is as the scan input end (Scan_in) of this class scan chain, article one, the scanning output end of scan chain is as the scanning output end 1 (Scan_out 1) of this class scan chain, and the scanning output end of second scan chain is as the scanning output end 2 (Scan_out 2) of this class scan chain; In this class scan chain architecture, article two, the scanning element of same position belongs to a group on the scan chain, and this group belongs to K2 class group, connect with a triple gate between two compatible scanning elements of same position, and the Enable Pin of all triple gates links together, as the control end of the replicate run (copy) of such scan chain; When reality was tested, the scanning migration process was at first carried out on article one scan chain, and article one scan chain obtains test data; Subsequently, control copy end is carried out " duplicating " operation, and promptly all triple gates enable, thereby the second scan chain has obtained the test data identical with article one scan chain; Scanning is shifted out process and is then carried out on two scan chains respectively; The 3rd class scan chain in fact also is a scan chain group, be formed in parallel by three scan chains, every scan chain all forms by each scanning element is connected in series, wherein the scan input end of a scan chain is as the scan input end (Scan_in) of this class scan chain, article one, the scanning output end of scan chain is as the scanning output end 1 (Scan_out 1) of this class scan chain, the scanning output end of second scan chain is as the scanning output end 2 (Scan_out 2) of this class scan chain, and the scanning output end of the 3rd scan chain is as the scanning output end 3 (Scan_out 3) of this class scan chain; In this class scan chain architecture, article three, the scanning element of same position belongs to a group on the scan chain, and this group belongs to K3 class group, connect with two triple gates between three compatible scanning elements of same position, and the Enable Pin of all triple gates links together, as the control end of the replicate run (copy) of such scan chain; When reality was tested, the scanning migration process was at first carried out on a scan chain, and this scan chain obtains test data; Subsequently, control copy end is carried out " duplicating " operation, and promptly all triple gates enable, thereby the two other scan chain has obtained the test data identical with article one scan chain; Scanning is shifted out process and is then carried out on three scan chains respectively;
Step 4: the test vector collection is adjusted in the variation according to scan chain architecture;
Step 5: adopt and the repeated data in the test set are compressed the test set T after finally being compressed based on the method for repeated data compression
E
Step 6: when testing, the test data after the compression is recovered through a decompression circuit fully, and each the bar scan chain that enters then in the circuit-under-test is tested.
The present invention is a kind of design for Measurability method of integrated circuit; After using this method the sweep test structure of IC interior being designed, can reduce the testing power consumption that integrated circuit produces greatly in test process, guarantee the reliability and the measurability of circuit thus; After application this method is carried out the integrated circuit design for Measurability, can effectively reduce amount of test data, improve efficiency of data compression, therefore reduce demand, and effectively reduced the test duration the data storage space.In actual use, only need a passage to come the multi-strip scanning chain of driving circuit inside between automatic test equipment (ATE) and the hardware decompression circuit, thereby reduced the ATE number of channels, reduced testing cost.
The present invention adopts a kind of having the scan chain architecture of " duplicating " mechanism, and scanning that can the level transition times is more moves into simplified control and is " duplicating " operation, has therefore reduced the sweep test power consumption; Data compression among the present invention partly is a kind of lossless compression method, and the test set after the compression can restore original test data fully through the decompression circuit of hardware, and quantity of information is disappearance not, can guarantee that test coverage is constant; Its hardware decoding circuit is easy to realize that communication protocol is simple that hardware cost is low.
Description of drawings
Fig. 1 is the scan chain architecture synoptic diagram that the first kind has " duplicating " mechanism, Fig. 2 is the scan chain architecture synoptic diagram that second class has " duplicating " mechanism, Fig. 3 is the scan chain architecture synoptic diagram that the 3rd class has " duplicating " mechanism, Fig. 4 is test data and scanning element corresponding relation synoptic diagram, Fig. 5 is the synoptic diagram that makes up non-directed graph G according to Fig. 4 scanning element, Fig. 6 is the synoptic diagram of the non-directed graph G after upgrading, Fig. 7 is the synoptic diagram that Fig. 4 scanning element group divides the result, Fig. 8 is the scan chain architecture synoptic diagram after the reconstruct, Fig. 9 is adjusted test vector collection synoptic diagram, Figure 10 is the test vector collection synoptic diagram of subvector form, Figure 11 is the test vector collection synoptic diagram after the deletion repeating data, Figure 12 is test vector collection and the control word synoptic diagram after the compression, Figure 13 is the implication figure of control word code and expression thereof, and Figure 14 is the structural representation of decompression circuit.
Embodiment
Embodiment one: in conjunction with Fig. 1～Figure 14 present embodiment is described, the method step of present embodiment is:
Step 1: with test set T
D={ t
1, t
2... t
nBeing expressed as a two-dimensional matrix, each row is represented a test vector, is total to n test vector, the value that on behalf of a scanning element, each row composed successively, S scanning element altogether; Calculate the compatibility between the column vector, i.e. compatibility between each scanning element in the test set;
Step 2: adopt group's division methods of putting preferential combination principle fully based on isolated point and 2-that scanning element is divided into K1, K2, K3 three class groups, scanning element in each group is fully compatible, for the group that belongs to the K1 class, each group only comprises a scanning element, for the group that belongs to the K2 class, each group only comprises two scanning elements, for the group that belongs to the K3 class, comprise three scanning elements in each group, finally there be A scanning element to put K1 class group under, there be B scanning element to put K2 class group under, have C scanning element to put K3 class group under;
Step 3: the scanning element in K1, K2, the K3 class group is connected respectively, form the scan chain that three classes have " duplicating " mechanism; First kind scan chain is the same with the plain scan chain, only with each scanning element (as Fig. 1) connected in series; The second class scan chain comes down to a scan chain group, be formed in parallel by two scan chains, every scan chain forms by each scanning element is connected in series respectively, wherein the scan input end of article one scan chain is as the scan input end (Scan_in) of this class scan chain, article one, the scanning output end of scan chain is as the scanning output end 1 (Scan_out 1) of this class scan chain, and the scanning output end of second scan chain is as the scanning output end 2 (Scan_out 2) of this class scan chain; In this class scan chain architecture, article two, the scanning element of same position belongs to a group on the scan chain, and this group belongs to K2 class group, connect with a triple gate between two compatible scanning elements of same position, and the Enable Pin of all triple gates links together, as the control end (as Fig. 2) of the replicate run (copy) of such scan chain; When reality was tested, the scanning migration process was at first carried out on article one scan chain, and article one scan chain obtains test data; Subsequently, control copy end is carried out " duplicating " operation, and promptly all triple gates enable, thereby the second scan chain has obtained the test data identical with article one scan chain.Scanning is shifted out process and is then carried out on two scan chains respectively; The 3rd class scan chain in fact also is a scan chain group, be formed in parallel by three scan chains, every scan chain all forms by each scanning element is connected in series, wherein the scan input end of a scan chain is as the scan input end (Scan_in) of this class scan chain, article one, the scanning output end of scan chain is as the scanning output end 1 (Scan_out 1) of this class scan chain, the scanning output end of second scan chain is as the scanning output end 2 (Scan_out 2) of this class scan chain, and the scanning output end of the 3rd scan chain is as the scanning output end 3 (Scan_out 3) of this class scan chain; In this class scan chain architecture, article three, the scanning element of same position belongs to a group on the scan chain, and this group belongs to K3 class group, connect with two triple gates between three compatible scanning elements of same position, and the Enable Pin of all triple gates links together, as the control end (as Fig. 3) of the replicate run (copy) of such scan chain; When reality was tested, the scanning migration process was at first carried out on a scan chain, and this scan chain obtains test data; Subsequently, control copy end is carried out " duplicating " operation, and promptly all triple gates enable, thereby the two other scan chain has obtained the test data identical with article one scan chain.Scanning is shifted out process and is then carried out on three scan chains respectively.
Step 4: the test vector collection is adjusted in the variation according to scan chain architecture;
Step 5: adopt and the repeated data in the test set are compressed the test set T after finally being compressed based on the method for repeated data compression
E
Step 6: when testing, the test data after the compression is recovered through a decompression circuit fully, and each the bar scan chain that enters then in the circuit-under-test is tested.
Compatibility between the column vector in the described step 1 is meant for two column vector s
iAnd s
jIf, s
iAnd s
jTwo data of middle same position are identical, perhaps have at least one to be don't-care bit " X ", claim that then these two column vectors are compatible, and promptly the scanning element of these two column vector correspondences is compatible.
Concrete scanning element compatibility can be referring to Fig. 4, the scanning element C among Fig. 4
1And C
6Be exactly compatible.Because the needed data of compatible scanning element or identical, perhaps have at least one to be don't-care bit " X ", therefore compatible scanning element can be with same group of test data assignment.
Employing described in the step 2 based on group's division methods that isolated point and 2-put preferential combination principle fully is:
If: (C E) represents each scanning element and correlativity thereof to non-directed graph G=, and the vertex set C of figure represents S scanning element, if having compatibility relation between certain two scanning element, has a limit between then corresponding two summits; If subgraph H=(S, the E of G
H) in all have a limit between any two summits, claim that then subgraph H is the complete subgraph of G, the vertex set S of subgraph H is the group of G; Three definition are here arranged:
Definition one:, then claim this point to be the public neighbours on this limit if certain summit all has the limit to link to each other with two end points on certain bar limit;
Definition two:, claim that then this point is an isolated point if certain a bit has only a limit to link to each other with it;
Define three: if certain point has n adjacent node, and this n some formation complete subgraph, claim that then this point is a n-point fully;
It is based on repeatedly circulation based on group's division methods that isolated point and 2-put preferential combination principle fully, each preferential isolated point and adjacent node or 2-thereof of merging put and public neighbours fully, all summits all are divided and enter corresponding group in figure: be meant several summits are merged here and delete these several summits and limit that all are coupled in former figure G, form new figure, these several summits form a group, and group's partitioning algorithm concrete steps are as follows:
Isolated point and adjacent node thereof among step 2, the merging non-directed graph G, the group after the merging is classified as K2 class group, upgrades G;
2-among step 3, the merging G is point fully, and the group after the merging is classified as K3 class group, upgrades G;
If have the limit among the step 5 figure G, forward step 1 to; Otherwise group's partitioning algorithm finishes, and K1 class group is included into as a group in each remaining summit;
Behind the group's of execution partitioning algorithm, finally there be A summit to put K1 class group under, have B summit to put K2 class group under, have C summit to put K3 class group under, promptly have A scanning element to put K1 class group under, have B scanning element to put K2 class group under, have C scanning element to put K3 class group under.
At the compatibility relation of each scanning element among Fig. 4, Fig. 5～7 group's of showing partition process.At first, make up non-directed graph G, referring to Fig. 5.According to algorithm steps, at first merge isolated point C2, C3, form two C of group
2,8, C
3,7, these two groups that group all is the K2 class.Figure G after the renewal as shown in Figure 6.Owing to still have the limit among the figure G after upgrading, continue to merge.The net result that group divides as shown in Figure 7, C wherein
1,6, C
2,8, C
3,7, C
4,10Group for obtaining after merging belongs to K2 class group; And C
5, C
9, C
11, C
12Belong to K1 class group.
The difference method of attachment of the scanning element in the K1 described in the step 3, K2, the K3 class group is:
With scan chain architecture the scanning element in K1, K2, the K3 class group is connected respectively, form three class scan chains; If circuit-under-test has m scan input end (Scan_in), there be A scanning element to put K1 class group under in the step 2, there be B scanning element to put K2 class group under, there be C scanning element to put K3 class group under, then the length d of every scanning amount equates, and satisfies:
" rounding " computing (as Fig. 8) in the following formula in [] expression mathematics.
Fig. 8 is after the scanning element execution in step two among Fig. 4, the scan chain that the scan chain architecture that adopts the present invention to propose rebuilds, the length d of every scan chain=4.
The method that the test vector collection is adjusted in the variation according to scan chain architecture described in the step 4 is: the test vector collection of first kind scan chain remains unchanged; The test vector collection of the second class scan chain only keeps the single chain data after the compatible optimization; The test vector collection of the 3rd class scan chain only keeps the single chain data after the compatible optimization.
According to the scan chain architecture of Fig. 8, after the execution in step four, the test vector collection can be referring to Fig. 9.
The method of the repeated data compression described in the step 5 is:
Described repeated data are meant on some scan chain, in test vector cycle on this scan chain the test data of all scanning elements all be " 0 " or all be " 1 " (as just there being repeated data among Fig. 9); If circuit-under-test has m scan input end (Scan_in), the test vector collection is made up of n vector, execution in step three back scan chain length are d (as Figure 10), and then each vector in the test set can be regarded as by m sub vectorial the composition, and each subvector length is d; The concrete steps of its method are as follows:
Step 1: be the don't-care bit of data centralization " X " assignment, occurrence equals the last bit data value of this bit data;
Step 2: according to the data characteristics (repeated data or general data) of subvector, for each subvector is determined control word (code and the implication of control word are seen Figure 13);
Step 3: repeated data are rejected (as Figure 11) from data centralization;
Step 4: the data after the arrangement compression are unit with the vector, the data of multichain form are put in order according to the sequencing that enters the circuit-under-test scan chain be the form of single data stream (as Figure 12).
In the example of Fig. 3, the 12*4=48 bit data is arranged in the original test set; And after employing this method, data set among Figure 12 after the compression and control word are the 16+14=30 bit data altogether.Therefore the scan chain architecture and the test data compression algorithm of this method employing are more effective for the minimizing of data volume.
Decompression circuit described in the step 6 is by a finite state machine (FSM), a storer (memory), a MUX (MUX), a log
2M digit counter, a log
2D digit counter, m * 2 FIFO and a m bit shift register are formed (as Figure 14); Storer is used to deposit control word, m * 2 FIFO then as the temporary register storeroom should Pretesting the address date of the required MUX of vector, MUX is then exported corresponding data according to address selection.The capacity of FIFO is set at m * 2.Finite state machine is then finished the logic control function to other each parts.En is an enable signal, and is ready when en output 1 expression demoder, waits for receiving compressed data; Packed data enters decompression circuit from the Data_in end;
The course of work of its decompression circuit is: after the test beginning, FSM at first reads control word from memory, and according to reading the result corresponding address date is write FIFO.If the control word first place is 0, then directly write " 00 " to FIFO; If the control word first place is 1, then continue to read the next bit control word, if next bit is 0, then writes " 10 ", otherwise write " 11 " to FIFO.When writing FIFO at every turn, log
2The m position all adds 1, is written into m time up to FIFO.At this moment, deposit the required m of first a test vector address date among the FIFO in; FSM starts the read pointer RD of FIFO then, address of the every output of FIFO, and MUX is correspondingly exported the one digit number certificate, and with this bit data input m bit shift register.In this process, the shift signal puts 1, log
2The m digit counter keeps count status.When counter is remembered m, represent that the m bit shift register has been write completely, this moment, the read pointer RD of FIFO pointed to last data, and the Done2 signal puts 1, and the m bit shift register writes circuit-under-test with test data.
Log in the circuit
2The d digit counter is used for representing the end of a test vector.After m bit data in shift register write circuit-under-test, this counter all added 1 operation, and the Reset3 signal enabling will make the read pointer of FIFO make zero to carry out the operation of next circulation m bit data simultaneously.Work as log
2D digit counter meter is full, represents that a test vector finishes, and then FSM will read control word once more from memory, and the address date among the FIFO will be updated, and the decompression process of next test vector begins.
Claims (6)
1. the method for LSI circuit test data and testing power consumption cooperate optimization is characterized in that steps of the method are:
Step 1: with test set T
D={ t
1, t
2... t
nBeing expressed as a two-dimensional matrix, each row is represented a test vector, is total to n test vector, the value that on behalf of a scanning element, each row composed successively, S scanning element altogether; Calculate the compatibility between the column vector, i.e. compatibility between each scanning element in the test set;
Step 2: adopt group's division methods of putting preferential combination principle fully based on isolated point and 2-that scanning element is divided into K1, K2, K3 three class groups, scanning element in each group is fully compatible, for the group that belongs to the K1 class, each group only comprises a scanning element, for the group that belongs to the K2 class, each group only comprises two scanning elements, for the group that belongs to the K3 class, comprise three scanning elements in each group, finally there be A scanning element to put K1 class group under, there be B scanning element to put K2 class group under, have C scanning element to put K3 class group under;
Step 3: the scanning element in K1, K2, the K3 class group is connected respectively, form the scan chain that three classes have " duplicating " mechanism; First kind scan chain is the same with the plain scan chain, and is only that each scanning element is connected in series; The second class scan chain comes down to a scan chain group, be formed in parallel by two scan chains, every scan chain forms by each scanning element is connected in series respectively, wherein the scan input end of article one scan chain is as the scan input end (Scan_in) of this class scan chain, article one, the scanning output end of scan chain is as the scanning output end 1 (Scan_out 1) of this class scan chain, and the scanning output end of second scan chain is as the scanning output end 2 (Scan_out 2) of this class scan chain; In this class scan chain architecture, article two, the scanning element of same position belongs to a group on the scan chain, and this group belongs to K2 class group, connect with a triple gate between two compatible scanning elements of same position, and the Enable Pin of all triple gates links together, as the control end of the replicate run (copy) of such scan chain; When reality was tested, the scanning migration process was at first carried out on article one scan chain, and article one scan chain obtains test data; Subsequently, control copy end is carried out " duplicating " operation, and promptly all triple gates enable, thereby the second scan chain has obtained the test data identical with article one scan chain; Scanning is shifted out process and is then carried out on two scan chains respectively; The 3rd class scan chain in fact also is a scan chain group, be formed in parallel by three scan chains, every scan chain all forms by each scanning element is connected in series, wherein the scan input end of a scan chain is as the scan input end (Scan_in) of this class scan chain, article one, the scanning output end of scan chain is as the scanning output end 1 (Scan_out 1) of this class scan chain, the scanning output end of second scan chain is as the scanning output end 2 (Scan_out 2) of this class scan chain, and the scanning output end of the 3rd scan chain is as the scanning output end 3 (Scan_out 3) of this class scan chain; In this class scan chain architecture, article three, the scanning element of same position belongs to a group on the scan chain, and this group belongs to K3 class group, connect with two triple gates between three compatible scanning elements of same position, and the Enable Pin of all triple gates links together, as the control end of the replicate run (copy) of such scan chain; When reality was tested, the scanning migration process was at first carried out on a scan chain, and this scan chain obtains test data; Subsequently, control copy end is carried out " duplicating " operation, and promptly all triple gates enable, thereby the two other scan chain has obtained the test data identical with article one scan chain; Scanning is shifted out process and is then carried out on three scan chains respectively;
Step 4: the test vector collection is adjusted in the variation according to scan chain architecture;
Step 5: adopt and the repeated data in the test set are compressed the test set T after finally being compressed based on the method for repeated data compression
E
Step 6: when testing, the test data after the compression is recovered through a decompression circuit fully, and each the bar scan chain that enters then in the circuit-under-test is tested.
2. according to a kind of LSI circuit test data described in the claim 1 and the method for testing power consumption cooperate optimization, it is characterized in that the compatibility between the column vector in the described step 1 is meant for two column vector s
iAnd s
jIf, s
iAnd s
jTwo data of middle same position are identical, perhaps have at least one to be don't-care bit " X ", claim that then these two column vectors are compatible, and promptly the scanning element of these two column vector correspondences is compatible.
3. according to a kind of LSI circuit test data described in the claim 1 and the method for testing power consumption cooperate optimization, it is characterized in that the employing described in the step 2 based on group's division methods that isolated point and 2-put preferential combination principle fully is:
If: (C E) represents each scanning element and correlativity thereof to non-directed graph G=, and the vertex set C of figure represents S scanning element, if having compatibility relation between certain two scanning element, has a limit between then corresponding two summits; If subgraph H=(S, the E of G
H) in all have a limit between any two summits, claim that then subgraph H is the complete subgraph of G, the vertex set S of subgraph H is the group of G; Three definition are here arranged:
Definition one:, then claim this point to be the public neighbours on this limit if certain summit all has the limit to link to each other with two end points on certain bar limit;
Definition two:, claim that then this point is an isolated point if certain a bit has only a limit to link to each other with it;
Define three: if certain point has n adjacent node, and this n some formation complete subgraph, claim that then this point is a n-point fully;
Its group's division methods of putting preferential combination principle fully based on isolated point and 2 one is based on repeatedly circulation, each preferential isolated point and adjacent node or 2-thereof of merging put and public neighbours fully, all summits all are divided and enter corresponding group in figure: be meant several summits are merged here and delete these several summits and limit that all are coupled in former figure G, form new figure, these several summits form a group, and group's partitioning algorithm concrete steps are as follows:
Step 1, set up non-directed graph G=(C, E);
Isolated point and adjacent node thereof among step 2, the merging non-directed graph G, the group after the merging is classified as K2 class group, upgrades G;
2-among step 3, the merging G is point fully, and the group after the merging is classified as K3 class group, upgrades G;
Step 4, select a limit arbitrarily, select two summits on its public neighbours and this limit to merge, and the group that will obtain after will merging is classified as K3 class group, renewal G;
If have the limit among the step 5 figure G, forward step 1 to; Otherwise group's partitioning algorithm finishes, and K1 class group is included into as a group in each remaining summit;
Behind the group's of execution partitioning algorithm, finally there be A summit to put K1 class group under, have B summit to put K2 class group under, have C summit to put K3 class group under, promptly have A scanning element to put K1 class group under, have B scanning element to put K2 class group under, have C scanning element to put K3 class group under.
4. according to a kind of LSI circuit test data described in the claim 1 and the method for testing power consumption cooperate optimization, it is characterized in that the difference method of attachment of the scanning element in the K1 described in the step 3, K2, the K3 class group is:
With scan chain architecture the scanning element in K1, K2, the K3 class group is connected respectively, form three class scan chains; If circuit-under-test has m scan input end (Scan_in), there be A scanning element to put K1 class group under in the step 2, there be B scanning element to put K2 class group under, there be C scanning element to put K3 class group under, then the length d of every scanning amount equates, and satisfies:
" rounding " computing in the following formula in [] expression mathematics.
5. according to a kind of LSI circuit test data described in the claim 1 and the method for testing power consumption cooperate optimization, it is characterized in that the variation according to scan chain architecture described in the step 4 adjusts the method for test vector collection and be: the test vector collection of first kind scan chain remains unchanged; The test vector collection of the second class scan chain only keeps the single chain data after the compatible optimization; The test vector collection of the 3rd class scan chain only keeps the single chain data after the compatible optimization.
6. according to a kind of LSI circuit test data described in the claim 1 and the method for testing power consumption cooperate optimization, it is characterized in that the method for the repeated data compression described in the step 5 is:
Wherein repeated data are meant on some scan chain, in test vector cycle on this scan chain the test data of all scanning elements all be " 0 " or all be " 1 "; If circuit-under-test has m scan input end (Scan_in), the test vector collection is made up of n vector, and execution in step three back scan chain length are d, and then each vector in the test set can be regarded as by m sub vectorial the composition, and each subvector length is d; The concrete steps of its method are as follows:
Step 1: be the don't-care bit of data centralization " X " assignment, occurrence equals the last bit data value of this bit data;
Step 2: according to the data characteristics of subvector, promptly repeated data or general data are for each subvector is determined control word;
Step 3: repeated data are rejected from data centralization;
Step 4: the data after the arrangement compression are unit with the vector, the data of multichain form are put in order according to the sequencing that enters the circuit-under-test scan chain be the form of single data stream.
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