CN112363045A - Chip scanning test method and device, processor chip and server - Google Patents
Chip scanning test method and device, processor chip and server Download PDFInfo
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Abstract
One or more embodiments of the invention disclose a chip scanning test method, a device, a processor chip and a server. The chip scanning test method comprises the following steps: acquiring a scanning test vector of a target chip; detecting whether the sequence of a preset partial vector in the scanning test vector meets a preset optimal vector sequence; and in response to the sequence of the preset partial vectors in the scanning test vectors meeting the optimal vector sequence, performing Automatic Test Equipment (ATE) on-machine test on the target chip based on the scanning test vectors. The method can shorten the period of chip scanning test.
Description
Technical Field
The invention relates to the technical field of automatic chip testing, in particular to a chip scanning testing method and device, a processor chip and a server.
Background
With the increasing integration of digital chips and the increasing number of transistors in integrated circuits, the Design work of DFT (Design For Test, circuit designed For chip Test) is from single person in the past to multi-person cooperation. Meanwhile, in order to ensure the coverage of product testing, the number of SCAN ATPG (Automatic Test Pattern Generation) ATE (Automatic Test Equipment) vectors generated by an EDA (Electronic Design Automation) tool and the capacity of a single vector are increasing. Therefore, test failures due to quality problems of the vectors themselves are increasing. In actual testing, due to the natural difference between the simulation environment and the real chip testing environment, the quality of SCAN ATPG ATE vector generated by DFT engineer often cannot satisfy the optimization condition of the ATE tester after silicon, and the increasingly tightened verification period after silicon is a great challenge for both DFT engineer and ATE tester. Therefore, how to ensure the optimization of the pre-silicon SCAN ATPG ATE vector will become more and more important.
In a new typical large-scale digital integrated circuit product development process, a SCAN test is the most important DFT design scheme for large-scale digital integrated circuit testing because of high coverage, easy defect diagnosis and positioning, and good test effect. Among them, SCAN testing is a DFT approach that utilizes EDA tools to insert SCAN CHAIN (SCAN chains) into digital circuits for testing digital circuit combinations and sequential circuits. In practical applications in the past, the period of SCAN ATPG ATE test vector generation will occupy 1/2 of the whole project period, and therefore, the quality of the vector will directly affect the marketing period of the product. When different DFT engineers complete a batch of SCAN ATPG ATE vectors for delivery, it is difficult for the ATE test engineer to check the vector contents off-line before the chip is shipped to the factory (before the silicon), especially when the total number of vectors is large and there are timing-related problems. It is possible that a test engineer will not find an error on the ATE for verification until after the chip is shipped (post-silicon), which is the most valuable for the product market cycle. If some systematic errors exist in some SCAN vector steps or the vector timing cannot reach the optimal conditions for the ATE production test, the DFT engineer will have to re-modify and re-generate new vectors in the post-silicon working stage, generally speaking, a new SCAN vector generation and simulation will take 1-2 weeks, and if there are more error vector sets, it will take more time, resulting in a longer test period for the chip.
Disclosure of Invention
In view of this, embodiments of the present invention provide a chip scan test method, an apparatus, a processor chip and a server, which can effectively shorten a chip scan test period.
One or more embodiments of the present invention provide a chip scan test method, including: acquiring a scanning test vector of a target chip; detecting whether the sequence of a preset partial vector in the scanning test vector meets a preset optimal vector sequence; and in response to the sequence of the preset partial vectors in the scanning test vectors meeting the optimal vector sequence, performing Automatic Test Equipment (ATE) on-machine test on the target chip based on the scanning test vectors.
Optionally, the method further includes: before obtaining a scanning test vector of a target chip, carrying out ATE on-machine test on the target chip through an initial scanning test vector to obtain a test result; adjusting the vector sequence of a preset part of vectors in the initial scanning test vector according to the test result, and performing ATE on-board test on the target chip again through the adjusted scanning test vector until the test result meets a preset condition to obtain the optimal vector sequence; and generating an optimal vector sequence detection algorithm according to the optimal vector sequence.
Optionally, detecting whether an order of a preset partial vector in the scan test vector meets a preset optimal vector order, including: and calling the optimal vector sequence detection algorithm to detect whether the sequence of the preset partial vectors in the scanning test vectors meets the optimal vector sequence.
Optionally, the method further includes: and sending a prompt message for regenerating the scanning test vector in response to the fact that the sequence of the preset partial vector in the scanning test vector does not meet the optimal vector sequence after detecting whether the sequence of the preset partial vector in the scanning test vector meets the preset optimal vector sequence.
Optionally, the preset partial vector is a vector that is not generated by an electronic design automation EDA algorithm in the scan test vector.
One or more embodiments of the present invention provide a chip scan test apparatus, including: the acquisition module is configured to acquire a scanning test vector of a target chip; a detection module configured to detect whether an order of a preset partial vector in the scan test vector satisfies a preset optimal vector order; and the first test module is configured to respond to the sequence of the preset partial vectors in the scanning test vectors meeting the optimal vector sequence, and perform Automatic Test Equipment (ATE) on-machine test on the target chip based on the scanning test vectors.
Optionally, the apparatus further comprises: the second testing module is configured to perform ATE on-board testing on the target chip through the initial scanning test vector before the scanning test vector of the target chip is acquired, so as to obtain a testing result; the third testing module is configured to adjust the vector sequence of a preset part of vectors in the initial scanning testing vectors according to the testing result, and perform the ATE on-board test on the target chip again through the adjusted scanning testing vectors until the testing result meets a preset condition to obtain the optimal vector sequence; a generating module configured to generate an optimal vector order detection algorithm according to the optimal vector order.
Optionally, the detection module is configured to: and calling the optimal vector sequence detection algorithm to detect whether the sequence of the preset partial vectors in the scanning test vectors meets the optimal vector sequence.
Optionally, the apparatus further comprises: and the prompting module is configured to send out a prompting message for regenerating the scanning test vector in response to that the sequence of the preset partial vector in the scanning test vector does not meet the optimal vector sequence after detecting whether the sequence of the preset partial vector in the scanning test vector meets the preset optimal vector sequence.
Optionally, the preset partial vector is a vector that is not generated by an electronic design automation EDA algorithm in the scan test vector.
One or more embodiments of the invention provide a processor chip comprising: at least one processor core, a cache; the processor core is used for executing any one of the chip scanning test methods.
One or more embodiments of the present invention provide a server, including: the device comprises a shell, a processor, a memory, a circuit board and a power circuit, wherein the circuit board is arranged in a space enclosed by the shell, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to each circuit or device of the electronic apparatus; the memory is used for storing executable program codes; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, and is used for executing any one of the chip scanning test methods.
In the chip scan testing method according to one or more embodiments of the present invention, it is detected at the pre-silicon stage of the chip whether the sequence of the preset partial vectors in the scan test vectors of the chip to be tested satisfies the preset optimal vector sequence, so as to ensure the optimization of the scan test vectors obtained at the pre-silicon stage of the chip, avoid the problem that the scan test vectors need to be generated again due to the quality problem of the scan test vectors at the post-silicon stage of the chip, and shorten the post-silicon test time of the chip.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flow diagram illustrating a method for chip scan testing in accordance with one or more embodiments of the invention;
FIG. 2A shows a chip scan test flow diagram;
FIG. 2B is a flow diagram illustrating a method for chip scan testing in accordance with one or more embodiments of the invention;
FIG. 3A is a schematic diagram illustrating results of a chip scan test according to one or more embodiments of the invention;
FIG. 3B is a diagram illustrating results of a chip scan test according to one or more embodiments of the invention;
FIG. 4 is a schematic diagram illustrating an exemplary configuration of a chip scan test apparatus according to one or more embodiments of the present invention;
FIG. 5 is a schematic diagram of a chip according to one or more embodiments of the invention;
fig. 6 is a schematic diagram illustrating a configuration of a server according to one or more embodiments of the invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the pre-silicon stage of the chip, different DFT engineers usually assign different sequences of special vectors (here, the special vectors are used to represent the scan test vectors assigned by the DFT engineers) to different vector groups, and the randomness is high. Due to the limitations of EDA tools, it is generally difficult to detect them with EDA simulation tools if these special vector sequences are problematic or inconsistent.
In addition, due to the difference between the simulation environment and the real test environment, it is difficult for the DFT engineer to directly define an optimized special vector sequence during pre-silicon ATPG of the chip. In post-silicon on-machine verification of a chip, the SCAN ATPG ATE vector often cannot be optimized for actual ATE on-machine testing at one time, and often requires one or more iterations.
Due to uncertain factors contained in the special vector, the random error introduced in the later silicon stage of the chip is strong, and the cost is high. If the Test is unstable, the yield is low, if SCAN CHAIN is too slow in turning speed, the difference between the Test times is 10 times, etc., which is not good for TTR (Test Time Reduction), resulting in increased cost of mass production Test of chips.
The DFT engineer may take too long to regenerate new SCAN vectors at the post-silicon stage of the chip, which may extend the chip test cycle.
DFT SCAN ATE the vector verification work is performed at the post-silicon stage of the chip, which is not beneficial to shortening the on-chip market period.
One or more embodiments of the present invention provide a chip scan testing method, and fig. 1 is a flowchart illustrating a chip scan testing method according to one or more embodiments of the present invention, as shown in fig. 1, where the method includes:
step 101: acquiring a scanning test vector of a target chip;
the target chip may be a chip in a pre-silicon stage, and the scan test vector of the target chip obtained in step 101 may be, for example, a scan test vector submitted by a DFT engineer in the pre-silicon stage of the chip.
Step 102: detecting whether the sequence of a preset partial vector in the scanning test vector meets a preset optimal vector sequence;
in step 102, since some preset partial vectors that are crucial to the chip test result often exist in the scan test vector, when these vectors exist in a certain sequence, a better test result can be obtained by performing ATE on-board test on the chip, so that it can be detected whether the sequence of the preset partial vectors in the scan test vector submitted by the DFT engineer in the pre-silicon stage of the chip meets the preset optimal vector sequence.
Step 103: and in response to the sequence of the preset partial vectors in the scanning test vectors meeting the optimal vector sequence, performing Automatic Test Equipment (ATE) on-machine test on the target chip based on the scanning test vectors.
In step 103, after determining that the order of the predetermined partial vectors in the scan test vectors of the pre-silicon stage of the chip satisfies the predetermined optimal vector order, the scan test vectors can be ensured to pass the ATE on-board basic condition test and the ATE on-board optimal condition test, so as to ensure that the optimal scan test vectors are obtained at the pre-silicon stage of the chip. Taking fig. 2A and fig. 2B as an example, fig. 2A shows a chip scan test flow, wherein two dotted frames from top to bottom in fig. 2A are a pre-silicon stage of a chip and a post-silicon stage of the chip, respectively. Fig. 2B shows a chip testing process according to one or more embodiments of the present invention, in which two dotted line boxes from top to bottom in fig. 2B are a pre-silicon stage of a chip and a post-silicon stage of the chip, respectively. In fig. 2A, after the generated scan test vector is submitted to the AET test engineer, the ATE on-board basic condition test is performed, and the ATE on-board optimal condition test is performed after the ATE on-board basic condition test is passed, and the test can be completed after both tests are passed. Since the sequence of the scan test vector is not detected after the scan test vector is generated in the scheme of fig. 2A, it cannot be ensured that the scan test vector can pass the ATE on-board basic condition test or the ATE on-board optimal condition test, and if the scan test vector cannot pass the two tests, the scan test vector needs to be regenerated in the post-silicon stage of the chip, which obviously prolongs the post-silicon test time of the chip. In the scheme shown in fig. 2B, after the scan test vector is generated, it is detected whether the sequence of the vector meets the preset optimal vector sequence, so that the optimization of the scan test vector is ensured to be realized at the pre-silicon stage of the chip, and the vector can be detected by the ATE on-machine basic conditions and the ATE on-machine optimal conditions. .
The chip scanning test method of one or more embodiments of the present invention detects whether the order of the preset partial vectors in the scanning test vectors of the chip to be tested satisfies the preset optimal vector order at the pre-silicon stage of the chip, ensures the optimization of the scanning test vectors obtained at the pre-silicon stage of the chip, avoids the problem that the scanning test vectors need to be generated again due to the quality problem of the scanning test vectors at the post-silicon stage of the chip, and shortens the post-silicon test time of the chip, thereby shortening the chip test time and improving the yield of the mass production of the chip.
In one or more embodiments of the present invention, the chip scan test method may further include:
before obtaining a scanning test vector of a target chip, carrying out ATE on-machine test on the target chip through an initial scanning test vector to obtain a test result; adjusting the vector sequence of a preset part of vectors in the initial scanning test vector according to the test result, and performing ATE on-board test on the target chip again through the adjusted scanning test vector until the test result meets a preset condition to obtain the optimal vector sequence; the adjusting the vector order of the preset partial vectors in the initial scan test vector according to the test result may be, for example, adjusting the order of vectors in the initial scan test vector that are not generated by the EDA algorithm. The preset condition may be, for example, that the ratio of the result of the test to the total test result reaches a preset threshold. And generating an optimal vector sequence detection algorithm according to the optimal vector sequence. For example, a detection algorithm may be written based on the obtained optimal vector order, and the detection algorithm may be used to detect whether a certain segment of the test vectors satisfies the optimal vector order, i.e., whether the vector order of a certain segment of the test vectors is consistent with the optimal vector order. The detection algorithm may be stored in the form of a piece of executable code. Here, the principle of obtaining the optimal vector order will be briefly described with reference to fig. 3A and 3B. In the coordinate system shown in fig. 3A and 3B, the abscissa represents the test speed (MHZ), the ordinate represents the test voltage (V), fig. 3A shows the test result obtained by automatically testing the target chip based on the original scan test vector, wherein the part S1 represents the result of passing the test, the part S2 represents the result of failing the test, and fig. 3B shows the test result obtained by automatically testing the target chip based on the adjusted scan test vector, wherein the part S1 'represents the result of passing the test, and the part S2' represents the result of failing the test, comparing fig. 3A and 3B shows that the proportion of the result of passing the test in the total test result obtained by automatically testing the target chip based on the adjusted scan test vector is significantly improved.
In one or more embodiments of the present invention, detecting whether an order of a preset partial vector in the scan test vector satisfies a preset optimal vector order may include:
and calling the optimal vector sequence detection algorithm to detect whether the sequence of the preset partial vectors in the scanning test vectors meets the optimal vector sequence. For example, after the optimal vector detection algorithm is generated as described above, the algorithm may be embedded in detection software to ensure that the scan test vectors are optimized prior to subjecting the target chip to ATE on-board testing. The optimal vector sequence detection algorithm may, for example, compare each vector in the optimal vector with each vector in the scan test vectors to be detected in sequence to determine whether the vector sequence of the scan test vectors to be detected is consistent with the vector sequence of the optimal vector.
In one or more embodiments of the present invention, the chip scan test method may further include: and sending a prompt message for regenerating the scanning test vector in response to the fact that the sequence of the preset partial vector in the scanning test vector does not meet the optimal vector sequence after detecting whether the sequence of the preset partial vector in the scanning test vector meets the preset optimal vector sequence. After learning the prompt message, the DFT engineer may regenerate the scan test vector at the pre-silicon stage of the chip, and then detect the sequence of the preset partial vectors in the regenerated scan test vector until the regenerated scan test vector passes the detection, i.e., the purpose of obtaining the optimized scan test vector at the pre-silicon stage of the chip is achieved.
In one or more embodiments of the invention, since scan testing of a chip is a structural test (a test type developed by designers for test paths, stimulus signals and response signals by test engineers), most of its scan test vectors are automatically generated by EDA tools using specific EDA algorithms based on hypothetical defect models, but the vector order of some non-EDA algorithms is self-specified by DFT engineers. While there may be multiple DFT engineers responsible for DFT design, the assigned vector sequence of each DFT engineer may be different, the quality of the vector contents is not easy to detect, but the vector contents are one of the important factors affecting the chip scan test. Based on this, the preset partial vector in the scan test vector in one or more embodiments of the present invention may be a vector in the scan test vector that is not generated by the EDA algorithm.
In one or more embodiments of the present invention, when detecting the sequence of scan test vectors of a series of chips with similar features, for example, a certain generation of chip products, an optimal vector detection algorithm generated in advance in the above manner may be utilized, that is, the series of chips may correspond to the same optimal vector detection algorithm.
Fig. 4 is a block diagram illustrating an apparatus for scan testing a chip according to one or more embodiments of the present invention, and as shown in fig. 4, the apparatus 40 includes:
an obtaining module 41 configured to obtain a scan test vector of a target chip;
a detection module 42 configured to detect whether an order of a preset partial vector in the scan test vector satisfies a preset optimal vector order;
a first testing module 43, configured to perform automatic test equipment ATE on-machine testing on the target chip based on the scan test vector in response to the order of preset partial vectors in the scan test vector satisfying the optimal vector order.
In one or more embodiments of the present invention, the chip scan test apparatus may further include:
the second testing module is configured to perform ATE on-board testing on the target chip through the initial scanning test vector before the scanning test vector of the target chip is acquired, so as to obtain a testing result;
the third testing module is configured to adjust the vector sequence of a preset part of vectors in the initial scanning testing vectors according to the testing result, and perform the ATE on-board test on the target chip again through the adjusted scanning testing vectors until the testing result meets a preset condition to obtain the optimal vector sequence;
a generating module configured to generate an optimal vector order detection algorithm according to the optimal vector order.
In one or more embodiments of the invention, the detection module may be configured to:
and calling the optimal vector sequence detection algorithm to detect whether the sequence of the preset partial vectors in the scanning test vectors meets the optimal vector sequence.
In one or more embodiments of the present invention, the chip scan test apparatus may further include:
and the prompting module is configured to send out a prompting message for regenerating the scanning test vector in response to that the sequence of the preset partial vector in the scanning test vector does not meet the optimal vector sequence after detecting whether the sequence of the preset partial vector in the scanning test vector meets the preset optimal vector sequence.
In one or more embodiments of the present invention, the preset partial vector is a vector that is not generated by an EDA algorithm in the scan test vector.
One or more embodiments of the present invention further provide a processor chip, and fig. 5 is a schematic diagram of a processing chip according to one or more embodiments of the present invention, as shown in fig. 5, the processing chip 50 includes: at least one processor core 51 and a cache 52; the processor core 51 is configured to execute any one of the chip scan test methods described above.
One or more embodiments of the present invention also provide a server, including: the device comprises a shell, a processor, a memory, a circuit board and a power circuit, wherein the circuit board is arranged in a space enclosed by the shell, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to each circuit or device of the electronic apparatus; the memory is used for storing executable program codes; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, and is used for executing any one of the chip scanning test methods.
Accordingly, as shown in fig. 6, a server provided by one or more embodiments of the present invention may include: the electronic device comprises a shell 61, a processor 62, a memory 63, a circuit board 64 and a power circuit 65, wherein the circuit board 64 is arranged inside a space enclosed by the shell 61, and the processor 62 and the memory 63 are arranged on the circuit board 64; a power supply circuit 65 for supplying power to each circuit or device of the electronic apparatus; the memory 63 is used to store executable program code; the processor 62 executes a program corresponding to the executable program code by reading the executable program code stored in the memory 63, so as to execute any one of the chip scan test methods provided by the foregoing embodiments.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term "comprising", without further limitation, means that the element so defined is not excluded from the group consisting of additional identical elements in the process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments.
In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
For convenience of description, the above devices are described separately in terms of functional division into various units/modules. Of course, the functionality of the units/modules may be implemented in one or more software and/or hardware implementations of the invention.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (12)
1. A chip scanning test method is characterized by comprising the following steps:
acquiring a scanning test vector of a target chip;
detecting whether the sequence of a preset partial vector in the scanning test vector meets a preset optimal vector sequence;
and in response to the sequence of the preset partial vectors in the scanning test vectors meeting the optimal vector sequence, performing Automatic Test Equipment (ATE) on-machine test on the target chip based on the scanning test vectors.
2. The method of claim 1, further comprising:
before obtaining a scanning test vector of a target chip, carrying out ATE on-machine test on the target chip through an initial scanning test vector to obtain a test result;
adjusting the vector sequence of a preset part of vectors in the initial scanning test vector according to the test result, and performing ATE on-board test on the target chip again through the adjusted scanning test vector until the test result meets a preset condition to obtain the optimal vector sequence;
and generating an optimal vector sequence detection algorithm according to the optimal vector sequence.
3. The method of claim 2, wherein detecting whether the order of the predetermined partial vectors in the scan test vector satisfies a predetermined optimal vector order comprises:
and calling the optimal vector sequence detection algorithm to detect whether the sequence of the preset partial vectors in the scanning test vectors meets the optimal vector sequence.
4. The method of claim 1, further comprising:
and sending a prompt message for regenerating the scanning test vector in response to the fact that the sequence of the preset partial vector in the scanning test vector does not meet the optimal vector sequence after detecting whether the sequence of the preset partial vector in the scanning test vector meets the preset optimal vector sequence.
5. The method according to any of claims 1 to 4, wherein the predetermined partial vectors are those of the scan test vectors that are not generated by an EDA algorithm.
6. A chip scanning test device, comprising:
the acquisition module is configured to acquire a scanning test vector of a target chip;
a detection module configured to detect whether an order of a preset partial vector in the scan test vector satisfies a preset optimal vector order;
and the first test module is configured to respond to the sequence of the preset partial vectors in the scanning test vectors meeting the optimal vector sequence, and perform Automatic Test Equipment (ATE) on-machine test on the target chip based on the scanning test vectors.
7. The apparatus of claim 6, further comprising:
the second testing module is configured to perform ATE on-board testing on the target chip through the initial scanning test vector before the scanning test vector of the target chip is acquired, so as to obtain a testing result;
the third testing module is configured to adjust the vector sequence of a preset part of vectors in the initial scanning testing vectors according to the testing result, and perform the ATE on-board test on the target chip again through the adjusted scanning testing vectors until the testing result meets a preset condition to obtain the optimal vector sequence;
a generating module configured to generate an optimal vector order detection algorithm according to the optimal vector order.
8. The apparatus of claim 7, wherein the detection module is configured to:
and calling the optimal vector sequence detection algorithm to detect whether the sequence of the preset partial vectors in the scanning test vectors meets the optimal vector sequence.
9. The apparatus of claim 6, further comprising:
and the prompting module is configured to send out a prompting message for regenerating the scanning test vector in response to that the sequence of the preset partial vector in the scanning test vector does not meet the optimal vector sequence after detecting whether the sequence of the preset partial vector in the scanning test vector meets the preset optimal vector sequence.
10. The apparatus according to any of claims 6 to 9, wherein the predetermined partial vectors are those of the scan test vectors that are not generated by an Electronic Design Automation (EDA) algorithm.
11. A processor chip, comprising: at least one processor core, a cache;
the processor core is used for executing the chip scanning test method of any one of the preceding claims 1-5.
12. A server, comprising: the device comprises a shell, a processor, a memory, a circuit board and a power circuit, wherein the circuit board is arranged in a space enclosed by the shell, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to each circuit or device of the electronic apparatus; the memory is used for storing executable program codes; the processor executes a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the chip scan test method of any one of the preceding claims 1 to 5.
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