CN114325294A - Test method and device - Google Patents
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Abstract
The embodiment of the invention provides a test method and a test device, which are applied to the test of a target chip, and the method comprises the following steps: obtaining a test vector required by testing the target chip; wherein the number of the test vectors is at least one; respectively extracting scanning port information from the test port information of each test vector; according to a preset compression multiple, respectively compressing and format converting the scanning port information of each test vector to obtain a target test vector corresponding to each test vector; and testing the target chip by adopting the target test vector. The embodiment of the invention extracts the scanning port information from the port information of the test vector and compresses the scanning port information part, thereby reducing the test depth of the test vector, reducing the storage space of the test vector in ATE and further reducing the test cost.
Description
Technical Field
The embodiment of the invention relates to the technical field of integrated circuits, in particular to a test method and a test device.
Background
With the continuous development of integrated circuit design in the nanometer field, the performance of the chip is more and more powerful. But the increasing number of nanoscale faults and the faster and faster clocking of chips make Design For Testability (DFT) more and more complex. DFT has become the most important ring in designing Very Large Scale Integration (VLSI) circuits. The most prominent DFT techniques for testing the digital portion of VLSI circuits include scan design techniques and methods of logic built-in self-test, with scan test techniques being the most widely used.
In the related art, the chip testing method comprises the following steps: test vectors aiming at various fault models in a chip are generated through an Automatic Test Pattern Generation (ATPG) tool, the Test vectors are converted into Test vectors in a specific format required by Automatic Test Equipment (ATE), the Test vectors in the specific format are input into a tested module of the chip through the ATE, and an output result of the tested module is compared with an expected stored result, so that whether the tested module of the chip is qualified or not is judged.
However, the test vectors generated by ATPG are all vectors that are directly converted into the specific format required by ATE by the conversion tool, so that the test vectors occupy a large storage space of ATE, thereby resulting in high test cost of the chip.
Disclosure of Invention
The embodiment of the invention provides a test method and a test device, which are used for solving the problems of large occupied depth of a measurement vector and chip measurement cost caused by directly converting the test vector through a conversion tool in the prior art.
A first aspect of an embodiment of the present invention provides a test method, applied to a test on a target chip, including:
obtaining a test vector required by testing the target chip; wherein the number of the test vectors is at least one;
respectively extracting scanning port information from the test port information of each test vector;
according to a preset compression multiple, respectively compressing and format converting the scanning port information of each test vector to obtain a target test vector corresponding to each test vector;
and testing the target chip by adopting the target test vector.
Optionally, before obtaining the target test vector, the method further includes:
respectively extracting non-scanning port information from the port information of each test vector; wherein the non-scanning port information and the scanning port information are different;
and carrying out format conversion on the non-scanning port information, or carrying out compression and format conversion on the non-scanning port information.
Optionally, any one of the test vectors includes description information of input and output states of a logic function; the method for respectively extracting the scanning port information and the non-scanning port information from the test port information of each test vector comprises the following steps:
and aiming at any test vector, extracting scanning port information and non-scanning port information from the port information of the test vector according to the description information of the test vector.
Optionally, the testing the target chip by using the target test vector includes:
inputting the target test vector into the target chip to obtain an output result;
comparing the output result with an expected result to obtain a comparison result;
and judging whether the target chip is qualified or not according to the comparison result.
Optionally, before the scanning port information is extracted from the test port information of each test vector, the method further includes:
according to the function descriptor, splitting each test vector respectively to obtain a configuration part and test port information of each test vector;
modifying the configuration part of each test vector respectively;
according to the preset compression multiple, respectively compressing and format converting the scanning port information of each test vector to obtain a target test vector corresponding to each test vector, including:
and for any test vector, reconstructing the modified configuration part of the test vector and the scan port information after the test vector compression and format conversion to obtain a target test vector corresponding to the test vector.
A second aspect of the embodiments of the present invention provides a test apparatus, which is applied to a test on a target chip, and includes:
the acquisition module is used for acquiring a test vector required by testing the target chip; wherein the number of the test vectors is at least one;
the extraction module is used for extracting scanning port information from the test port information of each test vector;
the processing module is used for respectively compressing and converting the scanning port information of each test vector according to a preset compression multiple to obtain a target test vector corresponding to each test vector;
and the test module is used for testing the target chip by adopting the target test vector.
Optionally, the extracting module is further configured to: before a target test vector is obtained, extracting non-scanning port information from the port information of each test vector; wherein the non-scanning port information and the scanning port information are different;
the processing module is specifically configured to perform format conversion on the non-scanning port information, or perform compression and format conversion on the non-scanning port information.
Optionally, any one of the test vectors includes description information of input and output states of a logic function; the extraction module is specifically configured to:
and aiming at any test vector, extracting scanning port information and non-scanning port information from the port information of the test vector according to the description information of the test vector.
Optionally, the test module is specifically configured to:
inputting the target test vector into the target chip to obtain an output result;
comparing the output result with an expected result to obtain a comparison result;
and judging whether the target chip is qualified or not according to the comparison result.
Optionally, the obtaining module is further configured to:
before scanning port information is extracted from the test port information of each test vector, splitting each test vector according to a function descriptor to obtain a configuration part and test port information of each test vector;
modifying the configuration part of each test vector respectively;
the processing module is further configured to:
and for any test vector, reconstructing the modified configuration part of the test vector and the scan port information after the test vector compression and format conversion to obtain a target test vector corresponding to the test vector.
The embodiment of the invention provides a test method and a test device, which are characterized in that a test vector required by testing a target chip is obtained; wherein the number of the test vectors is at least one; then respectively extracting scanning port information from the test port information of each test vector; according to a preset compression multiple, respectively compressing and format converting the scanning port information of each test vector to obtain a target test vector corresponding to each test vector; and finally, testing the target chip by adopting the target test vector. Because the scanning port information is extracted from the testing port information of the testing vector and occupies most of the whole testing vector space, the scanning port part is compressed, the testing depth of the testing vector is reduced, the storage space occupied by the testing vector in ATE is reduced, and the testing cost is reduced.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a diagram illustrating an application scenario of a testing method according to an exemplary embodiment of the present invention;
FIG. 2 is a schematic flow chart diagram of a testing method in accordance with an exemplary embodiment of the present invention;
FIG. 3 is a schematic flow chart diagram of a testing method according to another exemplary embodiment of the present invention;
FIG. 3-1 is a schematic diagram illustrating splitting of a test vector according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a test apparatus according to an exemplary embodiment of the present invention;
fig. 5 is a schematic structural diagram of a test apparatus according to an exemplary embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In the related art, the chip testing method is that an ATPG tool mainly generates a test vector through a scan test design, and the scan test mainly tests a standard unit in an integrated circuit and mainly comprises a shift stage and a capture stage; in the shift stage, the ATE inputs a test vector into the scanning unit through the scanning port, and then initialization is carried out according to the test vector, namely, a trigger in the chip is set to be in a preset initial state through shifting in and out of the scanning chain, and the scanning unit shifts to obtain a test value of each beat; and in the capturing stage, capturing the test value to the trigger to obtain an output value corresponding to the test value.
However, the test vectors generated by the ATPG tool are all vectors in a specific format required by the ATE directly through the conversion tool, and although the scan test greatly improves the fault coverage, the test vectors occupy a large storage space of the ATE, thereby resulting in high test cost of the chip.
Aiming at the defect, the technical scheme of the invention mainly comprises the following steps: according to the structure of the test vector, the test port information of the test vector is divided into scanning port information and non-scanning port information, the non-scanning port is kept unchanged due to the fact that configuration and observation are carried out through the scanning port in the shifting stage, the shifting stage occupies most of test time of the test vector, the scanning port information occupies a large space in the whole test vector, therefore, the scanning port information and the non-scanning port information contained in the test vector are divided, the scanning port information is compressed, and the storage space of the test vector can be greatly reduced.
Fig. 1 is a diagram illustrating an application scenario of a testing method for an integrated circuit chip according to an exemplary embodiment of the present invention.
As shown in fig. 1, the basic architecture of the application scenario of the test method for an integrated circuit chip provided in this embodiment mainly includes: ATPG tool 101, conversion tool 102, ATE103, and chip 104; the ATPG tool 101 is used for generating test vectors of various fault models required by a test chip; the conversion tool 102 is used to convert the test vectors into vectors in a specific format required by the ATE 103; the ATE103 is configured to perform a scan test on a chip according to a vector in a specific format to determine whether the chip is qualified.
FIG. 2 is a flow chart diagram illustrating a method of testing an integrated circuit chip in accordance with an exemplary embodiment of the present invention; in conjunction with the basic architecture diagram shown in fig. 1, the testing method employed by the embodiment of the present invention mainly involves the stage of processing the test vectors by the conversion tool 102 and the ATE103 in fig. 1.
As shown in fig. 2, the method provided by this embodiment mainly includes the following steps.
S201, obtaining a test vector required by testing the target chip.
Specifically, the test vectors required by the test target chip can be generated by DFT, and the modes of generating the test vectors by DFT are mainly divided into two major categories, namely generating the test vectors by an automatic test vector generation ATPG tool and generating the test vectors by a memory built-in self-test MBIST tool; the test vectors generated by the ATPG tool occupy a large space, and the test vectors generated by the MBIST tool occupy a small space.
Optionally, when the step is implemented specifically, the step is mainly performed on a test vector generation tool with a large occupied space for the generated test vector, that is, the obtained test vector is a test vector generated by an ATPG tool.
In the embodiment of the invention, the number of the acquired test vectors required by the test target chip is at least one; typically, the number of test vectors is plural.
S202, respectively extracting scanning port information from the test port information of each test vector.
Specifically, the test vector is generally divided into two parts, namely a configuration part and a test port information part, wherein the configuration part refers to information for determining the fault type, the test frequencies of the configuration part are different, and the test port information part is mainly description information of the input and output states of the designed logic function. In a specific application, the test port information part can be represented by pattern0-n, where the pattern0-n refers to test pattern scan chain information generated according to the type of fault, and n represents the number of specific scan chains and is a positive integer. The following describes the processing flow of the measurement vector by taking the pattern0-n part as an example to represent the information part of the test port; i.e. the test port information part may contain information representing n scan chains.
Aiming at the same test problem, a plurality of test vectors can be used for testing to verify, and the pattern0-n parts of any two test vectors in the plurality of test vectors are the same; moreover, the test frequencies corresponding to different measurement vectors are different, and the different test frequencies can be represented by the configuration part in the test vectors.
The test process of the multi-core chip is a sub-module test, and different test ports are used for testing different test problems of different modules. Specifically, for any test vector, all test ports in the test vector are not used at the same time; for example, a multi-core chip mainly includes a plurality of functional modules, such as a detection module, a calculation module, an execution module, and a power supply module, and when testing the multi-core chip, corresponding test vectors are generated for problems that may occur in different modules, each test vector includes a plurality of test ports, and the functions corresponding to the different test ports are different. Therefore, the test vector can be subjected to port splitting according to the port use condition in the scanning test process.
Specifically, the scan test is divided into two stages, wherein the first stage is a shift stage, and a trigger in a chip is set to be in a preset initial state through shifting in and out of a scan chain; the second phase is a capture phase, capturing the value to be observed onto the flip-flop. The test port information of the test vector is composed of two parts, namely, a scan test input-output port part (simply referred to as a scan port) and a non-scan test input-output port part (simply referred to as a non-scan port). The scan test input/output port part refers to a port used for shifting a scan chain into and out of a chip in a shift stage of a scan test, and the non-scan test port information refers to a port used for capturing a value to be observed on a trigger in a capture stage of the scan test. In the test process of a test vector, the shift stage is configured and observed through the scanning port, and the shift stage occupies most of test time, so that in a test vector, the ports mainly used are the scanning ports, and the scanning ports occupy most of storage space, so that the test port information of the test vector can be split into scanning port information and non-scanning port information. The scanning port information is used for representing relevant parameters of the scanning port; the non-scanning port information is used for characterizing relevant parameters of the non-scanning port.
And S203, respectively compressing and format converting the scanning port information of each test vector according to a preset compression multiple to obtain a target test vector corresponding to each test vector.
The preset compression multiple can be determined according to the time frame number of the automatic test equipment ATE for testing the chip. For example, a typical ATE includes 8 time frames, and if the scan port information of any test vector requires 4 time frames, the scan port information is compressed by a maximum of one-half of the original compression, i.e., a maximum of 2 times.
Specifically, for any test vector, because the scan port information of the test vector occupies most of the space of the whole test vector, the scan port of the test vector can be compressed and format-converted according to the preset compression multiple, so that the storage space occupied by the test vector can be greatly reduced. Format conversion refers to converting the test vectors into a format that can be directly used by the ATE. Optionally, for all test vectors of the target chip, the same preset compression multiple may be adopted to compress the scan port information of all test vectors; or, for all test vectors of the target chip, respectively compressing the scan port information of each test vector by using different preset compression multiples according to the specific condition of each test vector.
Illustratively, the CPUIP _ TF is a test vector, the scanning port information of the CPUIP _ TF test vector occupies 98% of the space occupied by the CPUIP _ TF test vector, the non-scanning port information occupies 2% of the space occupied by the CPUIP _ TF test vector, if the preset compression multiple is 2 times, the CPUIP _ TF test vector can be compressed to 51% of the original value, and the space occupied by the compressed CPUIP _ TF test vector is reduced by 49%.
And S204, testing the target chip by adopting the target test vector.
Specifically, the target test vector is input into the target chip to obtain an output result; and comparing the output result with an expected result to judge whether the target chip is qualified or not. The target test vector comprises at least one test vector which is processed by compression and format conversion.
In the embodiment, the scanning port information and the non-scanning port information in the test vector are extracted and divided, and the scanning port information is compressed, so that the test depth of the whole test vector is greatly reduced, the occupied space of the test vector is reduced, and the cost of chip testing is further reduced.
Fig. 3 is a flowchart illustrating a testing method of an integrated circuit chip according to another exemplary embodiment of the present invention, and this embodiment further describes the testing method of the integrated circuit chip in detail based on the embodiment illustrated in fig. 2.
As shown in fig. 3, the method provided by this embodiment mainly includes the following steps.
S301, DFT generates test vectors.
Specifically, when a chip is tested, modes of generating test vectors through DFT are mainly divided into two major categories, namely generating test vectors through an automatic test vector generation ATPG tool and generating test vectors through a memory built-in self-test MBIST tool; the test vectors generated by the ATPG tool occupy a large space, and the test vectors generated by the MBIST tool occupy a small space.
In this embodiment, the test vectors generated by the ATPG tool are mainly considered, and because the test method of the multi-core chip at present is mainly a module-by-module test, the test vectors generated by the ATPG tool mainly include several test vectors such as SA, TF, BF, PD, and the like according to the tested fault types, wherein the test vectors with large occupied space are mainly TF and PD.
Illustratively, taking a four-core chip as an example for illustration, the CPU has four cores, namely CPUIP0, CPUIP1, CPUIP2 and CPUIP3, and the vector generated corresponding to each core includes three test vectors, namely PD, TF and SA (compress and internal). As shown in table 1, for convenience of description, only two test vectors, PD and TF, corresponding to four cores, are listed in table 1, and as can be seen from table 1, the TF test vector occupation space of the CPU is 25.964M.
It should be noted that the chip tested in this embodiment is a multi-core chip; for homogeneous cores in a multi-core chip, storing information of a plurality of test vectors corresponding to a target core; the target core is any one of homogeneous cores, and the homogeneous cores refer to the same structure of processor cores of the chip and the same trigger pins; for a multi-core chip with homogeneous cores, because the processor cores of the homogeneous cores have the same structure and the trigger pins are the same, the test vectors of the homogeneous cores corresponding to the same test problem are the same; when the homogeneous cores are stored, only one processor core is selected from the homogeneous cores, and only the test vector of the selected any processor core is stored, so that the space occupied by the test vector is further reduced.
TABLE 1
| Pattern _ name (CPUIP module) | Mem_Used | unit(M) |
| XX_CPUIP0_PD_Internal_Pass1 | 546480 | 0.52116394 |
| XX_CPUIP2_PD_Internal_Pass1 | 546480 | 0.52116394 |
| XX_CPUIP1_PD_Internal_Pass1 | 546480 | 0.52116394 |
| XX_CPUIP3_PD_Internal_Pass1 | 546480 | 0.52116394 |
| XX_CPUIP0_TF_Compress_Pass1 | 6259992 | 5.969993591 |
| XX_CPUIP2_TF_Compress_Pass1 | 6259992 | 5.969993591 |
| XX_CPUIP1_TF_Compress_Pass1 | 6259992 | 5.969993591 |
| XX_CPUIP3_TF_Compress_Pass1 | 6259992 | 5.969993591 |
The first column in table 1 is the name of the pattern0-n part in each test vector, the second column is the memory size occupied by the pattern0-n part in each test vector, and the third column is the space size occupied by the unit vector of the pattern0-n part in each test vector.
S302, the test port information of each test vector is divided, and the scanning port information and the non-scanning port information of each test vector are obtained.
Specifically, each test vector includes description information (hereinafter, referred to as description information) of an input/output state of the logic function; for any one of the test vectors (hereinafter referred to as a test vector a), the test port information of the test vector is divided according to the description information included in the test vector a, and the scanning port information and the non-scanning port information of the test vector a are obtained.
In one embodiment, all test vectors obtain scan port information and non-scan port information in the manner of test vector a: each port information in the test vector A corresponds to description information, when the test vector A is used for carrying out scan test on a certain module in a chip, which ports are used for carrying out shift-in and shift-out of a scan chain in a shift stage, and which ports are used for capturing an observed value into a trigger in a capture stage are distributed according to the description information contained in the test vector A; for example, the description information corresponding to the first port in the test vector a includes "set trigger state", which indicates that the first port is a port used for shifting the scan chain into and out of the detection module in the shift stage, and the first port is divided into scan ports; if the functional description corresponding to the second port in the test vector a includes description information of "capturing the observation value", which indicates that the second port is a port used by a trigger in the detection module to capture the observation value in the capture stage, the second port is divided into non-scanning ports.
Further, before step 302, each test vector may be divided according to the function descriptor, that is, the test vector is divided into two parts, a configuration part and test port information (Pattern 0-n), where the test port information is mainly description of the input/output state of the designed logic function, and since the test process of the multi-core chip is a split-module test, that is, all ports of the test vector are not used at the same time, the ports may be split according to the situation. The test port information of the test vector is composed of two parts, namely, a scan test input-output port part (simply referred to as scan port information) and a non-scan test input-output port part (simply referred to as non-scan port information). Specifically, fig. 3-1 is a schematic diagram of splitting a test vector according to an embodiment of the present application, and as can be seen from fig. 3-1, the test vector is split into a configuration part and a pattern0-n part, and the pattern0-n part is split into scan port information and non-scan port information.
The function descriptor is used for identifying a function corresponding to each parameter in any test vector. Illustratively, for any test vector, two function descriptors, namely a function descriptor a and a function descriptor B, correspond to the test vector, where the function descriptor a represents a configuration part and the function descriptor B represents a pattern0-n part; the test vector comprises a parameter 1, a parameter 2, a parameter 3, a parameter 4 and a parameter 5, wherein a function descriptor corresponding to the parameter 1 is A, function descriptors corresponding to the parameter 1 and the parameter 2 are A, and function descriptors corresponding to the parameter 3, the parameter 4 and the parameter 5 are B; it can be seen that parameters 1 and 2 belong to the configuration part, and parameters 3 to 5 belong to the pattern part. Here, this is only an exemplary case, and the number of parameters included in any test vector in practical application will be larger than that in the above example.
In some embodiments, the test port information of the test vector may also be split according to the primary used port information and the non-primary used port information.
In this embodiment, in order to reduce the occupied space of the vector to the maximum extent, the test port information of the test vector is usually split into the scan port information and the non-scan port information.
And S303, respectively compressing and format converting the scanning port information of each test vector according to a preset compression multiple, and performing format conversion on the non-scanning port information or performing format conversion after compression to obtain a target test vector corresponding to each test vector.
The preset compression multiple may be determined according to the time edge number of the automatic test equipment for testing the chip, for example, the preset compression multiple may be set to be 2 times, 3 times, or 4 times.
Specifically, because the scan port of the test vector occupies most of the space of the whole test vector, the scan port of the test vector can be compressed, so that the storage space occupied by the test vector can be greatly reduced. Because the space occupied by the non-scanning port is very small, the non-scanning port can be directly subjected to format conversion without being compressed.
Optionally, the SCAN PORT (SCAN PORT) information and the non-SCAN PORT (nonscan PORT) information of the test vector are defined by a pin list (pinlist), such as: scan _ Port ═ …'; NOScan _ Port ═ …'.
It can be understood that, for any test vector a, since the description information of each port in the test vector a is logic function description information, and related personnel divide the test vector a into scanning port information and non-scanning port information according to the function description information, when all the scanning port information or the non-scanning port information is obtained to perform compression and format conversion on the scanning port information, the description information needs to be obtained according to the function description information of each port, but the function description information of each port is different, and when the scanning port is compressed and format converted, a section of compression and format conversion code needs to be defined for each scanning port. In this step, the scanning port and the non-scanning port are defined by the pin list, so that when the scanning port information and the non-scanning port information are compressed and format converted, the compression parameters and the format conversion parameters are respectively set directly by the pin list definitions corresponding to the scanning port information and the non-scanning port information. All the scanning port information and the non-scanning port information can be quickly acquired through the pin list definition of the scanning port information and the non-scanning port information, so that the time is saved, and the efficiency is improved.
Optionally, as shown in fig. 3-1, the compressing process performed on the pattern0-n portion includes: and performing first compression processing on the scanning port information in the pattern0-n parts, and performing second compression processing on the non-scanning port information in the pattern0-n parts, wherein the compression multiple adopted by the second compression processing is larger than that adopted by the first compression processing. In the embodiment, the pattern0-n part of the test vector is divided into the scanning port information and the non-scanning port information, the non-scanning part with small influence on the test result is compressed by a larger multiple, and the scanning part is compressed by a smaller multiple, so that the accuracy of the test result is further improved, and the space occupied by the test vector is saved.
Further, the configuration part of each test vector is modified respectively; and for any test vector, reconstructing the modified configuration part of the test vector and the scan port information after the test vector compression and format conversion to obtain a target test vector corresponding to the test vector. The modification of the test vector configuration part refers to modification of a configuration file, for example, modification of the identifier of the processor core, and modification of the processor core No. 0 to the processor core No. 2.
Optionally, reconstructing, for any test vector, the configuration part after the test vector is modified, and the scan port information after the test vector compression and format conversion includes: and aiming at any test vector, splicing the modified configuration part of the test vector and the compressed and format-converted scanning port information in a preset mode, and synthesizing and updating the test vector.
For example, assume that any test vector A contains n scan ports (denoted as A, respectively)1、A2…An) Information, m non-scanning ports (denoted B respectively)1、B2…Bm) When compressing and format converting each port, the following information needs to be defined:
"A1_Port""A1_Port_PT,Sync,1,2"；
…
"An_Port""An_Port_PT,Sync,1,2"；
"B1_Port""B1_Port,Sync,1,1"；
…
"Bm_Port""Bm_Port,Sync,1,1"。
in this step, after the SCAN PORT (SCAN PORT) information and the non-SCAN PORT (nonscan PORT) information of the test vector a are defined by the pin list (pinlist), the preset compression multiple is set to 2 times, the SCAN PORT information of the test vector a is compressed and format-converted, the non-SCAN PORT information is directly converted, and the following modes are implemented:
"Scan_Port""Scan_Port_PT,Sync,1,2"；
"NOScan_Port""NOScan_Port,Sync,1,1"。
wherein, 2 in "Sync, 1, 2" represents that the compression multiple is 2 times, and "Sync, 1, 2" represents that the scanning port information is compressed to one half of the original one. "Sync, 1, 1" indicates that the non-scanned port information is compressed by a factor of 1, i.e., not compressed.
In one possible embodiment, not only the scanning port information but also the non-scanning port information may be compressed, and the compression multiple may be determined according to actual conditions.
It should be noted that, the formats of the test vectors generated by DFT mainly include four types: STIL, VCD, EVCD, WGL. However, none of the four formats of test vectors can be used directly on an ATE machine, and the test vectors need to be converted into the specific format of vectors required by the machine.
S304, inputting the target test vector into a unit to be tested in the target chip to obtain an output result.
S305, comparing the output result with an expected result to judge whether the unit to be tested in the target chip is qualified.
In the embodiment, the scanning port and the non-scanning port in the port part of the test vector are divided, and the scanning port is compressed, so that the test depth of the whole test vector is greatly reduced, the occupied space of the test vector is reduced, and the cost of chip test is further reduced.
Fig. 4 is a schematic structural diagram of a test apparatus according to an exemplary embodiment of the present invention.
As shown in fig. 4, the apparatus provided in this embodiment includes: an acquisition module 401, an extraction module 402, a processing module 403 and a test module 404; the obtaining module 401 is configured to obtain a test vector required for testing the target chip; wherein the number of the test vectors is at least one; an extracting module 402, configured to extract scanning port information from the test port information of each test vector; the processing module 403 is configured to compress and format-convert the scan port information of each test vector according to a preset compression multiple, to obtain a target test vector corresponding to each test vector; a testing module 404, configured to test the target chip by using the target test vector.
Further, the extraction module is further configured to: before a target test vector is obtained, extracting non-scanning port information from the port information of each test vector; wherein the non-scanning port information and the scanning port information are different;
the processing module is specifically configured to perform format conversion on the non-scanning port information, or perform compression and format conversion on the non-scanning port information.
Furthermore, any one of the test vectors includes description information of input and output states of the logic function; the extraction module is specifically configured to:
and aiming at any test vector, extracting scanning port information and non-scanning port information from the port information of the test vector according to the description information of the test vector.
Further, the test module is specifically configured to:
inputting the target test vector into the target chip to obtain an output result;
comparing the output result with an expected result to obtain a comparison result;
and judging whether the target chip is qualified or not according to the comparison result.
Further, the obtaining module is further configured to:
before scanning port information is extracted from the test port information of each test vector, splitting each test vector according to a function descriptor to obtain a configuration part and test port information of each test vector;
modifying the configuration part of each test vector respectively;
the processing module is further configured to:
and for any test vector, reconstructing the modified configuration part of the test vector and the scan port information after the test vector compression and format conversion to obtain a target test vector corresponding to the test vector.
For detailed functional description of each module in this embodiment, reference is made to the description of the embodiment of the method, and the detailed description is not provided herein.
Fig. 5 is a schematic diagram of a hardware structure of a test apparatus according to an embodiment of the present invention. As shown in fig. 5, the test apparatus 500 provided in the present embodiment includes: at least one processor 501 and memory 502. The processor 501 and the memory 502 are connected by a bus 503.
In a specific implementation process, the at least one processor 501 executes the computer-executable instructions stored in the memory 502, so that the at least one processor 501 executes the test method in the above method embodiment.
For a specific implementation process of the processor 501, reference may be made to the above method embodiments, which implement the similar principle and technical effect, and this embodiment is not described herein again.
In the embodiment shown in fig. 5, it should be understood that the Processor may be a Central Processing Unit (CPU), other general purpose processors, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present invention may be embodied directly in a hardware processor, or in a combination of the hardware and software modules within the processor.
The memory may comprise high speed RAM memory and may also include non-volatile storage NVM, such as at least one disk memory.
The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended ISA (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, the buses in the figures of the present application are not limited to only one bus or one type of bus.
Another embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored, and when a processor executes the computer-executable instructions, the testing method in the above method embodiment is implemented.
The computer-readable storage medium may be implemented by any type of volatile or non-volatile memory device or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk. Readable storage media can be any available media that can be accessed by a general purpose or special purpose computer.
An exemplary readable storage medium is coupled to the processor such the processor can read information from, and write information to, the readable storage medium. Of course, the readable storage medium may also be an integral part of the processor. The processor and the readable storage medium may reside in an Application Specific Integrated Circuits (ASIC). Of course, the processor and the readable storage medium may also reside as discrete components in the apparatus.
Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A test method is applied to the test of a target chip, and is characterized by comprising the following steps:
obtaining a test vector required by testing the target chip; wherein the number of the test vectors is at least one;
respectively extracting scanning port information from the test port information of each test vector;
according to a preset compression multiple, respectively compressing and format converting the scanning port information of each test vector to obtain a target test vector corresponding to each test vector;
and testing the target chip by adopting the target test vector.
2. The method of claim 1, wherein prior to obtaining the target test vector, the method further comprises:
respectively extracting non-scanning port information from the port information of each test vector; wherein the non-scanning port information and the scanning port information are different;
and carrying out format conversion on the non-scanning port information, or carrying out compression and format conversion on the non-scanning port information.
3. The method of claim 1, wherein any of the test vectors includes description information of input/output states of logic functions; the method for respectively extracting the scanning port information and the non-scanning port information from the test port information of each test vector comprises the following steps:
and aiming at any test vector, extracting scanning port information and non-scanning port information from the port information of the test vector according to the description information of the test vector.
4. The method of any of claims 1-3, wherein the testing the target chip using the target test vector comprises:
inputting the target test vector into the target chip to obtain an output result;
comparing the output result with an expected result to obtain a comparison result;
and judging whether the target chip is qualified or not according to the comparison result.
5. The method of any of claims 1-4, wherein prior to extracting scan port information from the test port information of each of the test vectors, the method further comprises:
according to the function descriptor, splitting each test vector respectively to obtain a configuration part and test port information of each test vector;
modifying the configuration part of each test vector respectively;
according to the preset compression multiple, respectively compressing and format converting the scanning port information of each test vector to obtain a target test vector corresponding to each test vector, including:
and for any test vector, reconstructing the modified configuration part of the test vector and the scan port information after the test vector compression and format conversion to obtain a target test vector corresponding to the test vector.
6. A test apparatus for testing a target chip, comprising:
the acquisition module is used for acquiring a test vector required by testing the target chip; wherein the number of the test vectors is at least one;
the extraction module is used for extracting scanning port information from the test port information of each test vector;
the processing module is used for respectively compressing and converting the scanning port information of each test vector according to a preset compression multiple to obtain a target test vector corresponding to each test vector;
and the test module is used for testing the target chip by adopting the target test vector.
7. The testing device of claim 6, wherein the extraction module is further configured to: before a target test vector is obtained, extracting non-scanning port information from the port information of each test vector; wherein the non-scanning port information and the scanning port information are different;
the processing module is specifically configured to perform format conversion on the non-scanning port information, or perform compression and format conversion on the non-scanning port information.
8. The test apparatus as claimed in claim 6, wherein any one of the test vectors includes description information of input/output states of logic functions; the extraction module is specifically configured to:
and aiming at any test vector, extracting scanning port information and non-scanning port information from the port information of the test vector according to the description information of the test vector.
9. The testing device of any one of claims 6-8, wherein the testing module is specifically configured to:
inputting the target test vector into the target chip to obtain an output result;
comparing the output result with an expected result to obtain a comparison result;
and judging whether the target chip is qualified or not according to the comparison result.
10. The testing device of any one of claims 6-9, wherein the obtaining module is further configured to:
before scanning port information is extracted from the test port information of each test vector, splitting each test vector according to a function descriptor to obtain a configuration part and test port information of each test vector;
modifying the configuration part of each test vector respectively;
the processing module is further configured to:
and for any test vector, reconstructing the modified configuration part of the test vector and the scan port information after the test vector compression and format conversion to obtain a target test vector corresponding to the test vector.
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