CN114325294B - Test method and device - Google Patents
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Abstract
The embodiment of the invention provides a testing method and a testing device, which are applied to testing a target chip, wherein the method comprises the following steps: obtaining a test vector required by testing the target chip; wherein the number of test vectors is at least one; extracting scanning port information from the test port information of each test vector; compressing and format converting the scanning port information of each test vector according to a preset compression multiple to obtain a target test vector corresponding to each test vector; and testing the target chip by adopting the target test vector. According to the embodiment of the invention, the scanning port information is extracted from the port information of the test vector, and the scanning port information part is compressed, so that the test depth of the test vector is reduced, the storage space of the test vector in the ATE is reduced, and the test cost is reduced.
Description
Technical Field
The embodiment of the invention relates to the technical field of integrated circuits, in particular to a testing method and device.
Background
With the continuous development of integrated circuit designs in the nanometer field, the chip performance is more and more powerful. But the increasing number of nano-scale faults and the faster and faster clock of the chip make the design for testability (Design For Testability, DFT) more and more complex. DFT has become the most important ring in designing very large scale integration (Very Large Scale Integration, VLSI) circuits. The most prominent DFT techniques for testing the digital portion of VLSI circuits include scan design techniques and methods of logic built-in self-testing, with scan test techniques being the most widely used.
In the related art, the test method of the chip comprises the following steps: the test vector is converted into a test vector with a specific format required by automatic test equipment (Automatic Test Equipment, ATE) through an automatic test vector generation (Automatic Test Pattern Generation, ATPG) tool, the test vector with the specific format is input into a tested module of the chip by the ATE, and the output result of the tested module is compared with the expected stored result, so that whether the tested module of the chip is qualified or not is judged.
However, the test vectors generated by ATPG are all directly converted into the vectors in the specific format required by the ATE through the conversion tool, so that the test vectors occupy a large memory space of the ATE, thereby resulting in high test cost of the chip.
Disclosure of Invention
The embodiment of the invention provides a testing method and a testing device, which are used for solving the problems of large occupied depth of a measurement vector and chip measurement cost caused by directly converting the test vector through a conversion tool in the prior art.
A first aspect of an embodiment of the present invention provides a testing method, applied to testing a target chip, including:
obtaining a test vector required by testing the target chip; wherein the number of test vectors is at least one;
Extracting scanning port information from the test port information of each test vector;
compressing and format converting the scanning port information of each test vector according to a preset compression multiple to obtain a target test vector corresponding to each test vector;
and testing the target chip by adopting the target test vector.
Optionally, before the obtaining the target test vector, the method further includes:
extracting non-scanning port information from the port information of each test vector respectively; wherein the non-scan port information and the scan port information are different;
and carrying out format conversion on the non-scanning port information, or carrying out compression and format conversion on the non-scanning port information.
Optionally, any one of the test vectors includes description information of input and output states of logic functions; the method for respectively extracting the scanning port information and the non-scanning port information from the test port information of each test vector comprises the following steps:
for any test vector, extracting scanning port information and non-scanning port information from the port information of the test vector according to the description information of the test vector.
Optionally, the testing the target chip with the target test vector includes:
inputting the target test vector into the target chip to obtain an output result;
comparing the output result with an expected result to obtain a comparison result;
and judging whether the target chip is qualified or not according to the comparison result.
Optionally, before extracting scan port information from the test port information of each test vector, the method further includes:
splitting each test vector according to the function descriptor to obtain the configuration part of each test vector and the test port information;
modifying the configuration part of each test vector respectively;
compressing and format converting the scan port information of each test vector according to a preset compression multiple to obtain a target test vector corresponding to each test vector, including:
and reconstructing the configuration part of the test vector after modification and the scan port information of the test vector after compression and format conversion aiming at any test vector to obtain a target test vector corresponding to the test vector.
A second aspect of an embodiment of the present invention provides a testing apparatus, which is applied to a test of a target chip, including:
The acquisition module is used for acquiring a test vector required by testing the target chip; wherein the number of test vectors is at least one;
the extraction module is used for extracting scanning port information from the test port information of each test vector respectively;
the processing module is used for respectively compressing and converting the scanning port information of each test vector according to a preset compression multiple to obtain a target test vector corresponding to each test vector;
and the test module is used for testing the target chip by adopting the target test vector.
Optionally, the extracting module is further configured to: before a target test vector is obtained, non-scanning port information is respectively extracted from the port information of each test vector; wherein the non-scan port information and the scan port information are different;
the processing module is specifically configured to perform format conversion on the non-scanning port information, or perform compression and format conversion on the non-scanning port information.
Optionally, any one of the test vectors includes description information of input and output states of logic functions; the extraction module is specifically used for:
For any test vector, extracting scanning port information and non-scanning port information from the port information of the test vector according to the description information of the test vector.
Optionally, the test module is specifically configured to:
inputting the target test vector into the target chip to obtain an output result;
comparing the output result with an expected result to obtain a comparison result;
and judging whether the target chip is qualified or not according to the comparison result.
Optionally, the acquiring module is further configured to:
before the scanning port information is extracted from the test port information of each test vector, splitting each test vector according to the function descriptor to obtain the configuration part of each test vector and the test port information;
modifying the configuration part of each test vector respectively;
the processing module is further configured to:
and reconstructing the configuration part of the test vector after modification and the scan port information of the test vector after compression and format conversion aiming at any test vector to obtain a target test vector corresponding to the test vector.
The embodiment of the invention provides a testing method and a testing device, which are used for acquiring a testing vector required by testing a target chip; wherein the number of test vectors is at least one; then extracting scanning port information from the test port information of each test vector; compressing and format converting the scanning port information of each test vector according to a preset compression multiple to obtain a target test vector corresponding to each test vector; and finally, testing the target chip by adopting the target test vector. Because the scanning port information is extracted from the testing port information of the testing vector, and the scanning port information occupies most of the whole testing vector space, the scanning port part is compressed, the testing depth of the testing vector is reduced, the storage space occupied by the testing vector in the ATE is reduced, and the testing cost is reduced.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
FIG. 1 is an application scenario diagram of a test method according to an exemplary embodiment of the present invention;
FIG. 2 is a flow chart of a test method according to an exemplary embodiment of the invention;
FIG. 3 is a flow chart of a test method according to another exemplary embodiment of the present invention;
FIG. 3-1 is a schematic diagram illustrating a test vector splitting according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a test apparatus according to an exemplary embodiment of the present invention;
fig. 5 is a schematic structural view of a test apparatus according to an exemplary embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented, for example, in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In the related art, the test method of the chip is that the ATPG tool mainly generates test vectors through scanning test design, and the scanning test mainly tests standard units in the integrated circuit and mainly comprises a shift stage and a capture stage; in the shifting stage, the ATE inputs the test vector to the scanning unit through the scanning port, and then the initialization is carried out according to the test vector, namely, the trigger in the chip is set to be in a preset initial state through the shifting-in and shifting-out of the scanning chain, and the scanning unit shifts to obtain the test value of each beat; and in the capturing stage, capturing the test value onto the trigger to obtain an output value corresponding to the test value.
However, the test vectors generated by the ATPG tool are all vectors in a specific format required by the ATE through the conversion tool, and although the scan test greatly improves the fault coverage rate, the test vectors occupy a large storage space of the ATE, so that the test cost of the chip is high.
Aiming at the defect, the technical scheme of the invention mainly comprises the following steps: according to the structure of the test vector, the test port information of the test vector is divided into the scan port information and the non-scan port information, and the non-scan port is configured and observed through the scan port in the shift stage, so that the non-scan port is kept unchanged, and the shift stage occupies most of the test time of the test vector, and the whole test vector mainly occupies a large space for the scan port information, so that the scan port information and the non-scan port information contained in the test vector are divided, the scan port information is compressed, and the storage space of the test vector can be greatly reduced.
Fig. 1 is an application scenario diagram of a test method of an integrated circuit chip according to an exemplary embodiment of the present invention.
As shown in fig. 1, the basic architecture of the application scenario of the testing method of the integrated circuit chip provided in this embodiment mainly includes: ATPG tool 101, conversion tool 102, ate103, and chip 104; the ATPG tool 101 is used for generating test vectors of various fault models required by testing chips; conversion tool 102 is used to convert test vectors into vectors of a particular format required by ATE 103; ATE103 is configured to scan a chip according to a vector in a specific format to determine whether the chip is acceptable.
FIG. 2 is a flow chart of a method for testing an integrated circuit chip according to an exemplary embodiment of the invention; in connection with the basic architecture diagram shown in FIG. 1, the testing method employed by embodiments of the present invention generally involves the stages of processing test vectors by the conversion tool 102 and ATE103 of FIG. 1.
As shown in fig. 2, the method provided in this embodiment mainly includes the following steps.
S201, obtaining a test vector required by testing the target chip.
Specifically, the test vectors required for testing the target chip can be generated by DFT, and the manner of generating the test vectors by DFT is mainly divided into two main types, namely, generating the test vectors by an ATPG tool through automatic test vectors and generating the test vectors by a built-in self-test MBIST tool of the memory; the test vectors generated by the ATPG tool occupy a large space, and the test vectors generated by the MBIST tool occupy a small space.
Optionally, when the step is implemented, the method mainly aims at a test vector generating tool with large space occupation of the generated test vector, namely the acquired test vector is a test vector generated by an ATPG tool.
In the embodiment of the invention, the number of the test vectors required by the obtained test target chip is at least one; typically, the number of test vectors is a plurality.
S202, respectively extracting scanning port information from the test port information of each test vector.
Specifically, the configuration of the test vector is generally divided into two major parts, namely a configuration part and a test port information part, wherein the configuration part is information for determining fault types, the test frequencies are different, and the test port information part is mainly descriptive information of input and output states of designed logic functions. In a specific application, the test port information part may be represented by patterns 0-n, where patterns 0-n refer to test pattern scan chain information generated according to a fault type, and n represents the number of specific scan chains, which is a positive integer. The test port information part is represented by pattern0-n part as an example, and the processing flow of the measurement vector is introduced; i.e. the test port information section may contain information representing n scan chains.
For the same test problem, a plurality of test vectors can be utilized for testing and verifying, and patterns 0-n of any two test vectors in the plurality of test vectors are identical in part; and, the test frequencies corresponding to different measurement vectors are different, and different test frequencies can be represented by the configuration part in the test vectors.
The testing process of the multi-core chip is a split module testing, and the testing ports used for testing different testing problems of different modules are different. Specifically, for any test vector, all test ports in the any test vector are not used at the same time; for example, when the multi-core chip is tested, corresponding test vectors are generated for problems possibly occurring in different modules, each test vector comprises a plurality of test ports, and functions corresponding to different test ports are different. Therefore, the port splitting can be carried out on the test vector according to the port use condition in the scanning test process.
Specifically, the scan test is divided into two stages, wherein the first stage is a shift stage, and a trigger in the chip is set to be in a preset initial state through the shift in and out of the scan chain; the second stage is a capture stage, capturing the value to be observed onto the trigger. The test port information of the test vector is composed of two parts, namely a scan test input output port part (abbreviated as a scan port) and a non-scan test input output port part (abbreviated as a non-scan port). The scan test input/output port part refers to a port used for shifting a scan chain in and out of a chip in a shift stage of the scan test, and the non-scan test port information refers to a port used for capturing a value to be observed on a trigger in a capture stage of the scan test. In the test process of a test vector, the shift stage is configured and observed through the scanning port, and the shift stage occupies most of test time, so that in the test vector, the mainly used port is the scanning port, and the scanning port occupies most of storage space, and therefore, the test port information of the test vector can be split into the scanning port information and the non-scanning port information. The scan port information is used for characterizing the relevant parameters of the scan port; the non-scan port information is used to characterize the relevant parameters of the non-scan port.
And S203, respectively compressing and converting the scanning port information of each test vector according to a preset compression multiple to obtain a target test vector corresponding to each test vector.
The preset compression multiple can be determined according to the number of time frames of Automatic Test Equipment (ATE) of the test chip. For example, a typical ATE contains 8 time frames, and if 4 time frames are required for scan port information for any one test vector, the scan port information is maximally compressible by a factor of two, i.e., a compression factor of maximally 2.
Specifically, for any test vector, since the scan port information of the test vector occupies most of the space of the whole test vector, the scan port of the test vector can be compressed and converted according to a preset compression multiple, so that the storage space occupied by the test vector can be greatly reduced. The format conversion refers to converting the test vector into a format that can be directly used by ATE. Optionally, for all test vectors of the target chip, the scan port information of all test vectors may be compressed by using the same preset compression multiple; or, for all the test vectors of the target chip, respectively compressing the scan port information of each test vector by using different preset compression multiples according to the specific condition of each test vector.
For example, the cpu ip_tf is a test vector, the scan port information of the cpu ip_tf test vector occupies 98% of the space occupied by the cpu ip_tf test vector, the non-scan port information occupies 2% of the space occupied by the cpu ip_tf test vector, and if the predetermined compression multiple is 2 times, the scan port information is compressed, the cpu ip_tf test vector may be compressed to be 51%, and the space occupied by the compressed cpu ip_tf test vector is reduced by 49%.
S204, testing the target chip by adopting the target test vector.
Specifically, inputting the target test vector into the target chip to obtain an output result; and comparing the output result with an expected result to judge whether the target chip is qualified or not. The target test vector comprises at least one test vector subjected to compression and format conversion.
In this embodiment, the scan port information and the non-scan port information in the test vector are extracted and divided, and the scan port information is compressed, so that the test depth of the whole test vector is greatly reduced, the occupation space of the test vector is reduced, and the cost of chip testing is further reduced.
Fig. 3 is a flow chart of a testing method of an integrated circuit chip according to another exemplary embodiment of the present invention, and the testing method of the integrated circuit chip according to this embodiment is further described in detail on the basis of the embodiment shown in fig. 2.
As shown in fig. 3, the method provided in this embodiment mainly includes the following steps.
S301, DFT generates a test vector.
Specifically, when testing a chip, the mode of generating test vectors through DFT is mainly divided into two main types, namely, generating test vectors through an ATPG tool by using an automatic test vector and generating test vectors through a built-in self-test MBIST tool of a memory; the test vectors generated by the ATPG tool occupy a large space, and the test vectors generated by the MBIST tool occupy a small space.
In this embodiment, the test vectors generated by the ATPG tool are mainly considered, and because the current testing method of the multi-core chip is mainly a split module test, the test vectors generated by the ATPG tool mainly include several test vectors of SA, TF, BF, PD, and the like according to the type of the tested fault, wherein the test vectors with large occupied space are mainly TF and PD.
For example, four cores are taken as an example, and four cores are respectively CPU ip0, CPU ip1, CPU ip2 and CPU ip3, and vectors generated for each core include three test vectors of PD, TF, and SA (express and internal). As shown in table 1, for convenience of description, only two test vectors, i.e., PD and TF, corresponding to the four cores, respectively, are listed in table 1, and as can be seen from table 1, the TF test vector of the CPU occupies 25.964M.
It should be noted that, the chip tested in this embodiment is a multi-core chip; for isomorphic cores in the multi-core chip, storing information of a plurality of test vectors corresponding to a target core; the target core is any one of isomorphic cores, wherein the isomorphic cores are identical in structure of processor cores of the chips and identical in trigger pins; for the multi-core chip with the isomorphic core, because the processor cores of the isomorphic core have the same structure and the trigger pins are the same, the test vectors of the isomorphic core corresponding to the same test problem are the same; when the isomorphic cores are stored, only one processor core is selected from the isomorphic cores, and only the test vector of any selected processor core is stored, so that the space occupied by the test vector is further reduced.
TABLE 1
| Pattern_name (CPU IP Module) | Mem_Used | unit(M) |
| XX_CPUIP0_PD_Internal_Pass1 | 546480 | 0.52116394 |
| XX_CPUIP2_PD_Internal_Pass1 | 546480 | 0.52116394 |
| XX_CPUIP1_PD_Internal_Pass1 | 546480 | 0.52116394 |
| XX_CPUIP3_PD_Internal_Pass1 | 546480 | 0.52116394 |
| XX_CPUIP0_TF_Compress_Pass1 | 6259992 | 5.969993591 |
| XX_CPUIP2_TF_Compress_Pass1 | 6259992 | 5.969993591 |
| XX_CPUIP1_TF_Compress_Pass1 | 6259992 | 5.969993591 |
| XX_CPUIP3_TF_Compress_Pass1 | 6259992 | 5.969993591 |
The first column in Table 1 is the names of the pattern 0-n parts in each test vector, the second column is the memory size occupied by the pattern 0-n parts in each test vector, and the third column is the space size occupied by the pattern 0-n parts in each test vector.
S302, dividing the test port information of each test vector to obtain the scan port information and the non-scan port information of each test vector.
Specifically, each test vector includes description information of input/output states of logic functions (hereinafter referred to as description information); for any one of the above-mentioned test vectors (hereinafter referred to as test vector a), the test port information of the test vector a is divided according to the above-mentioned description information contained in the test vector a, and the scan port information and the non-scan port information of the test vector a are obtained.
In one embodiment, all test vectors acquire scan port information and non-scan port information in the manner of test vector a: each port information in the test vector A corresponds to descriptive information, when the test vector A is used for scanning and testing a certain module in the chip, which ports are used for moving in and out a scanning chain in a shifting stage, and which ports are used for capturing an observed value in a trigger in a capturing stage are distributed according to the descriptive information contained in the test vector A; for example, the description information corresponding to the first port in the test vector a includes "setting a trigger state", which indicates that the first port is a port used for moving the scan chain into and out of the detection module in the shift stage, and then the first port is divided into scan ports; if the description information of the "capture observation value" is included in the function description corresponding to the second port in the test vector a, which indicates that the second port is a port used by a trigger that captures the observation value to the detection module in the capture stage, the second port is divided into non-scanning ports.
Further, before step 302, each test vector may be divided according to the function descriptor, that is, the test vector is divided into two major parts, namely, a configuration part and test port information (patterns 0-n), wherein the test port information is mainly a description of the input/output states of the designed logic function. The test port information of the test vector is composed of two parts, namely a scan test input output port part (abbreviated as scan port information) and a non-scan test input output port part (abbreviated as non-scan port information). Specifically, fig. 3-1 is a schematic diagram of splitting a test vector according to an embodiment of the present application, and as can be seen from fig. 3-1, the test vector is split into a configuration portion and a pattern0-n portion, and the pattern0-n portion is split into scan port information and non-scan port information.
The function descriptors are used for identifying functions corresponding to various parameters in any test vector. For example, for any test vector, two kinds of function descriptors, namely a function descriptor a and a function descriptor B, respectively, where the function descriptor a represents a configuration part, and the function descriptor B represents a pattern0-n part; the test vector comprises a parameter 1, a parameter 2, a parameter 3, a parameter 4 and a parameter 5, wherein the function descriptors corresponding to the parameter 1 are A, the function descriptors corresponding to the parameter 1 and the parameter 2 are A, and the function descriptors corresponding to the parameter 3, the parameter 4 and the parameter 5 are B; it follows that both parameter 1 and parameter 2 belong to the configuration section, and that parameters 3 to 5 belong to the pattern section. Here, only an exemplary case is shown, and the number of parameters included in any test vector in the actual application will be greater than that in the above example.
In some embodiments, the test port information of the test vector may also be split according to the primary usage port information and the non-primary usage port information.
In this embodiment, in order to minimize the vector space, the test port information of the test vector is generally split into scan port information and non-scan port information.
And S303, respectively compressing and format converting the scanning port information of each test vector according to a preset compression multiple, and performing format conversion on the non-scanning port information or performing format conversion after compressing to obtain a target test vector corresponding to each test vector.
The preset compression multiple may be determined according to the number of time edges of the automatic test equipment for testing the chip, for example, may be set to 2 times, 3 times, or 4 times, etc.
Specifically, since the scan port of the test vector occupies most of the space of the whole test vector, the scan port of the test vector can be compressed, so that the storage space occupied by the test vector can be greatly reduced. Because the non-scanning port occupies a small space, the non-scanning port can be directly subjected to format conversion without compression.
Optionally, SCAN PORT (SCAN PORT) information and non-SCAN PORT (NOSCAN PORT) information of the test vector are defined by pin list (pinlist), such as: scan_port= '…'; noscan_port= '…'.
It can be understood that, for any test vector a, since the description information of each port in the test vector a is logic function description information, the related personnel divide the test vector a into scan port information and non-scan port information according to the function description information, and when all scan port information or non-scan port information is acquired to compress and convert the format of the test vector a, the test vector a also needs to acquire the test vector a according to the function description information of each port, but the function description information of each port is different, and when the scan port is compressed and converted in format, a section of compression and format conversion code needs to be defined for each scan port. In this step, the scan port and the non-scan port are defined by the pin list, so that when the scan port information and the non-scan port information are compressed and converted in format, compression and format conversion parameters are set respectively directly by the pin list definitions corresponding to the scan port information and the non-scan port information. All the scanning port information and the non-scanning port information can be rapidly obtained through the pin list definition of the scanning port information and the non-scanning port information, so that the time is saved and the efficiency is improved.
Optionally, referring to fig. 3-1, compressing the pattern 0-n portion includes: and carrying out first compression processing on the scanning port information in the pattern 0-n part, and carrying out second compression processing on the non-scanning port information in the pattern 0-n part, wherein the compression multiple adopted by the second compression processing is larger than that adopted by the first compression processing. In the embodiment, the pattern 0-n part of the test vector is divided into the scanning port information and the non-scanning port information, the non-scanning part with small influence on the test result is compressed in a multiple way, and the scanning part is compressed in a multiple way, so that the accuracy of the test result is further improved, and the space occupied by the test vector is saved.
Further, the configuration part of each test vector is modified respectively; and reconstructing the configuration part of the test vector after modification and the scan port information of the test vector after compression and format conversion aiming at any test vector to obtain a target test vector corresponding to the test vector. The modification to the test vector configuration part refers to modification to the configuration file, for example, modification to the identifier of the processor core, and modification to the processor core No. 0 to the processor core No. 2.
Optionally, for any test vector, reconstructing the configuration portion modified by the test vector and the scan port information compressed and converted by the test vector includes: and aiming at any test vector, splicing the configuration part modified by the test vector and the scan port information after compression and format conversion in a preset mode, and synthesizing and updating the test vector.
For example, assume that any one test vector a contains n scan ports (denoted as a respectively 1 、A 2 …A n ) Information, m non-scanning ports (denoted as B respectively 1 、B 2 …B m ) Information, when compressing and format converting each port, the following information needs to be defined:
"A 1 _Port""A 1 _Port_PT,Sync,1,2"；
…
"A n _Port""A n _Port_PT,Sync,1,2"；
"B 1 _Port""B 1 _Port,Sync,1,1"；
…
"B m _Port""B m _Port,Sync,1,1"。
in this step, after defining SCAN PORT (SCAN PORT) information and non-SCAN PORT (NOSCAN PORT) information of the test vector a with a pin list (pinlist), setting a preset compression multiple to 2 times, compressing and converting the SCAN PORT information of the test vector a, and directly converting the non-SCAN PORT information, which can be realized by the following modes:
"Scan_Port""Scan_Port_PT,Sync,1,2"；
"NOScan_Port""NOScan_Port,Sync,1,1"。
wherein, 2 in "Sync,1,2" represents that the compression multiple is 2 times, and "Sync,1,2" represents that the scan port information is compressed to be one half of the original. "Sync, 1" means that the compression multiple of the non-scan port information is 1 time, i.e., not compressed.
In one possible embodiment, not only the scan port information but also the non-scan port information may be compressed, and the compression multiple may be determined according to the actual situation.
It should be noted that the format of the test vector generated by DFT mainly includes four types: STIL, VCD, EVCD, WGL. However, the test vectors in the four formats cannot be directly used in an ATE machine, and the test vectors need to be converted into the vectors in the specific formats required by the machine.
S304, inputting the target test vector into a unit to be tested in the target chip to obtain an output result.
S305, comparing the output result with an expected result to judge whether the unit to be tested in the target chip is qualified or not.
In this embodiment, the scan port and the non-scan port in the port portion of the test vector are divided, so that the scan port is compressed, thereby greatly reducing the test depth of the whole test vector, reducing the occupation space of the test vector, and further reducing the cost of chip testing.
Fig. 4 is a schematic structural view of a test apparatus according to an exemplary embodiment of the present invention.
As shown in fig. 4, the apparatus provided in this embodiment includes: an acquisition module 401, an extraction module 402, a processing module 403 and a test module 404; the acquiring module 401 is configured to acquire a test vector required for testing the target chip; wherein the number of test vectors is at least one; an extracting module 402, configured to extract scan port information from the test port information of each test vector; the processing module 403 is configured to compress and format-convert the scan port information of each test vector according to a preset compression multiple, so as to obtain a target test vector corresponding to each test vector; and the test module 404 is configured to test the target chip by using the target test vector.
Further, the extraction module is further configured to: before a target test vector is obtained, non-scanning port information is respectively extracted from the port information of each test vector; wherein the non-scan port information and the scan port information are different;
the processing module is specifically configured to perform format conversion on the non-scanning port information, or perform compression and format conversion on the non-scanning port information.
Further, any one of the test vectors includes description information of input and output states of logic functions; the extraction module is specifically used for:
for any test vector, extracting scanning port information and non-scanning port information from the port information of the test vector according to the description information of the test vector.
Further, the test module is specifically configured to:
inputting the target test vector into the target chip to obtain an output result;
comparing the output result with an expected result to obtain a comparison result;
and judging whether the target chip is qualified or not according to the comparison result.
Further, the obtaining module is further configured to:
before the scanning port information is extracted from the test port information of each test vector, splitting each test vector according to the function descriptor to obtain the configuration part of each test vector and the test port information;
Modifying the configuration part of each test vector respectively;
the processing module is further configured to:
and reconstructing the configuration part of the test vector after modification and the scan port information of the test vector after compression and format conversion aiming at any test vector to obtain a target test vector corresponding to the test vector.
For a detailed description of the function of each module in this embodiment, reference is made to the description of the embodiment of the method, and detailed description thereof will not be provided herein.
Fig. 5 is a schematic hardware structure of a test apparatus according to an embodiment of the present invention. As shown in fig. 5, the test apparatus 500 provided in this embodiment includes: at least one processor 501 and a memory 502. The processor 501 and the memory 502 are connected by a bus 503.
In a specific implementation, at least one processor 501 executes computer-executable instructions stored in the memory 502, so that at least one processor 501 executes the test method in the above method embodiment.
The specific implementation process of the processor 501 may refer to the above-mentioned method embodiment, and its implementation principle and technical effects are similar, and this embodiment will not be described herein again.
In the embodiment shown in fig. 5, it should be understood that the processor may be a central processing unit (english: central Processing Unit, abbreviated as CPU), or may be other general purpose processors, digital signal processors (english: digital Signal Processor, abbreviated as DSP), application specific integrated circuits (english: application Specific Integrated Circuit, abbreviated as ASIC), or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present invention may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in a processor for execution.
The memory may comprise high speed RAM memory or may further comprise non-volatile storage NVM, such as at least one disk memory.
The bus may be an industry standard architecture (Industry Standard Architecture, ISA) bus, an external device interconnect (Peripheral Component Interconnect, PCI) bus, or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, among others. The buses may be divided into address buses, data buses, control buses, etc. For ease of illustration, the buses in the drawings of the present application are not limited to only one bus or one type of bus.
Another embodiment of the present application provides a computer readable storage medium having stored therein computer executable instructions that, when executed by a processor, implement the test method in the above method embodiments.
The computer readable storage medium described above may be implemented by any type of volatile or non-volatile memory device or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk. A readable storage medium can be any available medium that can be accessed by a general purpose or special purpose computer.
An exemplary readable storage medium is coupled to the processor such the processor can read information from, and write information to, the readable storage medium. In the alternative, the readable storage medium may be integral to the processor. The processor and the readable storage medium may reside in an application specific integrated circuit (Application Specific Integrated Circuits, ASIC for short). The processor and the readable storage medium may reside as discrete components in a device.
Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the method embodiments described above may be performed by hardware associated with program instructions. The foregoing program may be stored in a computer readable storage medium. The program, when executed, performs steps including the method embodiments described above; and the aforementioned storage medium includes: various media that can store program code, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (10)
1. The test method is applied to the test of the target chip and is characterized by comprising the following steps:
obtaining a test vector required by testing the target chip; wherein the number of test vectors is at least one;
extracting scanning port information from the test port information of each test vector respectively, wherein the part of the whole test vector space occupied by the scanning port information is larger than the part of the whole test vector space occupied by the non-scanning port information;
compressing and converting the scanning port information of each test vector according to a preset compression multiple to obtain a target test vector corresponding to each test vector;
testing the target chip by adopting the target test vector;
when the scanning ports are compressed and converted in format, the scanning ports and the non-scanning ports are defined through a pin list so as to respectively set compression and format conversion parameters; the compression multiple adopted for the compression treatment of the scanning port is larger than that adopted for the compression treatment of the non-scanning port, and the compression multiple and the compression degree are in direct proportion.
2. The method of claim 1, wherein prior to obtaining the target test vector for each of the test vectors, the method further comprises:
Extracting non-scanning port information from the port information of each test vector; wherein the non-scan port information and the scan port information are different;
and carrying out format conversion on the non-scanning port information, or carrying out compression and format conversion on the non-scanning port information.
3. The method of claim 1, wherein any one of the test vectors includes information describing input/output states of logic functions; the method for respectively extracting the scanning port information and the non-scanning port information from the test port information of each test vector comprises the following steps:
and for any test vector, extracting scanning port information and non-scanning port information from the port information of the test vector according to the description information of the test vector.
4. A method according to any of claims 1-3, wherein said testing said target chip with said target test vector comprises:
inputting the target test vector into the target chip to obtain an output result;
comparing the output result with an expected result to obtain a comparison result;
and judging whether the target chip is qualified or not according to the comparison result.
5. The method of any of claims 1-4, wherein prior to extracting scan port information from the test port information for each of the test vectors, respectively, the method further comprises:
splitting each test vector according to the function descriptor to obtain the configuration part of each test vector and the test port information;
modifying the configuration part of each test vector respectively;
compressing and format converting the scan port information of each test vector according to a preset compression multiple to obtain a target test vector corresponding to each test vector, wherein the method comprises the following steps:
and reconstructing the configuration part of the test vector after modification and the scan port information of the test vector after compression and format conversion aiming at any test vector to obtain a target test vector corresponding to the test vector.
6. A test apparatus for testing a target chip, comprising:
the acquisition module is used for acquiring a test vector required by testing the target chip; wherein the number of test vectors is at least one;
the extraction module is used for respectively extracting scanning port information from the test port information of each test vector, and the part of the whole test vector space occupied by the scanning port information is larger than the part of the whole test vector space occupied by the non-scanning port information;
The processing module is used for respectively compressing and converting the scanning port information of each test vector according to a preset compression multiple to obtain a target test vector corresponding to each test vector;
the test module is used for testing the target chip by adopting the target test vector;
when the scanning ports are compressed and converted in format, the scanning ports and the non-scanning ports are defined through a pin list so as to respectively set compression and format conversion parameters; the compression multiple adopted for the compression treatment of the scanning port is larger than that adopted for the compression treatment of the non-scanning port, and the compression multiple and the compression degree are in direct proportion.
7. The test device of claim 6, wherein the extraction module is further configured to: before the target test vector corresponding to each test vector is obtained, non-scanning port information is extracted from the port information of each test vector; wherein the non-scan port information and the scan port information are different;
the processing module is specifically configured to perform format conversion on the non-scanning port information, or perform compression and format conversion on the non-scanning port information.
8. The test device of claim 6, wherein any one of the test vectors includes description information of input/output states of logic functions; the extraction module is specifically used for:
and for any test vector, extracting scanning port information and non-scanning port information from the port information of the test vector according to the description information of the test vector.
9. The test device according to any one of claims 6-8, wherein the test module is specifically configured to:
inputting the target test vector into the target chip to obtain an output result;
comparing the output result with an expected result to obtain a comparison result;
and judging whether the target chip is qualified or not according to the comparison result.
10. The test device of any one of claims 6-9, wherein the acquisition module is further configured to:
before the scan port information is extracted from the test port information of each test vector, splitting each test vector according to a function descriptor to obtain each test vector configuration part and test port information;
modifying the configuration part of each test vector respectively;
The processing module is further configured to:
and reconstructing the configuration part of the test vector after modification and the scan port information of the test vector after compression and format conversion aiming at any test vector to obtain a target test vector corresponding to the test vector.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101158706A (en) * | 2007-11-16 | 2008-04-09 | 哈尔滨工业大学 | Large scale integrated circuit test data and method for testing power consumption cooperate optimization |
| WO2013016989A1 (en) * | 2011-07-29 | 2013-02-07 | Tsinghua University | Test stimuli compression and test response compaction in low-power scan testing |
| CN110687437A (en) * | 2019-09-03 | 2020-01-14 | 天津大学 | Optimization method for scan test compression |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7673204B2 (en) * | 2007-07-05 | 2010-03-02 | International Business Machines Corporation | Method using non-linear compression to generate a set of test vectors for use in scan testing an integrated circuit |
| US8527821B2 (en) * | 2009-04-13 | 2013-09-03 | Texas Instruments Incorporated | Hybrid test compression architecture using multiple codecs for low pin count and high compression devices |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101158706A (en) * | 2007-11-16 | 2008-04-09 | 哈尔滨工业大学 | Large scale integrated circuit test data and method for testing power consumption cooperate optimization |
| WO2013016989A1 (en) * | 2011-07-29 | 2013-02-07 | Tsinghua University | Test stimuli compression and test response compaction in low-power scan testing |
| CN110687437A (en) * | 2019-09-03 | 2020-01-14 | 天津大学 | Optimization method for scan test compression |
Non-Patent Citations (1)
| Title |
|---|
| 多核处理器可测性设计及其ATE实现;张鹏;《中国优秀硕士学位论文全文数据库信息科技辑》;46-60 * |
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